Re: Possible bug in linux-6.2/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c

2023-02-26 Thread Michael Ellerman
David Binderman writes: > Hello there, > > I ran the static analyser cppcheck over the linux-6.2 source code and got > this: > > linux-6.2/tools/testing/selftests/powerpc/pmu/sampling_tests/mmcra_thresh_marked_sample_test.c:68:10: > style: Same expression '0x3' found multiple times in chain of

Re: [PATCH v7 5/5] powerpc/64s: enable MMU_LAZY_TLB_SHOOTDOWN

2023-02-26 Thread Andrew Morton
On Fri, 3 Feb 2023 17:18:37 +1000 Nicholas Piggin wrote: > On a 16-socket 192-core POWER8 system, the context_switch1_threads > benchmark from will-it-scale (see earlier changelog), upstream can > achieve a rate of about 1 million context switches per second, due to > contention on the mm

Re: [PATCH mm-unstable v1 11/26] microblaze/mm: support __HAVE_ARCH_PTE_SWP_EXCLUSIVE

2023-02-26 Thread Geert Uytterhoeven
Hi David, On Fri, Jan 13, 2023 at 6:16 PM David Hildenbrand wrote: > Let's support __HAVE_ARCH_PTE_SWP_EXCLUSIVE by stealing one bit > from the type. Generic MM currently only uses 5 bits for the type > (MAX_SWAPFILES_SHIFT), so the stolen bit is effectively unused. > > The shift by 2 when

Re: [PATCH v6 01/10] dt-bindings: soc: fsl: cpm_qe: Add TSA controller

2023-02-26 Thread Rob Herring
On Fri, Feb 17, 2023 at 03:56:36PM +0100, Herve Codina wrote: > Add support for the time slot assigner (TSA) > available in some PowerQUICC SoC such as MPC885 > or MPC866. > > Signed-off-by: Herve Codina > --- > .../bindings/soc/fsl/cpm_qe/fsl,cpm1-tsa.yaml | 215 ++ >