In the case we miss to bring up some cpus, we need to make sure we can
find the correct cpu nodes in the device tree based on the given logical
cpu index from the caller.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/iommu/fsl_pamu.c |3 ++-
1 files changed, 2 insertions
On Wed, 2012-03-07 at 13:20 +0800, Shengzhou Liu wrote:
From: Liu Shuo shuo@freescale.com
Fix the compatible string of sec 4.0 to match with CAMM driver according
%s/CAMM/CAAM.
Haiying
to Documentation/devicetree/bindings/crypto/fsl-sec4.txt
Signed-off-by: Liu Shuo
On Fri, 2010-03-09 at 10:05 +0300, Ioannis Kokkoris wrote:
We are using a board revision 2 (pilot version). Our main concern is whether
this issue affects the working UCC1 eth interface performance.
No, it won't affect the performance. We got line rate for performance
for UECs on this board.
On Thu, 2010-02-09 at 11:26 +0300, Ioannis Kokkoris wrote:
From: johnko...@hotmail.com
To: linuxppc-dev@lists.ozlabs.org
Subject: P1021MDS QE Ethernet Ports
Date: Wed, 1 Sep 2010 15:11:56 +0300
Hello,
we are seeing a strange behavior when trying to use the QE Ethernet
P1021 is a dual e500v2 core based SOC with:
* 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board)
* 2 PCIe Controller
* 1 USB2.0 controller
* eSDHC, eSPI, I2C, DUART
* eLBC (NAND, BCSR, PMC0/1)
* Security Engine (SEC 3.3.2)
* Quicc Engine (QE)
Signed-off-by: Haiying Wang haiying.w
P1021 is a dual e500v2 core based SOC with:
* 3 eTSECs (eTSEC1/3 RGMII, eTSEC2 SGMII on this board)
* 2 PCIe Controller
* 1 USB2.0 controller
* eSDHC, eSPI, I2C, DUART
* eLBC (NAND, BCSR, PMC0/1)
* Security Engine (SEC 3.3.2)
* Quicc Engine (QE)
Signed-off-by: Haiying Wang haiying.w
On Mon, 2009-06-01 at 02:51 -0700, David Miller wrote:
Patch 3 of this series doesn't apply cleanly to net-next-2.6
so I'm dropping the entire patch set.
Also, in patch 3 you put your signoff in the Subject line.
Please fix all of this up and resubmit your patch series.
I only verified the
Disable fiber/copper auto selection for Marvell m88e SGMII support.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/net/phy/marvell.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/drivers/net/phy/marvell.c b/drivers/net/phy/marvell.c
index
unproperly, e.g. can not get the right clock. Normally the primary mdio bus is
the first UEC's mdio bus.
This patch allows the first UCC to be the MII management interface master of the
multiple UCC mdio buses.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/net/fsl_pq_mdio.c
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/include/asm/qe.h |2 +
drivers/net/ucc_geth.c| 79 -
drivers/net/ucc_geth.h| 28 ++-
3 files changed, 107 insertions(+), 2 deletions(-)
diff --git
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/boot/dts/mpc8569mds.dts | 63 ++
1 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts
b/arch/powerpc/boot/dts/mpc8569mds.dts
index 39c2927
unproperly, e.g. can notget the right clock. Normally the primary mdio bus is
the first UEC's mdio bus.
This patch allows the first UCC to be the MII management interface master of the
multiple UCC mdio buses.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/net/fsl_pq_mdio.c
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/boot/dts/mpc8569mds.dts | 63 ++
1 files changed, 63 insertions(+), 0 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8569mds.dts
b/arch/powerpc/boot/dts/mpc8569mds.dts
index 39c2927
Change the RISC allocation to macros instead of enum, add function to read the
number of risc engines from the new property fsl,qe-num-riscs under qe node
in dts. Add new property fsl,qe-num-riscs description in qe.txt
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: rename
in the case the QE has 46 SNUMs for the threads to support four UCC Ethernet at
1000Base-T simultaneously.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: Add comments for the Rx threads change.
drivers/net/ucc_geth.c | 10 +-
1 files changed, 9 insertions(+), 1
property. The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum
table which is 256.
Also we update the snum_init[] array with 18 more new SNUMs which are
confirmed to be useful on new chip.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: rename the new property
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
v2 change: rename num-riscs to fsl,qe-num-riscs, and num-snums to
fsl,qe-num-snums.
arch/powerpc/boot/dts/mpc8569mds.dts | 514 +
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 23 ++
2 files changed
Add fsl,qe-num-riscs and fsl,qe-num-snums to all the devices trees which have qe
node.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/boot/dts/mpc832x_mds.dts |2 ++
arch/powerpc/boot/dts/mpc832x_rdb.dts |2 ++
arch/powerpc/boot/dts/mpc836x_mds.dts |2
when there are 46 snums defined in device tree.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/net/ucc_geth.c |5 -
1 files changed, 4 insertions(+), 1 deletions(-)
diff --git a/drivers/net/ucc_geth.c b/drivers/net/ucc_geth.c
index 3e003fe..1f6529f 100644
property.
The macro QE_NUM_OF_SNUM is defined as the maximum number in QE snum table which
is 256.
Also we update the snum_init[] array with 18 more new SNUMs which are
confirmed to be useful on new chip.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
.../powerpc/dts-bindings/fsl/cpm_qe
Keep an unique machine def for the MPC8568 MDS board to handle some
subtle differences between the future MDS board. Also set the bcsrs in
setup_arch() only for mpc8568_mds because other mds has different bcsr settings.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
arch/powerpc/boot/dts/mpc8569mds.dts | 514 +
arch/powerpc/platforms/85xx/mpc85xx_mds.c | 23 ++
2 files changed, 537 insertions(+), 0 deletions(-)
create mode 100644 arch/powerpc/boot/dts
Change the RISC allocation to macros instead of enum, add function to read the
number of risc engines from the new property num-riscs under qe node in dts.
Add new property num-riscs description in qe.txt
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
.../powerpc/dts-bindings/fsl
Change the definition of riscTx and riscRx to unsigned integer instead of enum,
and change their values to support 4 risc allocation if the qe has 4 RISC
engines.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/net/ucc_geth.c | 14 +++---
drivers/net/ucc_geth.h
. This patch changes uec's phy id to
the same
format as gianfar's.
Signed-off-by: Haiying Wang haiying.w...@freescale.com
---
drivers/net/ucc_geth.c | 20 ++--
drivers/net/ucc_geth.h |2 ++
drivers/net/ucc_geth_mii.c | 12 +++-
drivers/net
On Thu, 2009-01-22 at 06:37 -0800, wael showair wrote:
m...@24520 {
#address-cells = 1;
#size-cells = 0;
device_type = mdio;
compatible = gianfar;
reg = 24520 20;
MPC8568E has 64K byte MURAM, so the size should be 0x1, not 0xc000 in dts.
Signed-off-by: Haiying Wang [EMAIL PROTECTED]
---
arch/powerpc/boot/dts/mpc8568mds.dts |4 ++--
1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/powerpc/boot/dts/mpc8568mds.dts
b/arch/powerpc
8540 doesn't have RSTCR register. You should not use fsl_rstcr_restart
for reboot your 8540 board.
Haiying
On Tue, 2008-03-25 at 17:15 +0100, Philippe De Muyter wrote:
Hi all,
I have a mpc8540 board that could reboot when driven by a ARCH=ppc linux,
but that hangs now in
+ abort();
while (1) ;
}
#endif
I don't have 8540 board to test.
Haiying
On Tue, 2008-03-25 at 21:20 +0100, Philippe De Muyter wrote:
Hi Haiying,
On Tue, Mar 25, 2008 at 12:34:55PM -0400, Haiying Wang wrote:
8540 doesn't have RSTCR register. You should not use
On Wed, 2008-01-09 at 00:06 -0500, mike zheng wrote:
Hi All,
I have one mpc8568 board using UART1 as the serial port. The OS is
Linux Kernel2.4. If I use the polling mode driver of
gen550_progress(), it works fine. However the printk() does not work
after the console_init(). Anyone
On Thu, 2007-09-20 at 13:16 -0500, Timur Tabi wrote:
Anton Vorontsov wrote:
I don't know (didn't look) why this works for 83xx w/o ack()...
maybe IPIC don't need this. Or maybe there is a bug hiding.
Scott W told me that me that the IPIC doesn't have the concept of EOI ack.
It
just
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