On Jul 10, 2012, at 5:22 AM, Xie Shaohui-B21989 wrote:
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
As commented, we should use PPC_FSL_BOOK3E, not CONFIG_PPC_FSL_BOOK3E.
- k
-Original Message-
From: Xie
On Jul 10, 2012, at 6:40 AM, Kumar Gala wrote:
On Jul 10, 2012, at 5:22 AM, Xie Shaohui-B21989 wrote:
Hi, All,
Is there any concern for this patch, it's been a long time.
Thanks!
Best Regards,
Shaohui Xie
As commented, we should use PPC_FSL_BOOK3E, not CONFIG_PPC_FSL_BOOK3E
shaohui@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
arch/powerpc/configs/corenet32_smp_defconfig | 22 +-
1 files changed, 21
PCI-E support
Signed-off-by: Haiying Wang haiying.w...@freescale.com
Signed-off-by: Laurentiu Tudor laurentiu.tu...@freescale.com
Signed-off-by: Harninder Rai harninder@freescale.com
Signed-off-by: Minghuan Lian minghuan.l...@freescale.com
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
On Jul 10, 2012, at 4:39 AM, Sethi Varun-B16395 wrote:
-Original Message-
From: Kumar Gala [mailto:ga...@kernel.crashing.org]
Sent: Tuesday, July 10, 2012 7:17 AM
To: Wood Scott-B07421
Cc: Sethi Varun-B16395; Hamciuc Bogdan-BHAMCIU1; linuxppc-
d...@lists.ozlabs.org
Subject: Re
On Jul 10, 2012, at 3:39 AM, Xu Jiucheng wrote:
P1021RDB-PC Overview
-
1Gbyte DDR3 (on board DDR)
16Mbyte NOR flash
32Mbyte eSLC NAND Flash
256 Kbit M24256 I2C EEPROM
128 Mbit SPI Flash memory
Real-time clock on I2C bus
SD/MMC connector to interface with the SD memory
We need to use CONFIG_FSL_SOC_BOOKE instead of CONFIG_PPC_85xx as
CONFIG_PPC_85xx isn't defined when we build support for 64-bit embedded
FSL PPC SoCs.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
drivers/usb/host/ehci-fsl.c |2 +-
1 files changed, 1 insertions(+), 1 deletions
On Feb 29, 2012, at 7:20 PM, Olivia Yin wrote:
From: Liu Yu yu@freescale.com
So that we can call it when improving SPE switch like book3e did for fp
switch.
Signed-off-by: Liu Yu yu@freescale.com
Signed-off-by: Olivia Yin hong-hua@freescale.com
---
v2: add Signed-off-by
On Jul 9, 2012, at 3:46 AM, Varun Sethi wrote:
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
This prevents us from eating in to hardware vector number space (MSIs)
while setting up internal sources.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
On May 11, 2012, at 12:33 AM, Shaohui Xie wrote:
CONFIG_FSL_BOOKE is only defined in 32-bit, CONFIG_PPC_FSL_BOOK3E is
defined in both 32-bit and 64-bit, so use CONFIG_PPC_FSL_BOOK3E to make
driver work in 32-bit 64-bit.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
changes
On Jul 10, 2012, at 1:08 AM, Jia Hongtao wrote:
The issue log on core1 is:
root@mpc8572ds:~# ifconfig eth0 10.192.208.244
net eth0: could not attach to PHY
SIOCSIFFLAGS: No such device
To attach PHY node mdio@24520 should not be disabled in dts of core1.
Because all PHYs are controlled
On Jul 10, 2012, at 1:08 AM, Jia Hongtao wrote:
With 2-cell format interrupts of MSI PCIe ethernet card can not work.
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Jia Hongtao b38...@freescale.com
---
arch/powerpc/boot/dts/mpc8572ds_camp_core0.dts |8
On Nov 11, 2011, at 10:05 AM, Kokoris, Ioannis wrote:
Hi,
QE Microcode Initialization using qe_upload_microcode() does not work on
P1021 if the IRAM-Ready register is not set after the microcode upload. This
patch adds a definition for the I-RAM Ready register and sets it uppon
On Jul 10, 2012, at 2:52 AM, Zhicheng wrote:
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/boot/dts/fsl/p1021si-post.dtsi | 16 ++-
arch/powerpc/boot/dts/p1025rdb.dtsi | 40 +++
2 files
On Mar 30, 2012, at 12:38 AM, Shawn Guo wrote:
Freescale PowerPC SoCs share a number of IP blocks with Freescale
ARM/IMX SoCs, FlexCAN, SSI, FEC, eSDHC, USB, etc. There are some
effort consolidating those drivers to make them work for both
architectures.
One outstanding difference
On Jul 10, 2012, at 10:31 AM, Scott Wood wrote:
On 07/10/2012 01:13 AM, Liu Shengzhou-B36685 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, July 10, 2012 12:39 AM
To: Liu Shengzhou-B36685
Cc: bhelg...@google.com; linux-...@vger.kernel.org; linuxppc-
On Jun 27, 2012, at 6:50 PM, Scott Wood wrote:
Similar to how the primary PCI bridge is identified by looking
for an isa subnode, we determine whether to apply uli exclusions
by looking for a uli subnode.
Signed-off-by: Scott Wood scottw...@freescale.com
---
Besides being an example of a
On Jul 9, 2012, at 3:45 AM, Varun Sethi wrote:
Previously, these interrupts would be mapped, but the offset
calculation was broken, and only the first group was initialized.
Signed-off-by: Scott Wood scottw...@freescale.com
---
arch/powerpc/include/asm/mpic.h |5 +++
On Jul 9, 2012, at 3:46 AM, Varun Sethi wrote:
We should use the MPIC_LARG_VECTORS flag while intializing the MPIC.
This prevents us from eating in to hardware vector number space (MSIs)
while setting up internal sources.
Signed-off-by: Varun Sethi varun.se...@freescale.com
---
On Jul 9, 2012, at 11:43 AM, Scott Wood wrote:
On 07/09/2012 09:12 AM, Kumar Gala wrote:
On Jul 9, 2012, at 3:45 AM, Varun Sethi wrote:
Previously, these interrupts would be mapped, but the offset
calculation was broken, and only the first group was initialized.
Signed-off-by: Scott
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
All SOC device error interrupts are muxed and delivered to the core as a
single
MPIC error interrupt. Currently all the device drivers requiring access to
device
errors have to register for the MPIC error interrupt as a shared interrupt.
On Jul 9, 2012, at 3:22 PM, Scott Wood wrote:
On 07/09/2012 02:03 PM, Kumar Gala wrote:
On Jul 9, 2012, at 3:47 AM, Varun Sethi wrote:
+int mpic_err_int_init(struct mpic *mpic, irq_hw_number_t irqnum)
+{
Why can't we do this during mpic_init() time?
Are you willing to hardcode
On Jul 5, 2012, at 5:07 PM, Timur Tabi wrote:
This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943.
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi ti...@freescale.com
---
On Jul 5, 2012, at 11:02 PM, Sethi Varun-B16395 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Tuesday, June 19, 2012 12:53 AM
To: Sethi Varun-B16395
Cc: Wood Scott-B07421; Kumar Gala; Linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH 4/4] powerpc/mpic: FSL MPIC error
On Mar 21, 2012, at 11:54 PM, Prabhakar Kushwaha wrote:
BSC9131RDB is a Freescale reference design board for BSC9131 SoC.The BSC9131
is integrated SoC that targets Femto base station market. It combines Power
Architecture e500v2 and DSP StarCore SC3850 core technologies with MAPLE-B2F
On Jul 5, 2012, at 5:07 PM, Timur Tabi wrote:
This reverts commit 96cc017c5b7ec095ef047d3c1952b6b6bbf98943.
The P3060 was cancelled before it went into production, so there's no point
in supporting it.
Signed-off-by: Timur Tabi ti...@freescale.com
---
On Jul 5, 2012, at 10:08 AM, Timur Tabi wrote:
In order to enable the DIU video controller on the P1022DS, the FPGA needs
to be switched to indirect mode, where the localbus is disabled and
the FPGA is accessed via writes to localbus chip select signals CS0 and CS1.
To obtain the address
On Apr 16, 2012, at 8:42 PM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
Add the RTC support for p1022ds
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
---
arch/powerpc/boot/dts/p1022ds.dtsi |4
On Apr 16, 2012, at 8:42 PM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
The compatilbe 'simple-bus' is removed from the latest DTS for NAND and
NOR flash partition, so we must add the new compatilbe support for
On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Friday, June 29, 2012 12:31 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; ga...@kernel.crashing.org; Li Yang-R58472;
ag...@suse.de; linuxppc-dev@lists.ozlabs.org
Subject:
On Jun 29, 2012, at 11:01 AM, Scott Wood wrote:
On 06/29/2012 10:57 AM, Kumar Gala wrote:
On Jun 28, 2012, at 9:36 PM, Jia Hongtao-B38951 wrote:
-Original Message-
From: Wood Scott-B07421
Sent: Friday, June 29, 2012 12:31 AM
To: Jia Hongtao-B38951
Cc: Wood Scott-B07421; ga
On Mar 16, 2012, at 11:07 AM, Timur Tabi wrote:
Kumar Gala wrote:
Haiying said it should be ok, but I haven't tried it yet. I'll try it on
Monday.
Did you ever test this?
No, I forgot all about it. I'll try it today, assuming the lone 8323
board in the board farm still works.
Do
On Sep 19, 2011, at 10:35 AM, Matias Garcia wrote:
Here's the patch against 2.6.37:
Change quirk_fsl_pcie_header from __init to __devinit.
Signed-off-by: Matias Garcia mgar...@rossvideo.com
applied
- k
___
Linuxppc-dev mailing list
On Apr 13, 2012, at 5:26 PM, Kim Phillips wrote:
At least for crypto/IPSec, doing so provides users with a better
performance experience out of the box.
Signed-off-by: Kim Phillips kim.phill...@freescale.com
---
arch/powerpc/configs/corenet32_smp_defconfig |1 +
On Apr 26, 2012, at 10:01 PM, Shengzhou Liu wrote:
Enable MTD/NOR/NAND options by default in mpc85xx_defconfig and
mpc85xx_smp_defconfig to support NOR, NAND flash.
Signed-off-by: Shengzhou Liu shengzhou@freescale.com
---
based on master branch of
On Apr 16, 2012, at 8:42 PM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
Add the RTC support for p1022ds
Signed-off-by: Jerry Huang chang-ming.hu...@freescale.com
---
arch/powerpc/boot/dts/p1022ds.dtsi |4
On May 9, 2012, at 2:53 PM, Sebastian Andrzej Siewior wrote:
* Kumar Gala | 2012-03-31 09:48:18 [-0500]:
Sorry for the delay Kumar, I though I allready done it.
Yes, please do.
Here it comes.
From 5b3e09992615e5670fa8e432e50424466fa9ca1a Mon Sep 17 00:00:00 2001
From: Sebastian
On May 23, 2012, at 9:35 AM, Gustavo Zacarias wrote:
Add EEPROM to the P1010RDB device tree.
The 24c01 acts as a memory SPD so it shouldn't be overwritten without
care.
The 24c256 is a general purpose memory.
Signed-off-by: Gustavo Zacarias gust...@zacarias.com.ar
---
On Jun 26, 2012, at 2:54 PM, Paul Gortmaker wrote:
This reference board dates back to 2004, and is largely a legacy
EOL product. The MPC8560 is a pre e500v2 CPU. The SBC8548 is
a more modern, better e500v2 target for people to use as a
reference board with today's kernels, should they
On May 8, 2012, at 8:57 AM, Holger Brunck wrote:
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Heiko Schocher h...@denx.de
cc: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/platforms/83xx/km83xx.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
applied
- k
as per Freescale
MPC8360ECE Errata document Rev.5(9/2011) item QE_ENET10.
Signed-off-by: Christian Herzig christian.her...@keymile.com
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Heiko Schocher h...@denx.de
cc: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/platforms
On May 8, 2012, at 8:57 AM, Holger Brunck wrote:
Switch on UBIFS, HOTPLUG and TIPC and update the config to
the latest kernel version.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Heiko Schocher h...@denx.de
cc: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/configs
.
Signed-off-by: Holger Brunck holger.bru...@keymile.com
cc: Heiko Schocher h...@denx.de
cc: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/boot/dts/mgcoge.dts | 23 +++
arch/powerpc/configs/mgcoge_defconfig | 12
arch/powerpc/platforms/82xx
On May 24, 2012, at 4:08 AM, b29...@freescale.com b29...@freescale.com
wrote:
From: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
Signed-off-by: Tang Yuantian yuantian.t...@freescale.com
---
On May 24, 2012, at 4:08 AM, b29...@freescale.com b29...@freescale.com
wrote:
From: Tang Yuantian yuantian.t...@freescale.com
The p1024rdb has the similar feature as the p1020rdb. Therefore, p1024rdb use
the same platform file as the p1/p2 rdb board.
Overview of P2020RDB platform
-
On Jun 29, 2012, at 4:41 AM, Shaohui Xie wrote:
NAND on p2041 uses CS1 as chip select.
Signed-off-by: Shaohui Xie shaohui@freescale.com
---
arch/powerpc/boot/dts/p2041rdb.dts | 41 +++-
1 files changed, 40 insertions(+), 1 deletions(-)
applied
- k
On Jun 28, 2012, at 5:50 AM, Benjamin Herrenschmidt wrote:
On Thu, 2012-06-28 at 11:38 +0800, Zhao Chenhui wrote:
The bootloader have done a timebase sync. If we do not need KEXEC or
HOTPLUG_CPU feature, it is unnecessary to do it again at boot time of
kernel. I only compile the timebase
On Jun 26, 2012, at 5:25 AM, Zhao Chenhui wrote:
Do hardware timebase sync. Firstly, stop all timebases, and transfer
the timebase value of the boot core to the other core. Finally,
start all timebases.
Only apply to dual-core chips, such as MPC8572, P2020, etc.
Signed-off-by: Zhao
On Jun 19, 2012, at 8:12 AM, Guilherme Maciel Ferreira wrote:
The struct fhci_regs (in fhci.h) is basically a redefinition
of the struct qe_usb_ctlr (in immap_qe.h). The later struct is
preferrable once it uses the registers names found at the
Freescale's QUICC Engine manual. Thus it is
On Jun 4, 2012, at 8:12 AM, Olof Johansson wrote:
Hi,
On Mon, Jun 4, 2012 at 12:58 AM, Anton Blanchard an...@samba.org wrote:
I blame Mikey for this. He elevated my slightly dubious testcase:
# dd if=/dev/zero of=/dev/null bs=1M count=1
to benchmark status. And naturally we need
On Jun 1, 2012, at 5:29 AM, Zhao Chenhui-B35336 wrote:
Hi Ben and Paul,
I am sorry to trouble you. It seems that Kumar is busy recently.
Could you have a review on the following patches? These patches
implement the power management support on MPC85xx platform.
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller at 0x20 */
43 pci0 {
44 compatible = fsl,p2041-pcie, fsl,qoriq-pcie-v2.2;
45
On Apr 20, 2012, at 2:04 PM, Scott Wood wrote:
On 04/20/2012 01:53 PM, Kumar Gala wrote:
On Apr 20, 2012, at 1:37 PM, Yoder Stuart-B08248 wrote:
There was refactoring change a while back that moved
the interrupt map down into the virtual pci bridge.
example:
42 /* controller
On Nov 30, 2011, at 10:19 AM, Timur Tabi wrote:
Commit 46d026ac (powerpc/85xx: consolidate of_platform_bus_probe calls)
replaced platform-specific of_device_id tables with a single function
that probes the most of the busses in 85xx device trees. If a specific
platform needed additional
On Apr 19, 2012, at 1:32 AM, Baruch Siach wrote:
Commit ae3a197e (Disintegrate asm/system.h for PowerPC) broke build of
assembly files when CONFIG_BOOKE_WDT is enabled as follows:
AS arch/powerpc/lib/string.o
/home/baruch/git/stable/arch/powerpc/include/asm/reg_booke.h: Assembler
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
In file included from arch/powerpc/sysdev/mpic_msgr.c:20:0:
~/arch/powerpc/include/asm/mpic_msgr.h: In function
'mpic_msgr_set_destination':
~/arch/powerpc/include/asm/mpic_msgr.h:117:2:
error: implicit declaration of function
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
Also fix issue of accessing invalid msgr pointer issue. The local
msgr pointer in fucntion mpic_msgr_get will be accessed before
getting a valid address which will cause kernel crash.
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/sysdev/mpic_msgr.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
applied to merge
- k
___
Linuxppc-dev mailing list
On Apr 15, 2012, at 9:05 PM, Mingkai Hu wrote:
Signed-off-by: Mingkai Hu mingkai...@freescale.com
---
arch/powerpc/boot/dts/fsl/pq3-mpic-message-B.dtsi | 43 +
arch/powerpc/boot/dts/fsl/pq3-mpic.dtsi | 10 +
2 files changed, 53 insertions(+), 0
Ben,
Some bug fix patches for v3.4.
- k
The following changes since commit fae2e0fb24c61ca68c98d854a34732549ebc1854:
powerpc: Fix typo in runlatch code (2012-04-11 10:42:15 +1000)
are available in the git repository at:
git://git.kernel.org/pub/scm/linux/kernel/git/galak/powerpc.git merge
On Apr 17, 2012, at 4:39 PM, York Sun wrote:
The timebase synchronization is only necessary if we need to reset a
separate core. Currently only KEXEC and CPU hotplug require resetting
a single core. The following code should be in the condition of
CONFIG_KEXEC or CONFIG_HOTPLUG_CPU
On Apr 17, 2012, at 5:17 PM, Scott Wood wrote:
On 04/17/2012 04:39 PM, York Sun wrote:
The timebase synchronization is only necessary if we need to reset a
separate core. Currently only KEXEC and CPU hotplug require resetting
a single core. The following code should be in the condition of
On Apr 17, 2012, at 11:42 PM, Anton Blanchard wrote:
Older versions of gcc had issues with using -maltivec together with
-mcpu of a non altivec capable CPU. We work around it by specifying
-mcpu=970, but the logic is complicated.
In preparation for adding more -mcpu targets, remove the
On Apr 17, 2012, at 11:45 PM, Anton Blanchard wrote:
Add a menu to select various 64-bit CPU targets for gcc. We
default to -mtune=power7 and if gcc doesn't understand that we
fallback to -mtune=power4.
Signed-off-by: Anton Blanchard an...@samba.org
---
Can you add a target for e5500
, leaving e6500's CPU
table entry missing CPU_FTR_EMB_HV.
Signed-off-by: Scott Wood scottw...@freescale.com
---
Fixup patch for the KVM merge as requested by Marcelo.
arch/powerpc/include/asm/cputable.h |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
Acked-by: Kumar Gala ga
On Apr 1, 2012, at 1:56 AM, Jia Hongtao wrote:
If PCI is primary bus we should set isa_io/mem_base when parsing PCI bridge
resources from device tree. The previous way to check the primary bus based
on a hard-coded address named primary_phb_addr. Now we add a property named
fsl,has-isa into
On Apr 4, 2012, at 8:32 AM, Shawn Guo wrote:
Kumar,
Gentle ping ...
Regards,
Shawn
Was on a bit of travel to nowhere, but that's a different story.
What timeframe are you looking for this to go in? 3.4 or 3.5?
- k
On Fri, Mar 30, 2012 at 01:38:56PM +0800, Shawn Guo wrote:
On Feb 10, 2012, at 1:59 AM, b29...@freescale.com b29...@freescale.com
wrote:
From: Tang Yuantian yuantian.t...@freescale.com
Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com
Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com
Signed-off-by: Tang Yuantian
On Jan 17, 2012, at 11:40 PM, Ramneek Mehresh wrote:
Add usb controller version info for the following:
MPC8536, P1010, P1020, P1021, P1022, P1023, P2020, P2041,
P3041, P3060, P5020
Signed-off-by: Ramneek Mehresh ramneek.mehr...@freescale.com
---
Applies on
On Feb 16, 2012, at 3:07 PM, Tabi Timur-B04825 wrote:
On Tue, Feb 14, 2012 at 2:06 AM, Zhicheng Fan b32...@freescale.com wrote:
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
Acked-by: Timur Tabi ti...@freescale.com
--
applied
- k
On Feb 16, 2012, at 3:06 PM, Tabi Timur-B04825 wrote:
On Tue, Feb 14, 2012 at 2:06 AM, Zhicheng Fan b32...@freescale.com wrote:
From: Zhicheng Fan b32...@freescale.com
P1025RDB Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
16Mbyte NOR flash
16 Mbyte SPI flash
SD
On Mar 5, 2012, at 8:58 PM, Liu Gang wrote:
For the file arch/powerpc/sysdev/fsl_rio.c, there will be some relocation
errors while using the corenet64_smp_defconfig:
WARNING: modpost: Found 6 section mismatch(es).
To see full details build your kernel with:
'make
On Mar 9, 2012, at 2:10 AM, Liu Gang wrote:
For the file arch/powerpc/sysdev/fsl_rmu.c, there will be some compile
errors while using the corenet64_smp_defconfig:
.../fsl_rmu.c:315: error: cast from pointer to integer of different size
.../fsl_rmu.c:320: error: cast to pointer from integer
On Feb 28, 2012, at 1:43 PM, Gustavo Zacarias wrote:
Fix typo introduced by powerpc: Add TBI PHY node to first MDIO bus
from Andy Fleming.
It's device_type rather than device-type, which causes the mdio probe to
fail thus making all gianfar ethernet interfaces unusable.
Signed-off-by:
On Mar 15, 2012, at 12:40 PM, Sebastian Andrzej Siewior wrote:
This is here most likely since the FSL bsp. Back in the FSL bsp it was
set to 50Mhz and working. However the driver divided the SoC freq. only
by 2. According to the TRM the platform clock (which the manual refers
in its formula)
On Mar 8, 2012, at 4:47 PM, soniccat@gmail.com wrote:
From: Liu Shuo soniccat@gmail.com
Signed-off-by: Liu Shuo soniccat@gmail.com
---
arch/powerpc/sysdev/fsl_msi.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
applied
- k
On Jan 18, 2012, at 1:39 PM, Kumar Gala wrote:
The registers that describe size supported by TLB are different on MMU
v2 as well as we support power of two page sizes. For now we continue
to assume that FSL variable size array supports all page sizes up to the
maximum one reported in TLB1PS
On Jan 18, 2012, at 1:39 PM, Kumar Gala wrote:
Add basic support for e6500 core in its single threaded mode.
Signed-off-by: Kumar Gala ga...@kernel.crashing.org
---
arch/powerpc/include/asm/cputable.h | 12
arch/powerpc/kernel/cputable.c | 18 ++
2
On Aug 11, 2011, at 9:25 AM, Robin Holt wrote:
If I have the the fsl,num_rx_queues and fsl,num_tx_queues properties
defined in the p1010's device tree file, I get a kernel panic very
shortly after boot. The failure indicates we are configuring the
gianfar.c driver for a queue depth greater
On Nov 24, 2011, at 7:57 AM, Tabi Timur-B04825 wrote:
On Nov 24, 2011, at 1:55 AM, Kumar Gala ga...@kernel.crashing.org wrote:
I'll have to check. But this patch can't be applied as-is unless it's
proven safe for all QE-enabled chips.
Any update on trying this on a MPC8323?
Haiying
On Mar 8, 2012, at 4:47 PM, soniccat@gmail.com wrote:
From: Liu Shuo soniccat@gmail.com
Signed-off-by: Liu Shuo soniccat@gmail.com
---
arch/powerpc/sysdev/fsl_msi.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
applied
- k
On Mar 15, 2012, at 12:40 PM, Sebastian Andrzej Siewior wrote:
It is not at 0xffa0. According to current u-boot source the NAND
controller is always at 0xff80 and it is either at CS0 or CS1
depending on NAND or NAND+NOR mode. In 36bit mode it is shifted to
0xfff80 but it has
On Mar 14, 2012, at 4:08 AM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
+ partition@0 {
+ /* 128KB for DTB Image */
+ reg = 0x0 0x0002;
+ label = NOR (RO) DTB Image;
+
On Jan 17, 2012, at 3:59 AM, Xie Xiaobo wrote:
1. Add partitions for NOR and NAND Flash.
2. Additional attributes for sdhc.
Signed-off-by: Xie Xiaobo x@freescale.com
---
arch/powerpc/boot/dts/fsl/mpc8536si-post.dtsi |5 ++
arch/powerpc/boot/dts/mpc8536ds.dts |6 ++-
On Jan 17, 2012, at 3:59 AM, Xie Xiaobo wrote:
The properties indicates that the hardware supports waking up via magic
packet.
Signed-off-by: Xie Xiaobo x@freescale.com
---
arch/powerpc/boot/dts/fsl/pq3-etsec1-0.dtsi |3 ++-
arch/powerpc/boot/dts/fsl/pq3-etsec1-1.dtsi |3 ++-
On Feb 15, 2012, at 6:25 PM, Timur Tabi wrote:
Create a 32-bit address space version of p1022ds.dts. To avoid confusion,
p1022ds.dts is renamed to p1022ds_36b.dts. We also create p1022ds.dtsi
to store some common nodes.
Signed-off-by: Timur Tabi ti...@freescale.com
---
On Feb 15, 2012, at 6:25 PM, Timur Tabi wrote:
The Freescale P1022 has a unique pin muxing feature where the DIU video
controller's video signals are muxed with 24 of the local bus address signals.
When the DIU is enabled, the bulk of the local bus is disabled, preventing
access to
On Feb 20, 2012, at 8:11 PM, Jia Hongtao wrote:
Signed-off-by: Jin Qing b24...@freescale.com
Signed-off-by: Jia Hongtao b38...@freescale.com
Signed-off-by: Li Yang le...@freescale.com
---
arch/powerpc/boot/dts/mpc8572ds.dtsi | 50 +
1 files changed, 32
On Mar 14, 2012, at 4:08 AM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
The p1020mbg-pc has the similar feature as the p1020rdb.
Therefore, p1020mbg-pc use the same platform file as the p1/p2 rdb board.
Overview of
On Mar 15, 2012, at 12:34 AM, Prabhakar Kushwaha wrote:
Integrated Flash Controller(IFC) can be used to hook NAND Flash
chips using NAND Flash Machine available on it.
Signed-off-by: Dipen Dudhat dipen.dud...@freescale.com
Signed-off-by: Scott Wood scottw...@freescale.com
Signed-off-by:
On Mar 14, 2012, at 4:08 AM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
The p1020utm-pc has the similar feature as the p1020rdb.
Therefore, p1020utm-pc use the same platform file as the p1/p2 rdb board.
Overview of
On Mar 14, 2012, at 4:08 AM, chang-ming.hu...@freescale.com
chang-ming.hu...@freescale.com wrote:
From: Jerry Huang chang-ming.hu...@freescale.com
The p1020mbg-pc has the similar feature as the p1020rdb.
Therefore, p1020mbg-pc use the same platform file as the p1/p2 rdb board.
Overview of
On Feb 10, 2012, at 12:48 AM, Zhicheng Fan wrote:
From: Zhicheng Fan b32...@freescale.com
Signed-off-by: Zhicheng Fan b32...@freescale.com
---
arch/powerpc/platforms/85xx/mpc85xx_rdb.c | 24 +++-
1 files changed, 23 insertions(+), 1 deletions(-)
applied
- k
On Feb 10, 2012, at 12:48 AM, Zhicheng Fan wrote:
From: Zhicheng Fan b32...@freescale.com
P1020RDB-PC Overview
--
1Gbyte DDR3 SDRAM
32 Mbyte NAND flash
10 16Mbyte NOR flash
16 Mbyte SPI flash
SD connector to interface with the SD memory card
Real-time clock on I2C bus
On Mar 12, 2012, at 12:12 PM, Martyn Welch wrote:
This patch adds the GE_FPGA configuration option. This is being carried
out as ground work to allow the PIC and GPIO drivers to be move from the
powerpc 86xx platform directory to more general locations to allow them to
be used on non-86xx
On Mar 12, 2012, at 12:12 PM, Martyn Welch wrote:
The GE GPIO driver provides basic support (set direction, read/write state)
for the GPIO provided on some GE single board computers. This patch moves
the driver from the 86xx specific platform directrory to the GPIO subsystem
so that it can
On Mar 12, 2012, at 12:12 PM, Martyn Welch wrote:
Move the GE PIC drivers to allow these to be used by non-86xx boards.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Move GPIO and PIC drivers to sysdev/ge/ rather than platforms/.
v3: Now just PIC driver. GPIO driver going to
On Mar 12, 2012, at 12:13 PM, Martyn Welch wrote:
Initial board support for the GE IMP3A, a 3U compactPCI card with a p2020
processor.
Signed-off-by: Martyn Welch martyn.we...@ge.com
---
v2: Rebase patch onto powerpc/next, taking work by Kyle Moffett into
account.
v3: Correct
On Nov 18, 2011, at 11:50 AM, Timur Tabi wrote:
When the P1022's DIU video controller is active, the pixis must be accessed
in indirect mode, which uses localbus chip select addresses.
Switching between the DVI and LVDS monitor ports is handled by the pixis,
so that switching needs to be
On Feb 9, 2012, at 8:27 PM, Jia Hongtao-B38951 wrote:
Hi Kumar,
This series of patches have been pending for a long time.
I'd like to know whether they are look good or not so I can do the further
work on it.
It's kind of emergency things for me.
Thanks a lot for your attention.
I
401 - 500 of 3919 matches
Mail list logo
