[PATCH v2] ocxl: control via sysfs whether the FPGA is reloaded on a link reset

Some opencapi FPGA images allow to control if the FPGA should be reloaded on the next adapter reset. If it is supported, the image specifies it through a Vendor Specific DVSEC in the config space of function 0. Signed-off-by: Philippe Bergheaud --- Changelog: v2: - refine ResetReload debug

[PATCH] ocxl: control via sysfs whether the FPGA is reloaded on a link reset

-off-by: Philippe Bergheaud --- Documentation/ABI/testing/sysfs-class-ocxl | 10 drivers/misc/ocxl/config.c | 59 +- drivers/misc/ocxl/ocxl_internal.h | 6 +++ drivers/misc/ocxl/sysfs.c | 35 + include/misc/ocxl-config.h

Re: [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

On 15/05/2018 07:30, Michael Ellerman wrote: Philippe Bergheaud <fe...@linux.ibm.com> writes: On 14/05/2018 12:51, Michael Ellerman wrote: Philippe Bergheaud <fe...@linux.ibm.com> writes: Skiboot used to set the default Tunnel BAR register value when capi mode was enabled. T

Re: [PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

On 14/05/2018 12:51, Michael Ellerman wrote: Philippe Bergheaud <fe...@linux.ibm.com> writes: Skiboot used to set the default Tunnel BAR register value when capi mode was enabled. This approach was ok for the cxl driver, but prevented other drivers from choosing different values. S

[PATCH v4 2/2] cxl: Report the tunneled operations status

Failure to synchronize the tunneled operations does not prevent the initialization of the cxl card. This patch reports the tunneled operations status via /sys. Signed-off-by: Philippe Bergheaud <fe...@linux.ibm.com> --- v3: Added this patch to report the tunneled operations status. v4: U

[PATCH v4 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

set/reset the Tunnel BAR register when entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar(). That should work with old skiboot (since we are re-writing the value already set) and new skiboot. Signed-off-by: Philippe Bergheaud <fe...@linux.ibm.com> Reviewed-by: Christophe Lomba

[PATCH v3 2/2] cxl: Report the tunneled operations status

Failure to synchronize the tunneled operations does not prevent the initialization of the cxl card. This patch reports the tunneled operations status via /sys. Signed-off-by: Philippe Bergheaud <fe...@linux.ibm.com> --- v3: Added this patch to report the tunneled operations status. --- d

[PATCH v3 1/2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

set/reset the Tunnel BAR register when entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar(). Signed-off-by: Philippe Bergheaud <fe...@linux.ibm.com> Reviewed-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> --- v2: Restrict tunnel bar setting to power9. Do not fail cxl_co

[PATCH v2] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

set/reset the Tunnel BAR register when entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar(). Signed-off-by: Philippe Bergheaud <fe...@linux.ibm.com> --- Changelog: v2: Restrict tunnel bar setting to power9. Do not fail cxl_configure_adapter() on tunnel bar setting error. Lo

[PATCH] cxl: Set the PBCQ Tunnel BAR register when enabling capi mode

set/reset the Tunnel BAR register when entering/exiting the cxl mode, with pnv_pci_set_tunnel_bar(). Signed-off-by: Philippe Bergheaud <fe...@linux.ibm.com> --- drivers/misc/cxl/pci.c | 4 1 file changed, 4 insertions(+) diff --git a/drivers/misc/cxl/pci.c b/drivers/misc/cxl/pc

[PATCH v10 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new

[PATCH v10 1/2] powerpc/powernv: Enable tunneled operations

to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> Reviewed-by: Frederic Barrat <fbar...@linux.vnet.ibm.com> --- Changelog: v2: Do not set the ASN indication. Get it from the device tree. v3: Make pnv_pci_get_phb_node() available when compiling without c

[PATCH v9 1/2] powerpc/powernv: Enable tunneled operations

to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: Do not set the ASN indication. Get it from the device tree. v3: Make pnv_pci_get_phb_node() available when compiling without cxl. v4: Add pnv_pci_get_as_notify_info(). Rebase opal call n

[PATCH v9 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3

[PATCH v8 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. This function uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. pnv_pci_get_as_notify_info() Return the ASN info of the thread to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.

[PATCH v8 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3

[PATCH v7 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3

[PATCH v7 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. This function uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. pnv_pci_get_as_notify_info() Return the ASN info of the thread to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.

[PATCH v6 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3

[PATCH v6 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. This function uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. pnv_pci_get_as_notify_info() Return the ASN info of the thread to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.

[PATCH v5 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3

[PATCH v5 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. This function uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. pnv_pci_get_as_notify_info() Return the ASN info of the thread to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.

[PATCH v4 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3

[PATCH v4 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. This function uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. void pnv_pci_get_as_notify_info() Return the ASN info of the thread to be woken up. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.

Re: [PATCH V2] cxl: Add support for ASB_Notify on POWER9

Signed-off-by: Christophe Lombard <clomb...@linux.vnet.ibm.com> Reviewed-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com>

[PATCH v3 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". v3: No cha

[PATCH v3 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. The latter uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: Do not set the ASN indication. Get it from the device tree. v3

[PATCH v2 2/2] cxl: read PHB indications from the device tree

Configure the P9 XSL_DSNCTL register with PHB indications found in the device tree, or else use legacy hard-coded values. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: New patch. Use the new device tree property "ibm,phb-indications". Th

[PATCH v2 1/2] powerpc/powernv: Enable tunneled operations

the Tunnel BAR Response address used by driver. The latter uses two new OPAL calls, as the PBCQ Tunnel BAR register is configured by skiboot. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changelog: v2: Do not set the ASN indication. Get it from the device tree. This patch d

[PATCH] powerpc/powernv: Enable tunneled operations

the Tunnel BAR address mask used by driver. These functions use four new OPAL calls, as PBCQ and PHB configurations are done by skiboot. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- This patch depends on the following skiboot prerequisites: https://patchwork.ozlabs.org/patch/

Re: [PATCH RFC] Interface to set SPRN_TIDR

On 31/08/2017 20:06, Sukadev Bhattiprolu wrote: felix [fe...@linux.vnet.ibm.com] wrote: On 31/08/2017 01:32, Sukadev Bhattiprolu wrote: Michael Neuling [mi...@neuling.org] wrote: Suka, Please CC Christophe who as an alternative way of doing this. We ned to get agreement across all users of

[PATCH v2] cxl: Use fixed width predefined types in data structure.

). This patch also changes the size of the field data_size, and makes it constant, to support 32-bit userland applications running on big-endian ppc64 kernels transparently. This breaks the (young) API that has been merged in v4.8. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- C

[PATCH] cxl: Use fixed width predefined types in data structure.

makes the definition of cxl_event_afu_driver_reserved more consistent with the other definitions in the header file. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- include/uapi/misc/cxl.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/include/uap

[PATCH v3] cxl: Refine slice error debug messages

implementation errors. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changes since v1: - Rebased on Ian's patch "cxl: Abstract the differences between the PSL and XSL" Changes since v2: - Added description drivers/misc/cxl/cxl.h| 15 +

[PATCH v2] cxl: Refine slice error debug messages

Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changes since v1: - Rebased on Ian's patch "cxl: Abstract the differences between the PSL and XSL" drivers/misc/cxl/cxl.h| 15 +++ drivers/misc/cxl/guest.c | 9 ++--- drivers/misc/c

[PATCH v2] cxl: Ignore CAPI adapters misplaced in switched slots

One should not attempt to switch a PHB into CAPI mode if there is a switch between the PHB and the adapter. This patch modifies the cxl driver to ignore CAPI adapters misplaced in switched slots. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- This patch fixes Bz 142217. C

[PATCH] cxl: Ignore CAPI adapters misplaced in switched slots

One should not attempt to switch a PHB into CAPI mode if there is a switch between the PHB and the adapter. This patch modifies the cxl driver to ignore CAPI adapters misplaced in switched slots. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- This patch fixes Bz

Re: [RESEND, v7, 2/2] cxl: Add set and get private data to context struct

Michael Ellerman wrote: On Fri, 2016-24-06 at 06:47:07 UTC, Philippe Bergheaud wrote: From: Michael Neuling <mi...@neuling.org> This provides AFU drivers a means to associate private data with a cxl context. This is particularly intended for make the new callbacks for driver specific

[RESEND v7,2/2] cxl: Add set and get private data to context struct

ctures they may use. Signed-off-by: Michael Neuling <mi...@neuling.org> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com Reviewed-by: Matthew R. Ochs <mro...@linux.vnet.ibm.com> --- No changes since v1. Added Matt Ochs

[v6,2/2] cxl: Add set and get private data to context struct

ctures they may use. Signed-off-by: Michael Neuling <mi...@neuling.org> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com Reviewed-by: Matthew R. Ochs <mro...@linux.vnet.ibm.com> --- No changes since v1. Added Matt Ochs

[v7, 1/2] cxl: Add mechanism for delivering AFU driver specific events

their own means for userspace to obtain the AFU file descriptor (i.e. cxlflash uses an ioctl on their scsi file descriptor to obtain the AFU file descriptor) and the generic cxl driver will never use this event, the ABI of the event is up to each individual AFU driver. Signed-off-by: Philippe

Re: [v6, 1/2] cxl: Add mechanism for delivering AFU driver specific events

Should also check against the length of user-buffer (count) provided in the read call.Ideally this condition check should be moved to the read call where you have access to the count variable. Right now libcxl is using a harcoded value of CXL_READ_MIN_SIZE to issue the read call and in kernel

Re: [v6, 1/2] cxl: Add mechanism for delivering AFU driver specific events

Matthew R. Ochs wrote: On Jun 21, 2016, at 5:34 AM, Vaibhav Jain wrote: Hi Ian, Ian Munsie writes: Excerpts from Vaibhav Jain's message of 2016-06-20 14:20:16 +0530: What exactly is the use case for this API? I'd vote to drop it if we can

[v6,2/2] cxl: Add set and get private data to context struct

ctures they may use. Signed-off-by: Michael Neuling <mi...@neuling.org> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com Reviewed-by: Matthew R. Ochs <mro...@linux.vnet.ibm.com> --- No changes since v1. Added Matt Ochs

[v6, 1/2] cxl: Add mechanism for delivering AFU driver specific events

for userspace to obtain the AFU file descriptor (i.e. cxlflash uses an ioctl on their scsi file descriptor to obtain the AFU file descriptor) and the generic cxl driver will never use this event, the ABI of the event is up to each individual AFU driver. Signed-off-by: Philippe Bergheaud <

Re: [v5, 1/2] cxl: Add mechanism for delivering AFU driver specific events

Michael Ellerman wrote: On Mon, 2016-23-05 at 12:49:01 UTC, Philippe Bergheaud wrote: This adds an afu_driver_ops structure with deliver_event() and event_delivered() callbacks. An AFU driver such as cxlflash can fill this out and associate it with a context to enable passing custom AFU

[RESEND v5,2/2] cxl: Add set and get private data to context struct

ctures they may use. Signed-off-by: Michael Neuling <mi...@neuling.org> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com Reviewed-by: Matthew R. Ochs <mro...@linux.vnet.ibm.com> --- No changes since v1, added Matt Ochs

[v4,2/2] cxl: Add set and get private data to context struct

ctures they may use. Signed-off-by: Michael Neuling <mi...@neuling.org> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com Reviewed-by: Matthew R. Ochs <mro...@linux.vnet.ibm.com> --- No changes since v1, added Matt Ochs

[v5, 1/2] cxl: Add mechanism for delivering AFU driver specific events

for userspace to obtain the AFU file descriptor (i.e. cxlflash uses an ioctl on their scsi file descriptor to obtain the AFU file descriptor) and the generic cxl driver will never use this event, the ABI of the event is up to each individual AFU driver. Signed-off-by: Philippe Bergheaud <

[RESEND v4,1/2] cxl: Add mechanism for delivering AFU driver

eneric cxl driver will never use this event, the ABI of the event is up to each individual AFU driver. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changes since v3: - Removed driver ops callback ctx_event_pending - Created cxl function cxl_context_pending_events - Created

[v3, 1/2] cxl: Add mechanism for delivering AFU driver specific events

eneric cxl driver will never use this event, the ABI of the event is up to each individual AFU driver. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- Changes since v3: - Removed driver ops callback ctx_event_pending - Created cxl function cxl_context_pending_events - Created

[v4,2/2] cxl: Add set and get private data to context struct

ctures they may use. Signed-off-by: Michael Neuling <mi...@neuling.org> Signed-off-by: Ian Munsie <imun...@au1.ibm.com> Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com Reviewed-by: Matthew R. Ochs <mro...@linux.vnet.ibm.com> --- No changes since v1, added Matt Ochs

[PATCH] cxl: Refine slice error debug messages.

Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- drivers/misc/cxl/cxl.h| 15 +++ drivers/misc/cxl/guest.c | 11 --- drivers/misc/cxl/irq.c| 27 +++ drivers/misc/cxl/native.c | 27 ++- 4 files chang

[PATCH v3 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL

The POWER8NVL chip has two CAPI ports. Configure the PSL to route data to the port corresponding to the CAPP unit. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- V2: - Complete rewrite after Mikey's review V3: Fixes suggested by Michael: - s/capp_unit_id(/get_capp_u

[PATCH v3 1/2] powerpc: Define PVR value for POWER8NVL processor

Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- V2: - New patch, added to patch set V3: - no change arch/powerpc/include/asm/reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index f5f4c66..c

Re: [PATCH] Added a 5ms wait after a msi-irq is masked

Sorry, I've sent this to the wrong list. Philippe Philippe Bergheaud wrote: From: Vaibhav Jain <vaib...@linux.vnet.ibm.com> Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so that the kernel delays cleanup until an irq if its in-flight is handled. The value 5ms is the

[PATCH] Added a 5ms wait after a msi-irq is masked

From: Vaibhav Jain Adds a 5ms wait to phb3_msi_set_xive after the interrupt is masked so that the kernel delays cleanup until an irq if its in-flight is handled. The value 5ms is the worst case time needed by an irq to be presented to the host after its generated.

[PATCH v2 1/2] powerpc: Define PVR value for POWER8NVL processor

Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- V2: - New patch, added to patch set arch/powerpc/include/asm/reg.h | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/powerpc/include/asm/reg.h b/arch/powerpc/include/asm/reg.h index c4cb2ff..6a6de4a 100644 ---

[PATCH v2 2/2] cxl: Configure the PSL for two CAPI ports on POWER8NVL

The POWER8NVL chip has two CAPI ports. Configure the PSL to route data to the port corresponding to the CAPP unit. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- V2: - Complete rewrite after Mikey's review drivers/misc/cxl/pci.c | 31 ++-

Re: [PATCH] cxl: Configure the PSL for dual port CAPI on Naples

Michael Neuling wrote: On Tue, 2016-03-15 at 15:26 +0100, Philippe Bergheaud wrote: Naples CPUs have two CAPI ports. Naples is an internal name, don't use that. Use POWER8NVL is the name we use in the kernel. alsi, it's a "chip" that has two CAPI ports, not the CPU. OK, I wil

[PATCH] cxl: Configure the PSL for dual port CAPI on Naples

Naples CPUs have two CAPI ports. Configure the PSL to route data to the port corresponding to the PHB index. Signed-off-by: Philippe Bergheaud <fe...@linux.vnet.ibm.com> --- drivers/misc/cxl/pci.c | 15 ++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/driver

[PATCH][RESEND] cxl: Set up and enable PSL Timebase

This patch configures the PSL Timebase function and enables it, after the CAPP has been initialized by OPAL. Acked-by: Ian Munsie imun...@au1.ibm.com Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- drivers/misc/cxl/cxl.h | 5 + drivers/misc/cxl/pci.c | 57

Re: [PATCH V2] cxl: Set up and enable PSL Timebase

Philippe Bergheaud wrote: This patch configures the PSL Timebase function and enables it, after the CAPP has been initialized by OPAL. V2: - Clear CXL_PSL_ErrIVTE_tberror bit - Define the sync count unit - Wait 1ms before each test - Use negative error code - Do not ignore errors - Except

[PATCH V2] cxl: Set up and enable PSL Timebase

is not supported by OPAL - Be silent on success Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- drivers/misc/cxl/cxl.h |5 drivers/misc/cxl/pci.c | 57 +++- 2 files changed, 61 insertions(+), 1 deletions(-) diff --git a/drivers/misc/cxl

Re: [PATCH] cxl: Set up and enable PSL Timebase

Michael Neuling wrote: On Mon, 2015-06-01 at 09:37 +0200, Philippe Bergheaud wrote: Michael Neuling wrote: On Thu, 2015-05-28 at 15:12 +0200, Philippe Bergheaud wrote: This patch configures the PSL Timebase function and enables it, after the CAPP has been initialized by OPAL. Failures

Re: [PATCH] cxl: Set up and enable PSL Timebase

Michael Neuling wrote: On Thu, 2015-05-28 at 15:12 +0200, Philippe Bergheaud wrote: This patch configures the PSL Timebase function and enables it, after the CAPP has been initialized by OPAL. Failures are reported and ignored. Needs an Signed-off-by. Yes. Comments inline. --- drivers

Re: [PATCH] cxl: Set up and enable PSL Timebase

Michael Neuling wrote: Please use negative error codes here. -EIO? And check it here. Mikey, I am reluctant to fail the entire CAPI init after a PSL timebase sync failure. If we ignore the error, the CAPI device stays available (without timebase sync). If we honour the error, the CAPI device

[PATCH] cxl: Set up and enable PSL Timebase

This patch configures the PSL Timebase function and enables it, after the CAPP has been initialized by OPAL. Failures are reported and ignored. --- drivers/misc/cxl/cxl.h |5 + drivers/misc/cxl/pci.c | 35 +++ 2 files changed, 40 insertions(+), 0

[PATCH] cxl: Fix a typo in ABI documentation

Fix the attribute name of the configuration record class ID. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- Documentation/ABI/testing/sysfs-class-cxl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/ABI/testing/sysfs-class-cxl b/Documentation

[PATCH] Update CXL ABI documentation

From: Philippe Bergheaud fe...@linux.vnet.ibm.com This fixes two typos and explains where shared attributes are stored. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com Acked-by: Michael Neuling mi...@neuling.org --- Documentation/ABI/testing/sysfs-class-cxl | 11 --- 1

Re: [PATCH] PPC: bpf_jit_comp: add SKF_AD_PKTTYPE instruction

Denis Kirjanov wrote: Any feedback from PPC folks? I have reviewed the patch and it looks fine to me. I have tested successfuly on ppc64le. I could not test it on ppc64. Philippe On 10/26/14, Denis Kirjanov k...@linux-powerpc.org wrote: Cc: Matt Evans m...@ozlabs.org Signed-off-by: Denis

Re: [PATCH] powerpc: memcpy optimization for 64bit LE

Anton Blanchard wrote: Unaligned stores take alignment exceptions on POWER7 running in little-endian. This is a dumb little-endian base memcpy that prevents unaligned stores. Once booted the feature fixup code switches over to the VMX copy loops (which are already endian safe). The question is

Re: [git pull] Please pull abiv2 branch

Rusty Russell wrote: Philippe Bergheaud fe...@linux.vnet.ibm.com writes: Anton Blanchard wrote: Here are the ABIv2 patches rebased against 3.15-rc2. After recompiling 3.15-rc2 with the ABIv2 patches, I see the following line in Modules.symvers: 0x TOC. vmlinux EXPORT_SYMBOL

Re: [git pull] Please pull abiv2 branch

Anton Blanchard wrote: Here are the ABIv2 patches rebased against 3.15-rc2. After recompiling 3.15-rc2 with the ABIv2 patches, I see the following line in Modules.symvers: 0x TOC. vmlinux EXPORT_SYMBOL Kernel will not load modules because TOC. has no CRC. Is this expected ?

Re: [PATCH 15/33] powerpc: Fix ABIv2 issues with stack offsets in assembly code

Anton Blanchard wrote: diff --git a/arch/powerpc/lib/memcpy_64.S b/arch/powerpc/lib/memcpy_64.S index 72ad055..01da956 100644 --- a/arch/powerpc/lib/memcpy_64.S +++ b/arch/powerpc/lib/memcpy_64.S @@ -12,7 +12,7 @@ .align 7 _GLOBAL(memcpy) BEGIN_FTR_SECTION - std r3,48(r1)

Re: [PATCH] powerpc: set default kernel thread priority to medium-low

Benjamin Herrenschmidt wrote: On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote: It would be nice if you could make an assertion about what the state of HMT handling should be once your patch is applied. I think it's: * The kernel should use HMT_MEDIUM_LOW as it's default priority *

Re: [PATCH] powerpc: set default kernel thread priority to medium-low

Michael Ellerman wrote: On Wed, 2013-12-11 at 11:30 +0100, Philippe Bergheaud wrote: Benjamin Herrenschmidt wrote: On Wed, 2013-12-11 at 17:29 +1100, Michael Ellerman wrote: It would be nice if you could make an assertion about what the state of HMT handling should be once your patch

[PATCH] powerpc: set default kernel thread priority to medium-low

to manage SMT priority for spinning and active (in the critical region) threads. Libpthread must be able to raise and lower the the SMT priority versus the default to be effective. This lowers the default kernel thread priority from medium to medium-low. Signed-off-by: Philippe Bergheaud fe

Re: [PATCH] powerpc: fix xmon disassembler for little-endian

Benjamin Herrenschmidt wrote: On Wed, 2013-12-04 at 14:45 +0100, Philippe Bergheaud wrote: +#ifdef __LITTLE_ENDIAN__ +#define GETWORD(v) (((v)[3] 24) + ((v)[2] 16) + ((v)[1] 8) + (v)[0]) +#else #define GETWORD(v) (((v)[0] 24) + ((v)[1] 16) + ((v)[2] 8) + (v)[3]) +#endif

Re: [PATCH] powerpc: fix xmon disassembler for little-endian

Tom Musta wrote: On 12/2/2013 3:10 AM, Philippe Bergheaud wrote: This patch fixes the disassembler of the powerpc kernel debugger xmon, for little-endian. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- arch/powerpc/xmon/xmon.c |4 1 file changed, 4 insertions(+) diff

[PATCH] powerpc: fix xmon disassembler for little-endian

This patch fixes the disassembler of the powerpc kernel debugger xmon, for little-endian. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- arch/powerpc/xmon/xmon.c |4 1 file changed, 4 insertions(+) diff --git a/arch/powerpc/xmon/xmon.c b/arch/powerpc/xmon/xmon.c index

[PATCH v2] powerpc: memcpy optimization for 64bit LE

for all other 64bit platforms. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- arch/powerpc/include/asm/string.h |4 arch/powerpc/kernel/ppc_ksyms.c |2 -- arch/powerpc/lib/Makefile |2 -- arch/powerpc/lib/memcpy_64.S | 19 +++ 4 files

Re: [PATCH] powerpc: memcpy optimization for 64bit LE

Michael Neuling wrote: Philippe Bergheaud fe...@linux.vnet.ibm.com wrote: Unaligned stores take alignment exceptions on POWER7 running in little-endian. This is a dumb little-endian base memcpy that prevents unaligned stores. It is replaced by the VMX memcpy at boot. Is this any faster

[PATCH] powerpc: memcpy optimization for 64bit LE

Unaligned stores take alignment exceptions on POWER7 running in little-endian. This is a dumb little-endian base memcpy that prevents unaligned stores. It is replaced by the VMX memcpy at boot. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- arch/powerpc/include/asm/string.h

[PATCH] powerpc: word-at-a-time optimization for 64bit LE

This is an optimization for the PowerPC in 64-bit little-endian. Bit counting is used in find_zero(), instead of the multiply and shift. It is modelled after Alan Modra's PowerPC LE strlen patch http://sourceware.org/ml/libc-alpha/2013-08/msg00097.html. Signed-off-by: Philippe Bergheaud fe

[PATCH] powerpc: BPF JIT compiler for 64bit LE

This enables the Berkeley Packet Filter JIT compiler for the PowerPC running in 64bit Little Endian. Signed-off-by: Philippe Bergheaud fe...@linux.vnet.ibm.com --- arch/powerpc/include/asm/ppc-opcode.h |1 + arch/powerpc/net/bpf_jit.h| 10 ++ arch/powerpc/net/bpf_jit_64