[PATCH v4] powerpc/rcpm: add RCPM driver

From: Tang Yuantian yuantian.t...@freescale.com There is a RCPM (Run Control/Power Management) in Freescale QorIQ series processors. The device performs tasks associated with device run control and power management. The driver implements some features: mask/unmask irq, enter/exit low power

[PATCH v3] powerpc/rcpm: add RCPM driver

From: Tang Yuantian yuantian.t...@freescale.com There is a RCPM (Run Control/Power Management) in Freescale QorIQ series processors. The device performs tasks associated with device run control and power management. The driver implements some features: mask/unmask irq, enter/exit low power

[PATCH v2] powerpc/rcpm: add RCPM driver

From: Tang Yuantian yuantian.t...@freescale.com There is a RCPM (Run Control/Power Management) in Freescale QorIQ series processors. The device performs tasks associated with device run control and power management. The driver implements some features: mask/unmask irq, enter/exit low power

[PATCH v4] powerpc/cache: add cache flush operation for various e500

From: Tang Yuantian yuantian.t...@freescale.com Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at

[PATCH v3] powerpc/cache: add cache flush operation for various e500

From: Tang Yuantian yuantian.t...@freescale.com Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at

[PATCH v2] powerpc/cache: add cache flush operation for various e500

From: Tang Yuantian yuantian.t...@freescale.com Various e500 core have different cache architecture, so they need different cache flush operations. Therefore, add a callback function cpu_flush_caches to the struct cpu_spec. The cache flush operation for the specific kind of e500 is selected at

[PATCH] cpufreq: qoriq: optimize the CPU frequency switching time

From: Tang Yuantian yuantian.t...@freescale.com Each time the CPU switches its frequency, the clock nodes in DTS are walked through to find proper clock source. This is very time-consuming, for example, it is up to 500+ us on T4240. Besides, switching time varies from clock to clock. To optimize

[PATCH] powerpc/config: add SCSI configs for corenet64_smp_defconfig

From: Tang Yuantian yuantian.t...@freescale.com Otherwise there wil be no SCSI device nodes. Signed-off-by: Shaohui Xie shaohui@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/configs/corenet64_smp_defconfig | 7 +++ 1 file changed, 7

[PATCH 1/2 v5] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com Freescale introduced new ARM core-based SoCs which support dynamic frequency switch feature. DFS on new SoCs are compatible with current PowerPC CoreNet platforms. In order to support those new platforms, this driver needs to be updated. The main

[PATCH 2/2 v5] cpufreq: qoriq: rename the driver

From: Tang Yuantian yuantian.t...@freescale.com This driver works on all QorIQ platforms which include ARM-based cores and PPC-based cores. Rename it in order to represent better. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Acked-by: Viresh Kumar viresh.ku...@linaro.org --- v5:

[PATCH 1/2 v4] cpufreq: qoriq: Make the driver usable on all QorIQ platforms

From: Tang Yuantian yuantian.t...@freescale.com Freescale introduced new ARM core-based SoCs which support dynamic frequency switch feature. DFS on new SoCs are compatible with current PowerPC CoreNet platforms. In order to support those new platforms, this driver needs to be updated. The main

[PATCH 2/2 v4] cpufreq: qoriq: rename the driver

From: Tang Yuantian yuantian.t...@freescale.com This driver works on all QorIQ platforms which include ARM-based cores and PPC-based cores. Rename it in order to represent better. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Acked-by: Viresh Kumar viresh.ku...@linaro.org --- v3, v4

[PATCH 2/2] clk: ppc-corenet: rename driver to clk-qoriq

From: Tang Yuantian yuantian.t...@freescale.com Freescale introduced new ARM-based socs which using the compatible clock IP block with PowerPC-based socs'. So this driver can be used on both platforms. Updated relevant descriptions and renamed this driver to better represent its meaning and keep

[PATCH 1/2] clock: redefine variable clocks_per_pll as a struct member

From: Tang Yuantian yuantian.t...@freescale.com redefine variable clocks_per_pll as a struct member If there are multiple PLL clock nodes, this variable will get overwritten. Redefining it as a struct member can avoid that. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- These

[PATCH 1/1] booke/watchdog: refine and clean up the codes

From: Tang Yuantian yuantian.t...@freescale.com Basically, this patch does the following: 1. Move the codes of parsing boot parameters from setup-common.c to driver. In this way, code reader can know directly that there are boot parameters that can change the timeout. 2. Make boot parameter

[PATCH v2] clk: qoriq: Update the clock bindings

From: Tang Yuantian yuantian.t...@freescale.com Main changs include: - Clarified the clock nodes' version number - Fixed a issue in example Singed-off-by: Tang Yuantian yuantian.t...@freescale.com --- v2: - rename this binding - rewrite the description

[PATCH] powerpc/mpc85xx: Update clock nodes in device tree

From: Tang Yuantian yuantian.t...@freescale.com The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/boot/dts/fsl/b4420si-post.dtsi | 36

[PATCH v7] clk: corenet: Adds the clock binding

From: Tang Yuantian yuantian.t...@freescale.com Adds the clock bindings for Freescale PowerPC CoreNet platforms Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v7: - refined some properties' definitions v6: - splited the

[PATCH v6] clk: corenet: Adds the clock binding

From: Tang Yuantian yuantian.t...@freescale.com Adds the clock bindings for Freescale PowerPC CoreNet platforms Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v6: - splited the previous patch into 2 parts, one is for binding(this

[PATCH v5] powerpc/mpc85xx: Update the clock nodes in device tree

From: Tang Yuantian yuantian.t...@freescale.com The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v5: - refine the binding document -

[PATCH v4] powerpc/mpc85xx: Update the clock device tree nodes

From: Tang Yuantian yuantian.t...@freescale.com The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v4: - add binding document - update

[PATCH v5] cpufreq: powerpc: Add cpufreq driver for Freescale e500mc SoCs

From: Tang Yuantian yuantian.t...@freescale.com Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs which are capable of changing the CPU frequency dynamically Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v5: - enhance

[PATCH v3] powerpc/mpc85xx: Update the clock device tree nodes

From: Tang Yuantian yuantian.t...@freescale.com The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v3: - fix typo v2: - add t4240,

[PATCH v2] powerpc/mpc85xx: Update the clock device tree nodes

From: Tang Yuantian yuantian.t...@freescale.com The following SoCs will be affected: p2041, p3041, p4080, p5020, p5040, b4420, b4860, t4240 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v2: - add t4240, b4420, b4860 support

[PATCH] clk/mpc85xx: Update the compatible string

From: Tang Yuantian yuantian.t...@freescale.com The compatible string of clock is changed from *-2 to *-2.0 on chassis 2. So updated it accordingly. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- drivers/clk/clk-ppc-corenet.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[PATCH] of: remove the unnecessary of_node_put for of_parse_phandle_with_args()

From: Tang Yuantian yuantian.t...@freescale.com As the function itself says it is caller's responsibility to call the of_node_put(). So, remove it on success to keep the reference count correct. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- drivers/of/base.c | 3 --- 1 file

[PATCH v3] clk: add PowerPC corenet clock driver support

From: Tang Yuantian yuantian.t...@freescale.com This adds the clock driver for Freescale PowerPC corenet series SoCs using common clock infrastructure. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v3: - remove the module author

[PATCH v2] of/base: release the node correctly in of_parse_phandle_with_args()

From: Tang Yuantian yuantian.t...@freescale.com Call of_node_put() only when the out_args is NULL on success, or the node's reference count will not be correct because the caller will call of_node_put() again. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- v2: - modified

[PATCH v3] cpufreq: Add cpufreq driver for Freescale e500mc SoCs

From: Tang Yuantian yuantian.t...@freescale.com Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs which are capable of changing the frequency of CPU dynamically Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v3: -

[PATCH 2/2 v2] cpufreq: Add cpufreq driver for Freescale e500mc SoCs

From: Tang Yuantian yuantian.t...@freescale.com Add cpufreq driver for Freescale e500mc, e5500 and e6500 SoCs which are capable of changing the frequency of CPU dynamically Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v2: -

[PATCH 1/2 V2] clk: add PowerPC corenet clock driver support

From: Tang Yuantian yuantian.t...@freescale.com This adds the clock driver for Freescale PowerPC corenet series SoCs using common clock infrastructure. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- v2: add the document for device tree

[PATCH 2/3] clk: add PowerPC corenet clock driver support

From: Tang Yuantian yuantian.t...@freescale.com This adds the clock driver for Freescale PowerPC corenet series SOC using common clock infrastructure. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/platforms/Kconfig.cputype |

[PATCH 1/3] powerpc/mpc85xx: Update the clock device tree nodes

From: Tang Yuantian yuantian.t...@freescale.com The following SOCs will be affected: p2041, p3041, p4080, p5020, p5040 Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com --- arch/powerpc/boot/dts/fsl/p2041si-post.dtsi | 62 -

[PATCH 3/3] cpufreq: Add cpufreq driver for Freescale e500mc SOCs

From: Tang Yuantian yuantian.t...@freescale.com Add cpufreq driver for Freescale e500mc, e5500 and e6500 SOCs which are capable of changing the frequency of CPU dynamically Signed-off-by: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Li Yang le...@freescale.com ---

[PATCH][V3] powerpc: remove the PPC_CLOCK dependency

From: Tang Yuantian yuantian.t...@freescale.com Config FSL_SOC does not depend on PPC_CLOCK anymore since the following commit got merged: 93abe8e (clk: add non CONFIG_HAVE_CLK routines) Config CPM does not use PPC_CLOCK either currently. So remove them. PPC_CLOCK also keeps Freescale PowerPC

[PATCH 1/2][RFC] PowerPC/85xx: Add clock nodes support

From: Tang Yuantian yuantian.t...@freescale.com Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- take p5020 for example. arch/powerpc/boot/dts/fsl/p5020si-post.dtsi | 44 ++- arch/powerpc/boot/dts/fsl/p5020si-pre.dtsi |2 + 2 files changed, 45

[PATCH 2/2][RFC] clk: add PowerPC corenet clock support

From: Tang Yuantian yuantian.t...@freescale.com This adds the clock driver support for Freescale E500MC, E5500, E6500 series SoCs using common clock framework. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/platforms/Kconfig.cputype |1 + drivers/clk/Kconfig

[PATCH][RFC, upstream] powerpc: remove the PPC_CLOCK dependency

From: Tang Yuantian yuantian.t...@freescale.com config FSL_SOC and CPM do not really depend on PPC_CLOCK. So remove it. PPC_CLOCK also keeps powerpc archtecture from supporting COMMON_CLK. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- arch/powerpc/Kconfig |1 -

[PATCH][V2] powerpc: remove the PPC_CLOCK dependency

From: Tang Yuantian yuantian.t...@freescale.com config FSL_SOC and CPM do not really depend on PPC_CLOCK. So remove it. PPC_CLOCK also keeps powerpc archtecture from supporting COMMON_CLK. Signed-off-by: Tang Yuantian yuantian.t...@freescale.com --- v2: correct the title arch/powerpc/Kconfig

[PATCH] powerpc/85xx: Add p2020rdb-pc dts support

From: Tang Yuantian b29...@freescale.com Signed-off-by: Prabhakar Kushwaha prabha...@freescale.com Signed-off-by: Poonam Aggrwal poonam.aggr...@freescale.com Signed-off-by: Tang Yuantian b29...@freescale.com --- arch/powerpc/boot/dts/p2020rdb-pc.dts| 96 +