Re: [PATCH] powerpc: warn on emulation of dcbz instruction

2021-09-17 Thread Benjamin Herrenschmidt
On Thu, 2021-09-16 at 14:36 +, David Laight wrote: > > Does userspace accesses non-cached memory directly ? > > > It probably can if a driver mmaps PCI space directly into user space. > > That certainly works on x86-64. The posterchild for that is Xorg Cheers, Ben.

RE: [PATCH] powerpc: warn on emulation of dcbz instruction

2021-09-16 Thread David Laight
From: Christophe Leroy > Sent: 16 September 2021 08:24 > > Le 16/09/2021 à 09:16, Benjamin Herrenschmidt a écrit : > > On Thu, 2021-09-16 at 17:15 +1000, Benjamin Herrenschmidt wrote: > >> On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote: > >>> dcbz instruction shouldn't be used on

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

2021-09-16 Thread Christophe Leroy
Le 16/09/2021 à 09:16, Benjamin Herrenschmidt a écrit : On Thu, 2021-09-16 at 17:15 +1000, Benjamin Herrenschmidt wrote: On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote: dcbz instruction shouldn't be used on non-cached memory. Using it on non-cached memory can result in alignment

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

2021-09-16 Thread Benjamin Herrenschmidt
On Thu, 2021-09-16 at 17:15 +1000, Benjamin Herrenschmidt wrote: > On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote: > > dcbz instruction shouldn't be used on non-cached memory. Using > > it on non-cached memory can result in alignment exception and > > implies a heavy handling. > > > >

Re: [PATCH] powerpc: warn on emulation of dcbz instruction

2021-09-16 Thread Benjamin Herrenschmidt
On Wed, 2021-09-15 at 16:31 +0200, Christophe Leroy wrote: > dcbz instruction shouldn't be used on non-cached memory. Using > it on non-cached memory can result in alignment exception and > implies a heavy handling. > > Instead of silentely emulating the instruction and resulting in high >

[PATCH] powerpc: warn on emulation of dcbz instruction

2021-09-15 Thread Christophe Leroy
dcbz instruction shouldn't be used on non-cached memory. Using it on non-cached memory can result in alignment exception and implies a heavy handling. Instead of silentely emulating the instruction and resulting in high performance degradation, warn whenever an alignment exception is taken due to