Using '8' is correct. PCI interrupts are *always* level sensitive and
active
low.
Unless you use one of those strange bridges that stick not gates on the
PCI IRQ inputs :-) But I don't think that's the case on the 440EP.
More generally, the target interrupt descriptors (sense values, in
On Tue, 2008-03-04 at 21:39 +0100, Segher Boessenkool wrote:
Using '8' is correct. PCI interrupts are *always* level sensitive and
active
low.
Unless you use one of those strange bridges that stick not gates on the
PCI IRQ inputs :-) But I don't think that's the case on the 440EP.
More generally, the target interrupt descriptors (sense values, in
particular) in a device tree interrupt map describe the interrupts as
seen on the target interrupt controller, *not* as seen on this
(source)
interrupt domain. This should be obvious, but since the source
interrupt
On Tue, 2008-03-04 at 21:59 +0100, Segher Boessenkool wrote:
More generally, the target interrupt descriptors (sense values, in
particular) in a device tree interrupt map describe the interrupts as
seen on the target interrupt controller, *not* as seen on this
(source)
interrupt
I'm having two problems with PCI interrupts as described in bamboo.dts.
Here is are the properties in question:
/* Bamboo has all 4 IRQ pins tied together per slot */
interrupt-map-mask = f800 0 0 0;
interrupt-map =
/* IDSEL 1 */
0800 0 0 0
On Mon, Mar 03, 2008 at 06:02:33PM -0600, Hollis Blanchard wrote:
I'm having two problems with PCI interrupts as described in bamboo.dts.
Here is are the properties in question:
/* Bamboo has all 4 IRQ pins tied together per slot */
interrupt-map-mask = f800 0 0 0;
On Tue, 2008-03-04 at 11:59 +1100, David Gibson wrote:
Uh.. there's no binding written down, it's just encoded into uic.c.
But UIC doesn't use OpenPIC sensitivity encoding. Like FSL's IPIC, it
uses Linux IRQ_TYPE values from include/linux/irq.h which makes 8
level sensitive, active-low.
On Tue, Mar 04, 2008 at 12:42:47PM +1100, Benjamin Herrenschmidt wrote:
On Tue, 2008-03-04 at 11:59 +1100, David Gibson wrote:
Uh.. there's no binding written down, it's just encoded into uic.c.
But UIC doesn't use OpenPIC sensitivity encoding. Like FSL's IPIC, it
uses Linux IRQ_TYPE
Uh.. there's no binding written down, it's just encoded into uic.c.
But UIC doesn't use OpenPIC sensitivity encoding. Like FSL's IPIC,
it
uses Linux IRQ_TYPE values from include/linux/irq.h which makes 8
level sensitive, active-low.
On a related note: aren't we taking a risk here of
On Tue, Mar 04, 2008 at 03:07:50AM +0100, Segher Boessenkool wrote:
Uh.. there's no binding written down, it's just encoded into uic.c.
But UIC doesn't use OpenPIC sensitivity encoding. Like FSL's IPIC,
it
uses Linux IRQ_TYPE values from include/linux/irq.h which makes 8
level
On Mon, 03 Mar 2008 18:02:33 -0600
Hollis Blanchard [EMAIL PROTECTED] wrote:
I'm having two problems with PCI interrupts as described in bamboo.dts.
Here is are the properties in question:
/* Bamboo has all 4 IRQ pins tied together per slot */
interrupt-map-mask = f800 0 0 0;
On Mon, 2008-03-03 at 21:37 -0600, Josh Boyer wrote:
I plugged in an old 3Com ethernet card tonight. Slot 0. It was
assigned dev #4 IRQ 25. Using the device tree as-is, I could see
interrupts happening in /proc/interrupts but ethernet traffic failed.
Then I changed the sense level to 4
On Tuesday 04 March 2008, Josh Boyer wrote:
Is anybody using Bamboo PCI support right now? Does it actually work?
I plugged in an old 3Com ethernet card tonight. Slot 0. It was
assigned dev #4 IRQ 25. Using the device tree as-is, I could see
interrupts happening in /proc/interrupts but
On Tue, 2008-03-04 at 07:15 +0100, Stefan Roese wrote:
Using '8' is correct. PCI interrupts are *always* level sensitive and
active
low.
Unless you use one of those strange bridges that stick not gates on the
PCI IRQ inputs :-) But I don't think that's the case on the 440EP.
Ben.
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