On Wed, Mar 11, 2009 at 10:03:22AM -0600, Grant Likely wrote:
On Wed, Mar 11, 2009 at 9:50 AM, Johns Daniel johns.dan...@gmail.com wrote:
A semicolon at the end of the macro means that the for loop has an
empty body, and so TSEC/MDIO will not work with older device trees.
This fix only
Complete workaround for DTLB errata in MPC5121e processors of die M36P and
older (all currently existing versions).
Due to the bug, the hardware-implemented LRU algorythm always goes to way 1 of
the TLB. This fix implements the proposed software workaround in form of a LRW
table for chosing
Forgot to mention: The patch is based on denx git tree head 'ads5121', but
it should apply without problem (some offset at most) to mainline.
Best regards,
--
David Jander
Protonic Holland.
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
Patch to limit NEC fixup to SBC310, following similar patch to SBC610 by Tony
Breeds: 368a12117dd8abf6eaefa37c21ac313b517128b9
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
Hi Kumar,
The sbc310 patches have been added to your next tree. This patch is
needed to stop the same problem
What does cat /proc/cpuinfo show on this board?
+#ifdef CONFIG_PPC_MPC512x
+/* MPC512x: workaround for errata in die M36P and earlier:
+ * Implement LRW for TLB way.
+ */
This errata impacts a number of cores and so we should make this a CPU
feature fixup rather than #ifdef code.
+
On Mar 13, 2009, at 5:26 AM, David Jander wrote:
Forgot to mention: The patch is based on denx git tree head
'ads5121', but
it should apply without problem (some offset at most) to mainline.
Best regards,
Out of interest did this version produce better performance on the
benchmarks
Hi all !
I am currently facing a big problem on my MPC8272ADS development board.
I have tried to use the /dev/ttyCPM1 port in order to send data over
the serial cable to another device.
This is just not working but nothing is sent, my DTR signal is down:
cat /proc/tty/driver/ttyCPM
0: uart:CPM
Hi Jean-Michel,
On Friday 13 March 2009 14:38:55 Jean-Michel Hautbois wrote:
Hi all !
I am currently facing a big problem on my MPC8272ADS development board.
I have tried to use the /dev/ttyCPM1 port in order to send data over
the serial cable to another device.
This is just not working
On Friday 13 March 2009 14:22:22 Kumar Gala wrote:
On Mar 13, 2009, at 5:26 AM, David Jander wrote:
Forgot to mention: The patch is based on denx git tree head
'ads5121', but
it should apply without problem (some offset at most) to mainline.
Best regards,
Out of interest
On Friday 13 March 2009 14:21:57 Kumar Gala wrote:
What does cat /proc/cpuinfo show on this board?
# cat /proc/cpuinfo
processor : 0
cpu : e300c4
clock : 400.00MHz
revision: 1.0 (pvr 8086 2010)
bogomips: 99.84
timebase: 5000
2009/3/13 Laurent Pinchart laure...@cse-semaphore.com:
Hi Jean-Michel,
Support for the modem control lines has been added in v2.6.27-rc2. You will
need to declare the modem control lines in your device tree. See
Documentation/powerpc/dts-bindings/fsl/cpm_qe/serial.txt for more information.
Hi Jean-Michel,
On Friday 13 March 2009 15:20:24 Jean-Michel Hautbois wrote:
2009/3/13 Laurent Pinchart laure...@cse-semaphore.com:
Support for the modem control lines has been added in v2.6.27-rc2. You
will need to declare the modem control lines in your device tree. See
From: David Jander david.jan...@protonic.nl
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software workaround in
form of a LRW table for chosing the TLB-way.
On Mar 13, 2009, at 9:24 AM, David Jander wrote:
On Friday 13 March 2009 14:21:57 Kumar Gala wrote:
What does cat /proc/cpuinfo show on this board?
# cat /proc/cpuinfo
processor : 0
cpu : e300c4
clock : 400.00MHz
revision: 1.0 (pvr 8086 2010)
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
arch/powerpc/boot/dts/gef_ppc9a.dts |
The following series implements basic support for the GE Fanuc PPC9A, a
6U single board computer, based on the Freescale MPC8641D.
This series provides:
- The ability to boot the board with a serial console.
- Ethernet support.
- Sata and USB.
- Support for one of the 2 available watchdog
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the default config file for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch martyn.we...@gefanuc.com
---
Update ps3_defconfig.
Sets these options:
CONFIG_PS3_VRAM=m
CONFIG_BLK_DEV_DM=m
CONFIG_USB_HIDDEV=y
CONFIG_EXT4_FS=y
Signed-off-by: Geoff Levand geoffrey.lev...@am.sony.com
---
Ben,
Here is an updated patch (v2). I removed CONFIG_DYNAMIC_FTRACE
from this one.
Please send upstream
Hi all,
I haven't checked the kernel source in the few weeks since ISA 2.06 was
released but I suspect that the default Program Priority level hasn't
been changed in the kernel yet.
Program Priority:
Per ISA 2.06: Section 3.1 (page 671) titled Program Priority
Registers, The 'normal' process
Hi all,
Those of us working on the POWER toolchain can envision a certain class
of customers who may benefit from intelligently disabling certain
register class enable bits on context switches, i.e. not disabling by
default.
Currently, per process, if the MSR enable bits for FPs, VRs or VSRs are
From: Felix Radensky fe...@embedded-sol.com
Date: Wed, 11 Mar 2009 10:56:31 +0200
Benjamin Herrenschmidt wrote:
emac: Fix clock control for 405EX and 405EXr chips
The EMAC variant in the 405EX and 405EXr chips needs the 440EP type clock
control workaround to avoid lockups of the Rx side
From: Jan-Bernd Themann ossth...@de.ibm.com
Date: Thu, 12 Mar 2009 16:20:18 +0100
This patch fixes the circular locking problem by changing the locking strategy
concerning the logging of firmware handles.
Signed-off-by: Jan-Bernd Themann them...@de.ibm.com
Applied, thanks.
On Mar 13, 2009, at 3:23 PM, Ryan Arnold wrote:
Hi all,
Those of us working on the POWER toolchain can envision a certain
class
of customers who may benefit from intelligently disabling certain
register class enable bits on context switches, i.e. not disabling by
default.
Currently, per
On Fri, 2009-03-13 at 10:16 -0500, Kumar Gala wrote:
From: David Jander david.jan...@protonic.nl
Complete workaround for DTLB errata in e300c2/c3/c4 processors.
Due to the bug, the hardware-implemented LRU algorythm always goes to way
1 of the TLB. This fix implements the proposed software
+BEGIN_FTR_SECTION
+ b TlbWo/* Code for TLB-errata workaround doesn't fit here */
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_DTLB_SW_LRU)
+RFTlbWo:
Can you use nicer label names ? :-)
Also, that's a lot of code for such a hot path...
Cheers,
Ben.
On Mar 13, 2009, at 4:26 PM, Benjamin Herrenschmidt wrote:
+BEGIN_FTR_SECTION
+ b TlbWo/* Code for TLB-errata workaround doesn't fit
here */
+END_FTR_SECTION_IFSET(CPU_FTR_NEED_DTLB_SW_LRU)
+RFTlbWo:
Can you use nicer label names ? :-)
Also, that's a lot of code for such a hot
If these applications are aware they are heavy users (of FP, VMX, VSX)
can we not use a sysctl()? Doing so wouldn't be that difficult.
I think trying to do something based on a runtime heuristic sounds a
bit iffy.
Another option might be simply to say that if an app has used FP, VMX
Hi Guys:
Sequoia uses on board discrete memory with one rank. So one chip
select would be fine.
Turning on both won't matter, since the other cs is never used.
Feng Kan
Stefan Roese wrote:
On Wednesday 11 March 2009, Valentine Barshak wrote:
I've been looking at the docs once again
hi,
I've configured SCC1 to be serial uart driver.
(in addition to SMC1 SMC2 that were already configured
as UARTs).
Now I can see these defines in .config file:
CONFIG_SERIAL_CPM_SCC1=y
CONFIG_SERIAL_CPM_SMC1=y
CONFIG_SERIAL_CPM_SMC2=y
When the kernal starts I see these log messages:
ttyCPM0
More specifically, I envision restart to work like this:
1) user invokes user-land utility (e.g. cr --restart ...
2) 'cr' will create a new container
3) 'cr' will start a child in that container
process 1 in its private namespaces.
4) child will create rest of tree (in kernel or in user
hi,
I've configured SCC1 to be serial uart driver.
(in addition to SMC1 SMC2 that were already configured
as UARTs).
Now I can see these defines in .config file:
CONFIG_SERIAL_CPM_SCC1=y
CONFIG_SERIAL_CPM_SMC1=y
CONFIG_SERIAL_CPM_SMC2=y
When the kernal starts I see these log messages:
ttyCPM0
Ben,
We're looking at the fixes you put in place for the various PCI errors
and we think this is the solution we need for our system, a GE Fanuc CM6
PPC board (single 8641), but your patches appear to apply either to
2.6.24 or 2.6.25, and we have 2.6.23. Do you know of any similar work
done
On Sat, Mar 14, 2009 at 09:45:51AM +1100, Benjamin Herrenschmidt wrote:
If these applications are aware they are heavy users (of FP, VMX, VSX)
can we not use a sysctl()? Doing so wouldn't be that difficult.
I think trying to do something based on a runtime heuristic sounds a
bit iffy.
On Fri, Mar 13, 2009 at 1:56 PM, liran raz liranrazli...@gmail.com wrote:
Does anyone know what I'm missing? or what do I need to configure
in order to have: /dev/ttyCPM2 ?
My guess is that you don't have udev or mdev running.
--
Timur Tabi
Linux kernel developer at Freescale
On Fri, Mar 13, 2009 at 03:52:26PM +, Martyn Welch wrote:
Support for the PPC9A VME Single Board Computer from GE Fanuc (PowerPC
MPC8641D).
This is the basic board support for GE Fanuc's PPC9A, a 6U single board
computer, based on Freescale's MPC8641D.
Signed-off-by: Martyn Welch
On Sat, 2009-03-14 at 09:45 +1100, Benjamin Herrenschmidt wrote:
If these applications are aware they are heavy users (of FP, VMX, VSX)
can we not use a sysctl()? Doing so wouldn't be that difficult.
I think trying to do something based on a runtime heuristic sounds a
bit iffy.
Both of these thoughts came to mind. I don't have a particular
preference. It's very likely that a process which results in the
enabling of FP,VMX, or VSX may continue to use the facility for the
duration of it's lifetime. Threads would be even more likely to exhibit
this behavior.
The
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