Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 02:34:15:
On Tue, 2009-10-06 at 01:35 +0200, Joakim Tjernlund wrote:
Well, if the HW has the ability to enforce trap when store with !
DIRTY,
Yes, provided that the kernel invalidates the TLB too so the next
access
Rex Feany rfe...@mrv.com wrote on 06/10/2009 00:42:18:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
I got this oops:
Unable to handle kernel paging request for data at address 0x
Faulting instruction address: 0xc000e110
Oops: Kernel access of bad area,
The creation of the flattened device tree depended on the compiler
putting the constant strings for an object in a section with a
particular name. This was changed with recent compilers. Do this
explicitly instead.
Without this patch, iseries kernels may silently not boot when built with
some
I assumed it was NIP because ... I'm not sure why. TRAP() above
dereferences regs, and that didn't fail, but I didn't see that until
now.
Yes, it is a bit strange though that the kernel isn't allowed to read from
NULL. Is that expected?
Yes, that's absolutely expected :-) You really
On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote:
Yes, I would too but TLB Miss knows nothing about load/store, protection etc.
because DSISR isn't set. So I cannot see any other way than the TLB Error way.
Hrm... that MMU really sucks more than I thought :-(
I'll go read the manual
Hi Ben,
On Tue, 6 Oct 2009 17:28:47 +1100 Stephen Rothwell s...@canb.auug.org.au
wrote:
The creation of the flattened device tree depended on the compiler
putting the constant strings for an object in a section with a
particular name. This was changed with recent compilers. Do this
Adds documentation for the size parameter of Freescale's QorIQ
based cache-sram
Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
---
v2: No change
Documentation/kernel-parameters.txt |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git
Adds documentation for Freescale's QorIQ based cache-sram as under:-
* How to enable it from a low level driver
* How to set its size
Signed-off-by: Vivek Mahajan vivek.maha...@freescale.com
---
v2: No change
Documentation/powerpc/fsl_85xx_cache_sram.txt | 31 +
1
This adds QorIQ based Cache-SRAM support as under:-
* A small abstraction over powerpc's remote heap allocator
* Exports mpc85xx_cache_sram_alloc()/free() APIs
* Supports only one contiguous SRAM window
* Defines FSL_85XX_CACHE_SRAM and its base address
Signed-off-by: Vivek Mahajan
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 08:45:47:
On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote:
Yes, I would too but TLB Miss knows nothing about load/store, protection
etc.
because DSISR isn't set. So I cannot see any other way than the TLB Error
Hmm.. currently I prefer to remove it, because it is not a uc101 special
wdt driver. When this wdt driver go in mainline, it is easy to readd it
to this board support.
Great, another one interested in a mainline GPIO-WDT-driver :) I'll check again
what happened last time and summarize it
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 03:52:15:
\
So how does this look? Does it change anything?
It should as the previous way was way off :(
diff --git a/arch/powerpc/mm/fault.c b/arch/powerpc/mm/fault.c
index c33c6de..08a392f 100644
---
No, use get_user() not __get_user() or if you use the later, also use
access_ok(), and test the result in case it errors (if it does, you
probably want to just goto bad access and SEGV).
OK, lets see what this gives us:
Hrm... did you change anything ? :-)
Ben.
diff --git
Hello,
I'm newbie in PPCLinux, don't know I'm right here.
I made a ports to an AVNET FX12 minimodul and custom board (FX40/FX60) based
on linuxppc found on http://git.xilinx.com/ (ppc405 processor).
All works fine, but I can use/configure only the half memory size available
in the dts (for
Betreff: XILINX memory layout - physical memory
Hello,
I'm newbie in PPCLinux, don't know I'm right here.
I made a ports to an AVNET FX12 minimodul and custom board (FX40/FX60) based
on linuxppc found on http://git.xilinx.com/ (ppc405 processor).
All works fine, but I can use/configure only
Hi there,
I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard time
getting it to boot without a screen attached, but I eventually managed to
(yaboot was the culprit). However, this machine is SMU-based, and I couldn't
find a way to enable the equivalent of the PMU's server_mode
On Tue, 2009-10-06 at 11:16 +0200, Romain Goyet wrote:
Hi there,
I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard
time getting it to boot without a screen attached, but I eventually
managed to (yaboot was the culprit). However, this machine is
SMU-based, and I
On Tue, 2009-10-06 at 11:16 +0200, Romain Goyet wrote:
I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard
time getting it to boot without a screen attached, but I eventually
managed to (yaboot was the culprit).
Out of curiosity, how did you solve this? I still have an
No, use get_user() not __get_user() or if you use the later, also use
access_ok(), and test the result in case it errors (if it does, you
probably want to just goto bad access and SEGV).
OK, lets see what this gives us:
Hrm... did you change anything ? :-)
Yes, see below
Ben.
On Tue, 2009-10-06 at 12:58 +0200, Joakim Tjernlund wrote:
Here I don't care if err. insn will be 0 if it fails and the following
if will be false
I'd rather you use get_user() so it does access_ok().
Else, you can probably manufacture some code that will make the kernel
access some MMIO
Hi Benjamin !
Actually I saw a post where you mentioned this tool on Google. I then
searched it for like an hour or so, but really couldn't find it. That's why
I ended up posting on this mailing list. I'm really glad you're on it by the
way ! Anyway, like I said : I really looked for this tool,
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 13:06:26:
From:
Benjamin Herrenschmidt b...@kernel.crashing.org
To:
Joakim Tjernlund joakim.tjernl...@transmode.se
Cc:
linuxppc-...@ozlabs.org linuxppc-...@ozlabs.org, Rex Feany
rfe...@mrv.com, Scott Wood
Hi Michel :-)
Acutally I didn't figure it out by myself :
http://saintaardvarkthecarpeted.com/blog/archive/2005/02/THE_WINE_OF_BOOT.html
However, here's my 2 cents about it :
1/ The fix (removing screen line in ofboot.b on yaboot partition) doesn't
work with all versions of the yaboot binary.
Hi again Benjamin !
That's allright, I'll ping you next month ! Thanks for the help !
- Romain
On Tue, Oct 6, 2009 at 12:51 PM, Benjamin Herrenschmidt
b...@kernel.crashing.org wrote:
On Tue, 2009-10-06 at 12:31 +0200, Romain Goyet wrote:
Hi Benjamin !
Actually I saw a post where
On Tue, 2009-10-06 at 13:44 +0200, Romain Goyet wrote:
Acutally I didn't figure it out by myself :
http://saintaardvarkthecarpeted.com/blog/archive/2005/02/THE_WINE_OF_BOOT.html
However, here's my 2 cents about it :
1/ The fix (removing screen line in ofboot.b on yaboot partition)
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 13:06:26:
On Tue, 2009-10-06 at 12:58 +0200, Joakim Tjernlund wrote:
Here I don't care if err. insn will be 0 if it fails and the following
if will be false
I'd rather you use get_user() so it does access_ok().
Else,
On Tue, 2009-10-06 at 15:05 +1100, Anton Blanchard wrote:
Hi Steve,
I think this may do better in a file like:
arch/powerpc/kernel/trace.h
You can look at the sample code and Makefile in samples/trace_events/
that shows how to make it work outside the include/trace/events
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
This patch cleans up drivers/cpuidle/cpuidle.c
Earlier cpuidle assumed pm_idle as the default idle loop. Break that
assumption and make it more generic. cpuidle_idle_call() which is the
main idle loop of cpuidle is to be called by
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
Implement a list based registering mechanism for architectures which
have multiple sets of idle routines which are to be registered.
Currently, in x86 it is done by merely setting pm_idle = idle_routine
and managing this pm_idle
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
This patch cleans up x86 of all instances of pm_idle.
pm_idle which was earlier called from cpu_idle() idle loop
is replaced by cpuidle_idle_call.
x86 also registers to cpuidle when the idle routine is selected,
by populating the
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
This patch enables the cpuidle option in Kconfig for pSeries.
Currently cpuidle infrastructure is enabled only for x86 and ARM.
This code is almost completely borrowed from x86 to enable
cpuidle for pSeries.
Signed-off-by: Arun R
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
This patch removes the routines, pseries_shared_idle_sleep and
pseries_dedicated_idle_sleep, since this is implemented as a part
of arch/powerpc/platform/pseries/processor_idle.c
Also, similar to x86, call cpuidle_idle_call from
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
In arch/powerpc/kernel/idle.c create a default_idle() routine by moving
the failover condition of the cpu_idle() idle loop. This is needed by
cpuidle infrastructure to call default_idle when other idle routines
are not yet
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
This patch creates arch/powerpc/platforms/pseries/processor_idle.c,
which implements the cpuidle infrastructure for pseries.
It implements a pseries_cpuidle_loop() which would be the main idle loop
called from cpu_idle(). It makes
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 08:45:47:
On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote:
Yes, I would too but TLB Miss knows nothing about load/store, protection
etc.
because DSISR isn't set. So I cannot see any other way than the TLB Error
pasemi_defconfig hasn't been updated for a year.
Mostly a refresh of defaults, but this also disables 64K pages.
Signed-off-by: Olof Johansson o...@lixom.net
diff --git a/arch/powerpc/configs/pasemi_defconfig
b/arch/powerpc/configs/pasemi_defconfig
index 4f8681c..20ba0cf 100644
---
Weird, I see my address in the to: line but I never got a copy in my inbox.
On Mon, Oct 05, 2009 at 05:27:56PM +0400, Valentine Barshak wrote:
Not all pasemi mac interfaces can have a phy attached.
For example, XAUI has no phy and phydev is NULL for it.
In this case ethtool get settings causes
On Mon, Oct 05, 2009 at 05:31:24PM +0400, Valentine Barshak wrote:
Add ethtool set settings to pasemi_mac_ethtool.
Signed-off-by: Valentine Barshak vbars...@ru.mvista.com
Acked-by: Olof Johansson o...@lixom.net
___
Linuxppc-dev mailing list
On Tue, Oct 06, 2009 at 09:11:22PM +1100, Benjamin Herrenschmidt wrote:
On Tue, 2009-10-06 at 11:16 +0200, Romain Goyet wrote:
Hi there,
I have this Quad G5 here, running GentooPPC64. Runs fine. Had a hard
time getting it to boot without a screen attached, but I eventually
managed
* Arun R Bharadwaj a...@linux.vnet.ibm.com [2009-10-06 20:54:21]:
Hi
Please consider this for inclusion into the testing tree.
This patchset introduces cpuidle infrastructure to POWER, prototyping
for pSeries, and also does a major refactoring of current x86 idle
power management and a
Hi, Greg K-H,
I think we have put in all the suggested changes. Are you planning to
put it into your tree? Or is there something we need to do?
Thank you,
Julie.
-Original Message-
From: Julie Zhu [mailto:julie@xilinx.com]
Sent: Monday, September 21, 2009 4:08 PM
To: John
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009
08:45:47:
On Tue, 2009-10-06 at 08:15 +0200, Joakim Tjernlund wrote:
Yes, I would too but TLB Miss knows nothing about load/store, protection
etc.
because DSISR isn't set. So I cannot see any other way than the
On Tue, Oct 06, 2009 at 11:07:32AM -0600, Julie Zhu wrote:
Hi, Greg K-H,
I think we have put in all the suggested changes. Are you planning to
put it into your tree? Or is there something we need to do?
I will queue it up in my tree.
thanks,
greg k-h
On Tue, 2009-10-06 at 22:05 +0530, Arun R Bharadwaj wrote:
Also, the per-cpu nature of registration/unregistration of cpuidle
has been maintained as ACPI needs this.
Right, so can't we ditch that and have acpi default to the lowest common
C-state and warn when various cpus report different
We have an embedded prouct using 8270 based on pq2fads with MontaVista 4.0.1,
kernel 2.6.10. We recently had a need to increase memory. We can populate
1x256M, 2x256M, 1x512M or 2X512M. In all configurations with at least 512M, it
we set memory size to 496M or greater system crashes on boot up
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 06/10/2009 02:34:15:
On Tue, 2009-10-06 at 01:35 +0200, Joakim Tjernlund wrote:
Well, if the HW has the ability to enforce trap when store with !
DIRTY,
Yes, provided that the kernel invalidates the TLB too so the next
access
After some more thinking I don't think I do TLB Miss/Error correctly yet.
The problem is ACCESSED. Since I don't know if load or store in TLB Miss
I must choose:
- Assume load and do what you do above. That will incorrectly
set ACCESSED on store ops when mapped as RO(plus whatever more I
Allright, did a bit of reading of doco and code..
Doco isn't totally clear though. At some stage, it -hints- that in case
of a TLB error (match on EA/ASID but incorrect
protection/valid/changed/...) the offending TLB entry is automatically
invalidated. Do you know if that is correct ?
I would
Well, I've got to start somewhere...
So here goes. I've begun the work to merge and clean up the OF device
tree handling code and this is my first set of patches. Not fully
tested yet, but I'm getting them out to the lists so that I can start
responding to comments and collecting acks. This
In preparation to prune things out of the Sparc, PowerPC and Microblaze
asm/prom.h files, change the #include statements to ensure that
even if asm/prom.h is included first, linux/of.h gets to determine the
order in which files are processed.
This patch adds a #include linux/of.h to each of the
Merge of common code duplicated between Sparc, PowerPC and Microblaze
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 10 --
arch/powerpc/include/asm/prom.h| 12
arch/sparc/include/asm/prom.h | 12
Merge of common code duplicated between Sparc, PowerPC and Microblaze
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 20
arch/powerpc/include/asm/prom.h| 20
arch/sparc/include/asm/prom.h |
Merge of common code duplicated between Sparc, PowerPC and Microblaze
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/sparc/include/asm/prom.h |3 ---
include/linux/of.h|3 +++
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git
Add a common header file for working with the flattened device tree
data structure and merge the shared data tags used by Microblaze and
PowerPC
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 12 +---
arch/powerpc/include/asm/prom.h|
Merge common code for working with Flattened Device Tree data structure
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 30 --
arch/powerpc/include/asm/prom.h| 31 ---
Merge common code between PowerPC and Microblaze
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 16
arch/powerpc/include/asm/prom.h| 17 -
include/linux/of.h | 16
3 files
Merge common code between Microblaze and PowerPC
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 12
arch/powerpc/include/asm/prom.h| 20
include/linux/of.h | 23 +++
3
Merge common code between Sparc, PowerPC and Microblaze.
Sparc differs in the implementation at this point, so this patch uses
a #ifdef to handle sparc differently for now. The merging of
implementations will occur in a later patch
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
Merge common flattened device tree code between Microblaze and PowerPC
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 11 ---
arch/powerpc/include/asm/prom.h| 10 --
include/linux/of_fdt.h | 14 ++
Merge common prototypes used by Microblaze and PowerPC
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/include/asm/prom.h | 12
arch/powerpc/include/asm/prom.h| 14 --
include/linux/of_fdt.h | 13 +
3 files
Merge common code between Microblaze and PowerPC, and make it available
to Sparc
Signed-off-by: Grant Likely grant.lik...@secretlab.ca
---
arch/microblaze/kernel/prom.c | 23 ---
arch/powerpc/kernel/prom.c| 23 ---
drivers/of/base.c |
On Tue, Oct 6, 2009 at 10:29 PM, Grant Likely grant.lik...@secretlab.ca wrote:
Well, I've got to start somewhere...
So here goes. I've begun the work to merge and clean up the OF device
tree handling code and this is my first set of patches. Not fully
tested yet, but I'm getting them out to
Hi Grant,
Just first obvious thing:
On Tue, 06 Oct 2009 22:30:59 -0600 Grant Likely grant.lik...@secretlab.ca
wrote:
diff --git a/arch/microblaze/include/asm/prom.h
b/arch/microblaze/include/asm/prom.h
index 64e8b3a..5f461f0 100644
--- a/arch/microblaze/include/asm/prom.h
+++
On Tue, 2009-10-06 at 22:30 -0600, Grant Likely wrote:
--- /dev/null
+++ b/include/linux/of_fdt.h
@@ -0,0 +1,30 @@
+/*
+ * Definitions for working with the Flattened Device Tree data format
+ *
+ * Copyright (C) 1996-2005 Paul Mackerras.
+ *
+ * Updates for PPC64 by Peter Bergner David
On Wed, Oct 7, 2009 at 14:49, Grant Likely grant.lik...@secretlab.ca wrote:
On Tue, Oct 6, 2009 at 10:29 PM, Grant Likely grant.lik...@secretlab.ca
wrote:
So here goes. I've begun the work to merge and clean up the OF device
tree handling code and this is my first set of patches. Not fully
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