Signed-off-by: Geoff Levand geoffrey.lev...@am.sony.com
---
Hi Ben,
Please send upstream if it is not too late.
Is the current one broken? Maybe a commit message would be nice :-P
Mikey
-Geoff
arch/powerpc/configs/ps3_defconfig | 211 +-
---
1
On POWER6 systems RA needs to be the base and RB the index.
If they are reversed you take a misdirect hit.
Signed-off-by: Mike Wolf mjw...@us.ibm.com
Looks good thanks Mike!
Acked-by: Michael Neuling mi...@neuling.org
--- altivec.orig/arch/powerpc/include/asm/ppc_asm.h
# size vmlinux
text data bss dec hex filename
9812942 1982496 1105228 12900666 c4d93a vmlinux
... over kernel releases with pseries_defconfig:
text databss dec hex
2.6.32-rc1 9872090 1971184 1105236
2.6.28 86470801699460 780472 11127012a9c8e4
2.6.27 74616631505796 774400 9741859 94a623
If you compile 28 with the 27 pseries_config, you lose most of this
1.2MB text bloat.
If we remove just FUNCTION_TRACER and STACK_TRACER from 28 we gain back
about 600K.
2.6.28 8647080 1699460 780472 11127012a9c8e4
2.6.27 7461663 1505796 774400 9741859 94a623
If you compile 28 with the 27 pseries_config, you lose most of this
1.2MB text bloat.
If we remove just FUNCTION_TRACER and STACK_TRACER from 28 we gain back
about
The architecture defines that if MSR PR is set we are in problem state
irrespective of the HV bit. This fixes perf events to reflect this.
Signed-off-by: Michael Neuling mi...@neuling.org
CC: pau...@samba.org
---
Tested on PHYP and BML.
This could go back into 31 too with s/event/counters/g
The architecture defines that if MSR PR is set we are in problem state
irrespective of the HV bit. This fixes perf events to reflect this.
Also, on bare metal systems, samples taken in Linux will now be reported
as kernel rather than hypervisor.
Signed-off-by: Michael Neuling mi
irqs_disabled_flags is #defined in linux/irqflags.h when
CONFIG_TRACE_IRQFLAGS_SUPPORT is enabled.
This fixes the case when someone needs to include both linux/irqflags.h
and asm/hw_irq.h.
Signed-off-by: Michael Neuling mi...@neuling.org
---
I'm not sure if this is the right fix. We could just
.
Signed-off-by: Michael Neuling mi...@neuling.org
---
I think you can just remove irqs_disabled_flags as we always have
CONFIG_TRACE_IRQFLAGS_SUPPORT (for both 32 and 64).
Ok, thanks kumar.
arch/powerpc/include/asm/hw_irq.h |5 -
1 file changed, 5 deletions(-)
Index: linux-2.6-ozlabs/arch
This is the really low level of guest entry/exit code.
Book3s_64 has an SLB, which stores all ESID - VSID mappings we're
currently aware of.
The segments in the guest differ from the ones on the host, so we need
to switch the SLB to tell the MMU that we're in a new context.
So we store
snip
+static void invalidate_pte(struct hpte_cache *pte)
+{
+ dprintk_mmu(KVM: Flushing SPT %d: 0x%llx (0x%llx) - 0x%llx\n,
+ i, pte-pte.eaddr, pte-pte.vpage, pte-host_va);
+
+ ppc_md.hpte_invalidate(pte-slot, pte-host_va,
+MMU_PAGE_4K,
This is the really low level of guest entry/exit code.
Book3s_64 has an SLB, which stores all ESID - VSID mappings we're
currently aware of.
The segments in the guest differ from the ones on the host, so we
need
to switch the SLB to tell the MMU that we're in a new context.
In message 4b0c8ce3.4010...@austin.ibm.com you wrote:
This patch provides the kernel DLPAR infrastructure in a new filed named
dlpar.c. The functionality provided is for acquiring and releasing a resourc
e
from firmware and the parsing of information returned from the
In message 31581.1259115...@neuling.org you wrote:
In message 4b0c8ce3.4010...@austin.ibm.com you wrote:
This patch provides the kernel DLPAR infrastructure in a new filed named
dlpar.c. The functionality provided is for acquiring and releasing a resou
rc
e
from firmware and the
-by: Neil Campbell ne...@linux.vnet.ibm.com
Thanks for this Neil!
Acked-by: Michael Neuling mi...@neuling.org
Cc: sta...@kernel.org
---
diff --git a/arch/powerpc/kernel/align.c b/arch/powerpc/kernel/align.c
index a5b632e..f0c624f 100644
--- a/arch/powerpc/kernel/align.c
+++ b/arch/powerpc/kernel
In message 20091216043933.ga9...@in.ibm.com you wrote:
This patch ports the kprobe-based event tracer to powerpc. This patch
is based in x86 port. This brings powerpc on par with x86.
Port the following API's to ppc for accessing registers and stack entries
from pt_regs.
-
In message 4b29c3e3.3060...@redhat.com you wrote:
Hi Michael,
Michael Neuling wrote:
+
+static const struct pt_regs_offset regoffset_table[] = {
+ REG_OFFSET_NAME(gpr[0]),
+ REG_OFFSET_NAME(gpr[1]),
+ REG_OFFSET_NAME(gpr[2]),
+ REG_OFFSET_NAME(gpr[3]),
+ REG_OFFSET_NAME(gpr
In message 4b29ee5f.9020...@linux.vnet.ibm.com you wrote:
Hi Michael,
Michael Neuling wrote:
Index: linux-2.6-tip/arch/powerpc/include/asm/ptrace.h
===
--- linux-2.6-tip.orig/arch/powerpc/include/asm/ptrace.h
+++ linux-2.6
In message 4b2b0ebf.5040...@linux.vnet.ibm.com you wrote:
Michael Neuling wrote:
In message 4b29ee5f.9020...@linux.vnet.ibm.com you wrote:
Hi Michael,
Michael Neuling wrote:
+ * regs_get_argument_nth() - get Nth argument at function call
+ * @regs: pt_regs which contains
Subject: Re: [PATCH] powerpc: update ibm,client-architecture
Please give this a more appropriate name.
In order to boot with more than 64 cores on machines that support the
ibm,client-architecture RTAS call a new field has been added to the
structure. This patch updates that field and
Subject: Re: [PATCH] powerpc: update ibm,client-architecture
Please give this a more appropriate name.
Any suggestions?
Something that's more descriptive of what the patch does. Say Add
max CPU nodes field to ibm,client-architecture call
In order to boot with more
OK.
+ W(NR_CPUS/4), /* max cores supported */
FYI reading the PAPR, this comment should technically be max 'cpu'
nodes presented.
I applied a disambiguation filter to the comment since cpus can mean a
lot of things these days ( ie hardware threads,
In message 4b317324.3000...@redhat.com you wrote:
Michael Neuling wrote:
In message 4b2b934c.1060...@redhat.com you wrote:
Mahesh Jagannath Salgaonkar wrote:
Michael Neuling wrote:
In message 4b29ee5f.9020...@linux.vnet.ibm.com you wrote:
Hi Michael,
Michael Neuling wrote
: *** [sub-make] Error 2
Looks like #ifdef CONFIG_PM in arch/powerpc/sysdev/ipic.c should be
CONFIG_SUSPEND. d49747bdfb2ddebea24d1580da55b79d093d48a9 introduced
this.
Maybe this fixes it?
Fix build when we have CONFIG_PM but no CONFIG_SUSPEND.
Signed-off-by: Michael Neuling mi...@neuling.org
I get the following compile error with ftrace with mainline with the
attached config (made with randconfig)
/home/mikey/src/linux-2.6-ozlabs/arch/powerpc/kernel/ftrace.c: In function
‘__ftrace_make_call’:
/home/mikey/src/linux-2.6-ozlabs/arch/powerpc/kernel/ftrace.c:443: error:
dereferencing
In message 20090206060527.369616...@goodmis.org you wrote:
From: Steven Rostedt srost...@redhat.com
Michael Neuling reported a compile bug when dynamic ftrace was
configured in and modules were not. This was due to the ftrace
code referencing module specific structures.
Reported
question for the ppc folks why does the print symbol magic format str
ing
thing print a dot symbol and not the real function name?
Should that be fixed instead?
We have two symbols for each function, foo points to the function
descriptor, and .foo points to the instruction text. If
arch/powerpc/oprofile/cell/spu_profiler.c is missing a asm/time.h
include which is required for ppc_proc_freq. This can cause compile
failures for some config combinations.
Signed-off-by: Michael Neuling mi...@neuling.org
---
This is against mainline, so should be pushed up soon-ish
arch
arch/powerpc/platforms/pseries/hotplug-memory.c uses
remove_section_mapping() but doesn't include sparsemem.h which defines
it. This can cause compilation fails for some configs.
Signed-off-by: Michael Neuling mi...@neuling.org
---
This is against mainline, so should be pushed up soon-ish
cbe_cpufreq.c uses cbe_cpufreq_has_pmi which is provided by
cbe_cpufreq_pmi.c. Hence CBE_CPUFREQ depends on CBE_CPUFREQ_PMI.
Signed-off-by: Michael Neuling mi...@neuling.org
---
I'm not 100% sure is this the right fix. Should CBE_CPUFREQ really
depend on CBE_CPUFREQ_PMI?
arch/powerpc
cbe_cpufreq.c uses cbe_cpufreq_has_pmi which is provided by
cbe_cpufreq_pmi.c. Hence CBE_CPUFREQ depends on CBE_CPUFREQ_PMI.
=20
Signed-off-by: Michael Neuling mi...@neuling.org
---
I'm not 100% sure is this the right fix. Should CBE_CPUFREQ really
depend on CBE_CPUFREQ_PMI
cbe_cpufreq.c uses cbe_cpufreq_has_pmi which is provided by
cbe_cpufreq_pmi.c. Hence CBE_CPUFREQ depends on CBE_CPUFREQ_PMI.
=20
Signed-off-by: Michael Neuling mi...@neuling.org
---
I'm not 100% sure is this the right fix. Should CBE_CPUFREQ really
depend on CBE_CPUFREQ_PMI?
No I
cbe_cpufreq.c uses cbe_cpufreq_has_pmi which is provided by
cbe_cpufreq_pmi.c. Hence CBE_CPUFREQ depends on CBE_CPUFREQ_PMI.
=20
Signed-off-by: Michael Neuling mi...@neuling.org
---
I'm not 100% sure is this the right fix. Should CBE_CPUFREQ really
depend on CBE_CPUFREQ_PMI
cbe_cpufreq has a partial dependency on cbe_cpufreq_pmi, which cannot
be easily expressed in Kconfig. This fixes it by introducing an
extra Kconfig symbol CBE_CPUFREQ_PMI_ENABLE. To make the dependency
clearer, turn PPC_PMI into an automatic symbol.
Reported-by: Michael Neuling mi
Fix the VSX alignment handler for VSX registers 32. 32-63 are stored
in the VMX part of the thread_struct not the FPR part.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/kernel/align.c |7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
Index: linux-2.6-ozlabs
lfiwzx is a new floating point load instruction in 2.06 that needs an
alignment handler for Linux.
Turns out to be the worlds easiest handler to add.
Signed-off-by: Michael Neuling mi...@neuling.org
---
Benh: this is for 2.6.30, but would be nice to be back in 2.6.27/28/29
too.
arch/powerpc
When we introduced VSX, we changed the way FPRs are stored in the
thread_struct. Unfortunately we missed the load/store float double
alignment handler code when updating how we access FPRs in the
thread_struct.
Below fixes this and merges the little/big endian case.
Signed-off-by: Michael
Add macros for the GS (guest state) bit to the list of MSR bit definitions.
On PowerPC cores that support embedded hypervisor mode, GS is cleared if
the system is running in hypervisor state (and MSR[PR] is cleared), and set
if it's running in guest state. See the Power ISA 2.06 specification
Sachin,
2450cf51a1bdba7037e91b1bcc494b01c58aaf66 fixes this. Already upstream.
Mikey
In message 49acfd4e.8060...@in.ibm.com you wrote:
2.6.29-rc6-git6 ppc64_defconfig build fails with
arch/powerpc/kernel/built-in.o: In function `.of_pci_phb_probe':
of_platform.c:(.devinit.text+0xe0):
mpc52xx_gpt_create_attribs is missing a parameter name and shouldn't
return anything since it's void.
Signed-off-by: Michael Neuling mi...@neuling.org
---
This is against benh's testing tree
arch/powerpc/platforms/52xx/mpc52xx_gpt.c |2 +-
1 file changed, 1 insertion(+), 1 deletion
Hey Ben,
Here are some more for -next.
The following changes since commit 652e8f8d579d61745094e36b4ff085026a332e73:
Benjamin Herrenschmidt (1):
Merge commit 'jwb/next' into next
are available in the git repository at:
git://git.secretlab.ca/git/linux-2.6-mpc52xx next
Grant,
Can you grab this guy too?
http://patchwork.ozlabs.org/patch/24082/
Oops, forgot to email you about this one. I actually wrote another
patch the eliminates the sysfs attributes entirely which also
eliminates the problem. It will be in my next pull request to Ben
(any day
FYI pseries_defconfig and ppc64_defconfig boot fine with this on BML
systemsim.
Mikey manual kisskb Neuling
The following commits have been added to powerpc test:
Andrew Klossner (1):
powerpc/udbg: Fix lost byte during console handover; change LFCR
to CRLF
Benjamin Herrenschmidt
Hi all,
Those of us working on the POWER toolchain can envision a certain class
of customers who may benefit from intelligently disabling certain
register class enable bits on context switches, i.e. not disabling by
default.
Currently, per process, if the MSR enable bits for FPs, VRs or
.
[r...@p5-20-p6-e0 ~]# cat /proc/3422/sched |tail -3
switch_count : 559
fp_count : 317
vr_count :0
[r...@p5-20-p6-e0 ~]#
Signed-off-by: Michael Neuling mi...@neuling.org
Fix the calculation for offsetting into the FPRs when ptracing a 32 bit
app on 64 bit kernels.
Signed-off-by: Michael Neuling mi...@neuling.org
cc: sta...@kernel.org
---
benh: it'd be nice if this went back in to 27,28 29
Also, I vote we kill ptracing 64 bit apps from 32 apps as it's
completely
The ptrace compat wrapper mishandles access to the fpu registers. The
PTRACE_PEEKUSR and PTRACE_POKEUSR requests miscalculate the index into
the fpr array due to the broken FPINDEX macro. The
PPC_PTRACE_PEEKUSR_3264 request needs to use the same formula that the
native ptrace interface uses
So if you're looking fixing 32 bit apps ptracing 64 bit apps, does that
mean we can get a single 32 bit GDB that'll ptrace both 64 and 32 bit
apps?
Currently gdb only supports 32x64 debugging for the SPU.
Ok, thanks.
@@ -263,7 +263,8 @@ long compat_arch_ptrace(struct task_struct
In message m2myb32rk8@igel.home you wrote:
Michael Neuling mi...@neuling.org writes:
@@ -263,7 +263,9 @@ long compat_arch_ptrace(struct task_stru
ret = ptrace_put_reg(child, numReg, freg);
} else {
flush_fp_to_thread(child
randconfig build on powerpc failed with :
arch/powerpc/platforms/pseries/dtl.c: In function dtl_init:
arch/powerpc/platforms/pseries/dtl.c:238: error: implicit declaration of func
tion firmware_has_feature
arch/powerpc/platforms/pseries/dtl.c:238: error: FW_FEATURE_SPLPAR
- alignment exception turns FP off but leaves VSX on
VSX instruction - no exception since VSX on, hence we get the
wrong VSX register values for VSX registers 0-31
(overlapping the FPRs)
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch
needs to use the same formula that the
native ptrace interface uses when operating on the register number (as
opposed to the 4-byte offset). The PPC_PTRACE_POKEUSR_3264 request
didn't take TS_FPRWIDTH into account.
Signed-off-by: Andreas Schwab sch...@linux-m68k.org
Signed-off-by: Michael Neuling
into account.
Signed-off-by: Andreas Schwab sch...@linux-m68k.org
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/kernel/ptrace32.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/kernel/ptrace32.c
In message alpine.lrh.2.00.0904061430090.11...@vixen.sonytel.be you wrote:
On Fri, 3 Apr 2009, Kumar Gala wrote:
On Apr 3, 2009, at 7:08 AM, Geert Uytterhoeven wrote:
Finally (after ca. 1.5 years), he're an updated version of my patch to k=
eep
track of emulated instructions. In the light
In message alpine.lrh.2.00.0904070926001.17...@vixen.sonytel.be you wrote:
On Tue, 7 Apr 2009, Michael Neuling wrote:
In message alpine.lrh.2.00.0904061430090.11...@vixen.sonytel.be you wrote
:
On Fri, 3 Apr 2009, Kumar Gala wrote:
On Apr 3, 2009, at 7:08 AM, Geert Uytterhoeven wrote
From: Milton Miller milt...@bga.com
powerpc: Enable CPU feature sections for inline asm
This adds the ability to do CPU feature sections for inline asm.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/feature-fixups.h
These patches implement the new PowerPC 2.06 tlbie mnemonics
Signed-off-by: Michael Neuling mi...@neuling.org
---
It's friday afternoon I'm drinking beer, so odds are that these
patches are complete crap.
___
Linuxppc-dev mailing list
Linuxppc-dev
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
As they say, better out
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include
From: Milton Miller milt...@bga.com
powerpc: Enable MMU feature sections for inline asm
This adds the ability to do MMU feature sections for inline asm.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/feature-fixups.h
Kumar,
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
These patches implement the PowerPC ISA 2.06 tlbie mnemonics
Signed-off-by: Michael Neuling mi...@neuling.org
---
This version attempts to address issues raised by Kumar.
- Add missing mmu.h
- Follow the bouncing ball in ppc-opcode.h for #define PPC_TLBIE
From: Milton Miller milt...@bga.com
powerpc: Enable MMU feature sections for inline asm
This adds the ability to do MMU feature sections for inline asm.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/feature-fixups.h
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/mmu.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/mmu.h
@@ -58,6 +58,11 @@
*/
#define
These patches implement the PowerPC ISA 2.06 tlbie mnemonics
Signed-off-by: Michael Neuling mi...@neuling.org
---
Moves MMU_FTR_TLBIE_206 down one bit as the item before has now been
removed. Thanks to Kumar for noticing.
___
Linuxppc-dev mailing
From: Milton Miller milt...@bga.com
powerpc: Enable MMU feature sections for inline asm
This adds the ability to do MMU feature sections for inline asm.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/feature-fixups.h
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include
Move VSX load/stores into ppc-opcode.h
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h |9 +
arch/powerpc/include/asm/ppc_asm.h| 10 --
2 files changed, 9 insertions(+), 10 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc
Cleanup some code in ppc-opcode.h
___
Linuxppc-dev mailing list
Linuxppc-dev@ozlabs.org
https://ozlabs.org/mailman/listinfo/linuxppc-dev
Macros need to be more braces happy
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
These patches implement the PowerPC ISA 2.06 tlbie mnemonics
Signed-off-by: Michael Neuling mi...@neuling.org
---
Built ontop of ppc-opcode cleanup patches
Renamed somethings to be more logical based on comments from mpe.
___
Linuxppc-dev mailing list
From: Milton Miller milt...@bga.com
powerpc: Enable MMU feature sections for inline asm
This adds the ability to do MMU feature sections for inline asm.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/feature-fixups.h
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
===
--- linux-2.6-ozlabs.orig/arch/powerpc/include/asm/ppc-opcode.h
+++ linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
@@ -49,6 +49,7 @@
/* macros to
These patches implement the tlbie instruction for PowerPC ISA 2.06 and a few
cleanups for ppc-opcode.h
Signed-off-by: Michael Neuling mi...@neuling.org
---
Fixed coding style for moved VSX instructions.
Correctly alphabetized the newly added instructions
From: Milton Miller milt...@bga.com
powerpc: Enable MMU feature sections for inline asm
This adds the ability to do MMU feature sections for inline asm.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/feature-fixups.h
Make macros more braces happy.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h |8
1 file changed, 4 insertions(+), 4 deletions(-)
Index: linux-2.6-ozlabs/arch/powerpc/include/asm/ppc-opcode.h
Cleans up the VSX load/store instructions by moving them into
ppc-opcode.h.
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include/asm/ppc-opcode.h | 13 +
arch/powerpc/include/asm/ppc_asm.h| 10 --
2 files changed, 13 insertions(+), 10 deletions
From: Milton Miller milt...@bga.com
This adds the PowerPC 2.06 tlbie mnemonics and keeps backwards
compatibilty for CPUs before 2.06.
Only useful for bare metal systems.
Signed-off-by: Milton Miller milt...@bga.com
Signed-off-by: Michael Neuling mi...@neuling.org
---
arch/powerpc/include
In message [EMAIL PROTECTED] you wrote:
Hi Andrew,
The 2.6.25-rc3-mm1 kernel panics while bootup on power box. The machine boote
d up
without the panic on the third attempt, but badness call trace were seen whil
e running
tests
1) The kernel panic on first attempt
Unable to handle
In message [EMAIL PROTECTED] you wrote:
Hi,
I found the following bug at kernel boot up on my power machine
with 2.6.25-rc6 kernel.
USB Mass Storage support registered.
mice: PS/2 mouse device common for all mice
Unable to handle kernel paging request for data at address
Does it make more sense to call this ppc64/power5+rev3?
This is a change to support new counter setup for oprofile. It may be the
same if there is a revision 4 or 5 etc. So since the internal name was ++
I followed that convention.
I'm not too fussed, but if rev 4 comes out, the
Okay.
What I didn't want to do is spend a day sifting some other development
tree picking out what I think might be possibly sort of the right patches
for it.
I'd get it wrong because having not worked on it, I don't know what I am
even looking for.
And I don't want to run -rt or
in waiting
on pSeries.
Also adds some whitespace fixups.
Signed-off-by: Michael Neuling [EMAIL PROTECTED]
---
There are two possibly solutions I see in the long run:
=20
=A0- We could set the FW features earlier on pseries, though that is a bit
annoying because that means doing it before
On Wednesday 18 July 2007, Michael Neuling wrote:
Move firmware feature initialisation from pSeries_init_early to the
earlier pSeries_probe_hypertas so they are initialised before firmware
feature fixups are applied.
=20
Currently firmware feature sections are only used for iSeries which
From ehea_start_xmit in ehea_main.c we have:
if (unlikely(atomic_read(pr-swqe_avail) = 1)) {
spin_lock_irqsave(pr-netif_queue, flags);
if (unlikely(atomic_read(pr-swqe_avail) = 1)) {
pr-p_stats.queue_stopped++;
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is always
valid.
Signed-off-by: Michael Neuling [EMAIL PROTECTED]
---
Paulus
On Wed, 2007-08-01 at 16:02 +1000, Michael Neuling wrote:
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer
--- linux-2.6-ozlabs.orig/arch/powerpc/kernel/entry_64.S
+++ linux-2.6-ozlabs/arch/powerpc/kernel/entry_64.S
@@ -389,7 +389,9 @@ BEGIN_FTR_SECTION
ld r9,PACA_SLBSHADOWPTR(r13)
li r12,0
std r12,SLBSHADOW_STACKESID(r9) /* Clear ESID */
+ eieio
std
But even in the case of a checkpoint restart, the ordering will be
preserved as the NIA we get as part of the checkpoint will have all
previous instructions complete and none of the following instructions
started.
Instruction completion isn't enough to ensure storage ordering. The
On Thu, 2007-08-02 at 18:56 +1000, Michael Neuling wrote:
But even in the case of a checkpoint restart, the ordering will be
preserved as the NIA we get as part of the checkpoint will have
all
previous instructions complete and none of the following
instructions
started
We sometimes change the vmalloc segment in slb_flush_and_rebolt but we
never updated with slb shadow buffer. This fixes it. Thanks to paulus
for finding this.
Also added some write barriers to ensure the shadow buffer is always
valid.
Signed-off-by: Michael Neuling [EMAIL PROTECTED
In message [EMAIL PROTECTED] you wrote:
Hi, Michael,
Thanks for doing this, this is really useful.
Michael Neuling wrote:
This adds two items to the taststats struct to account for user and
system time based on scaling the CPU frequency and instruction issue
rates.
Adds
This fixes the following warning:
arch/powerpc/kernel/sysfs.c:388: warning: ignoring return value of
'sysfs_create_group', declared with attribute warn_unused_result
Signed-off-by: Michael Neuling [EMAIL PROTECTED]
---
arch/powerpc/kernel/sysfs.c |8 ++--
1 file changed, 6 insertions
In message [EMAIL PROTECTED] you wrote:
Michael Neuling wrote:
I'd also request for you to add a cpu_scaled_run_real_total for use
by delay accounting. cpu_scaled_run_real_total should be similar in
functionality to cpu_run_real_total.
Will do. Should I add cpu_scaled_run_real_total
In message [EMAIL PROTECTED] you wrote:
Andrew Morton wrote:
unsigned int rt_priority;
- cputime_t utime, stime;
+ cputime_t utime, stime, utimescaled, stimescaled;
Adding 8 or 16 bytes to the task_struct for all architectures for something
which only powerpc uses?
Is
On Wed, 12 Sep 2007, Michael Neuling wrote:
The tty: termios locking functions break with new termios type patch
(f629307c857c030d5a3dd777fee37c8bb395e171) breaks the powerpc compile.
Really?
It shouldn't. The use of kernel_termios_to_user_termios_1() is conditional
In message [EMAIL PROTECTED] you wrote:
On Wed, 12 Sep 2007 12:20:32 +0200 Heiko Carstens [EMAIL PROTECTED] wrote:
On Wed, Sep 12, 2007 at 12:04:39PM +1000, Michael Neuling wrote:
The tty: termios locking functions break with new termios type patch
Paulus,
Could you take this as well for 2.6.24?
Remove barriers from the SLB shadow buffer update
http://patchwork.ozlabs.org/linuxppc/patch?id=13116
Mikey
In message [EMAIL PROTECTED] you wrote:
David Gibson (2):
[POWERPC] Move bootwrapper's strchr() and strncmp() from .h to
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