On Wed, Aug 26, 2009 at 10:39:24PM +0800, wilbur.chan wrote:
In an assemblely code , I invalided all the TLB entries except for
the entry we are executed in.
After that , I setuped a 1:1 TLB entry mapping of 1GB .
What is it you're trying to do?
At last , I wrote value 30 into the
wilbur.chan wrote:
I am using a SMP E500 v2, and I want CPU0 to write some value to a
physical address, and wait for CPU1 to read from it.
Is this under Linux (it is a Linux mailing list...)? If so, there are
better ways of communicating that don't involve clobbering random memory
and
wilbur.chan wrote:
2009/8/27 Scott Wood scottw...@freescale.com:
Is this under Linux (it is a Linux mailing list...)? If so, there are
better ways of communicating that don't involve clobbering random memory and
overlapping userspace TLB mappings.
Yes, I'm doing this under linux in kernel
On Fri, Sep 04, 2009 at 12:31:25PM +0200, Roland Lezuo wrote:
The following patch is needed to correctly assign the IRQs for the
gianfar driver on the MPC8313ERDB-revc boards. ERR and TX are swapped
as well as the interrupt lines for the two devices.
And it will incorrectly assign them on
On Sun, Sep 06, 2009 at 01:06:41PM +0200, Sebastian Andrzej Siewior wrote:
irq_of_parse_and_map() creates a mapping between the hardware irq number
as specified in the device tree and the linux number (virq) which is
used within the linux api in request_irq() for instance.
On Wed, Sep 09, 2009 at 01:16:07PM +0200, Kenneth Johansson wrote:
On Tue, 2009-09-08 at 13:48 +0800, Li Tao-B22598 wrote:
Dear all,
I have a problem in MPC5121 sleep mode. As you know MPC5121 use e300c4
core. When I make the e300c4 core into sleep mode, it will return to
full power
On Wed, Sep 09, 2009 at 04:49:57PM +0200, Roel Kluin wrote:
Prevent NULL dereference if kmalloc() fails. Also clean up if
of_mdiobus_register() returns an error.
Signed-off-by: Roel Kluin roel.kl...@gmail.com
Acked-by: Scott Wood scottw...@freescale.com
-Scott
Li Tao wrote:
Hi Scott Wood,
Thanks for your response
在 2009-09-09三的 13:43 -0500，Scott Wood写道：
The decrementer stops ticking when the core goes to sleep. However, if a
decrementer was already pending (but masked with MSR[EE]) before you
enter sleep mode, it will cause a wakeup.
To avoid
On Thu, Sep 10, 2009 at 05:01:53PM +0200, Isaac Gomez Morales wrote:
Hello,
I'm trying to get a Linux distro such as Debian in the following system
System:
mpc8572ds HW
The 8572 does not have classic PowerPC floating point. The Debian
binaries use this, so they cannot run without
Anton Vorontsov wrote:
MPC8360 QE UCC ethernet controllers hang when changing link duplex
under a load (a bit of NFS activity is enough).
PHY: m...@e0102120:00 - Link is Up - 1000/Full
sh-3.00# ethtool -s eth0 speed 100 duplex half autoneg off
PHY: m...@e0102120:00 - Link is Down
PHY:
Sebastian Andrzej Siewior wrote:
So the split is a FSL thing.
What do you thing about making this clear? Adding into every .dts a
comment right on top or maybe in
Documentation/powerpc/dts-bindings/fsl/?
Add an fsl/mpic.txt binding that describes this and any other
pecularities above and
On Sun, Aug 30, 2009 at 11:37:18PM +0400, Anton Vorontsov wrote:
This patch adds suspend/resume support for MPC8540, MPC8569 and
MPC8641D-compatible CPUs.
MPC8540 and MPC8641D-compatible PMCs are trivial: we just write
the SLP bit into the PM control and status register.
MPC8569 is a bit
On Mon, Sep 14, 2009 at 07:33:49PM +0400, Anton Vorontsov wrote:
On Sun, Aug 30, 2009 at 11:36:25PM +0400, Anton Vorontsov wrote:
On Fri, Aug 28, 2009 at 12:38:51AM -0500, Kumar Gala wrote:
This patch adds suspend/resume support for MPC8540-compatible and
MPC8569 CPUs.
[...]
I'd
on
resume we must reload QE microcode and reset QE.
So far we don't support Deep Sleep mode as found in newer MPC85xx
CPUs (i.e. MPC8536). It can be relatively easy implemented though,
and for it we reserve 'mem' suspend type.
Signed-off-by: Anton Vorontsov avoront...@ru.mvista.com
Acked-by: Scott
Matthew L. Creech wrote:
I upgraded from 2.6.29 to 2.6.31, and the kernel no longer recognized
the partitions embedded within my DTS file. I had to revert this
change:
http://git.kernel.org/?p=linux/kernel/git/torvalds/linux-2.6.git;a=commit;h=4b08e149c0e02e97ec49c2a31d14a0d3a02f8074
in order
Anton Vorontsov wrote:
On Mon, Sep 21, 2009 at 05:36:25PM -0500, Scott Wood wrote:
Matthew L. Creech wrote:
I upgraded from 2.6.29 to 2.6.31, and the kernel no longer recognized
the partitions embedded within my DTS file. I had to revert this
change:
http://git.kernel.org/?p=linux/kernel/git
On Wed, Sep 23, 2009 at 10:52:44PM +0400, Anton Vorontsov wrote:
+#ifdef CONFIG_SUSPEND
+struct ehci_fsl {
+ struct ehci_hcd ehci;
+
+ /* Saved USB PHY settings, need to restore after deep sleep. */
+ u32 usb_ctrl;
+};
This doesn't seem like the right place to define this...
On Thu, Oct 01, 2009 at 08:35:59AM +1000, Benjamin Herrenschmidt wrote:
From what I can see, the TLB miss code will check _PAGE_PRESENT, and
when not set, it will -still- insert something into the TLB (unlike
all other CPU types that go straight to data access faults from there).
So we end
On Mon, Oct 05, 2009 at 02:16:33PM +0200, Joakim Tjernlund wrote:
Here are my latest code to fixup 8xx's TLB code.
This code needs some serious testing before it
can be commited.
The 8xx, fault: Add some debug code to do_page_fault() is
purely a debug check and will be removed/disabled when
On Sat, Oct 03, 2009 at 08:04:33AM +1000, Benjamin Herrenschmidt wrote:
On Fri, 2009-10-02 at 16:49 -0500, Scott Wood wrote:
Adding a tlbil_va to do_page_fault makes the problem go away for me (on
top of your merge branch) -- none of the other changes in this thread
do (assuming I didn't
On Mon, Oct 05, 2009 at 08:27:39PM +0200, Joakim Tjernlund wrote:
After resolving the conflict, without adding tlbil_va in do_page_fault(), I
get the same stuck behavior as before.
Expected, I havn't not tried to fix the missing tlbil_va(). That is
different problem that you and Ben needs
Benjamin Herrenschmidt wrote:
On Mon, 2009-10-05 at 14:28 -0500, Scott Wood wrote:
Yes, it hits ptep_set_access_flags() and adding _tlbil_va there helps (I
didn't put it in the filter function, because that doesn't take address as a
parameter). I'd misread your suggestion as referring
Joakim Tjernlund wrote:
Yes, every ld.so uses dcbX and icbi insn when relocatin code.
Maybe you see some version of the dcbX bug, but my fault.c should
fix them up. My bet would be the 32 byte cache line, it will miss
out every second line and so the results are unreliable.
I found the 32-byte
Joakim Tjernlund wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 05/10/2009 23:31:39:
Yes, every ld.so uses dcbX and icbi insn when relocatin code.
Even with -msecure-plt ?
hmm, maybe not. Can't remember now. But perhaps LAZY relocs still
need dcbX? Easiest is to check in
On Wed, Sep 16, 2009 at 03:02:33PM -, nanda wrote:
Hi,
Iam getting the below crash on new board tested on MPC832x using
linux-2.6.24, please let me what could be the problem on the same.
Does it infer any information on the exception?
Please try running the latest kernel.
# Oops:
On Fri, Oct 09, 2009 at 10:14:56AM -0400, Roberto Guerra wrote:
Hello,
My uboot can read my flash chip, finding the uImage and the initramfs,
and booting the kernel fine. However, I'd like the Linux kernel to
read my flash chip so that it can update files in it.
Have you described your flash
On Fri, Oct 09, 2009 at 01:59:58PM -0400, Roberto Guerra wrote:
No. I did not. My FDT was simplified from the stock MPC8272ADS:
= fdt list
/ {
model = pq2fads;
compatible = fsl,pq2fads;
#address-cells = 0x0001;
#size-cells = 0x0001;
cpus {
On Wed, Oct 14, 2009 at 09:41:33AM +0200, Richard Cochran wrote:
-Original Message-
From: linuxppc-dev-bounces On Behalf Of Scott Wood
Sent: Wednesday, September 09, 2009 8:22 PM
To: Roland Lezuo
Cc: linuxppc-dev@lists.ozlabs.org
Subject: Re: [PATCH] * mpc8313erdb.dts: Fixed eTSEC
On Sun, Oct 11, 2009 at 06:35:05PM +0200, Joakim Tjernlund wrote:
8xx sometimes need to load a invalid/non-present TLBs in
it DTLB asm handler.
These must be invalidated separaly as linux mm don't.
---
arch/powerpc/mm/fault.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
On Sun, Oct 11, 2009 at 06:35:06PM +0200, Joakim Tjernlund wrote:
+ mfspr r11, SRR1
+ /* clear all error bits as TLB Miss
+ * sets a few unconditionally
+ */
+ rlwinm r11, r11, 0, 0x
+ mtspr SRR1, r11
arch/powerpc/kernel/head_8xx.S:369: Error: unsupported
On Sun, Oct 11, 2009 at 06:35:09PM +0200, Joakim Tjernlund wrote:
DARFix: /* Return from dcbx instruction bug workaround, r10 holds value
of DAR */
[snip]
+ b DARfix /* Nope, go back to normal TLB processing */
arch/powerpc/kernel/head_8xx.S:577: undefined reference
On Sun, Oct 11, 2009 at 06:35:08PM +0200, Joakim Tjernlund wrote:
This is an assembler version to fixup DAR not being set
by dcbX, icbi instructions. There are two versions, one
uses selfmodifing code, the other uses a
jump table but is much bigger(default).
---
On Sun, Oct 11, 2009 at 06:35:04PM +0200, Joakim Tjernlund wrote:
This is the latest batch of mu 8xx MMU/TLB rework.
I think this is complete now and will relax with
other work the next few days. I hope I can get some
testing from Scott and Rex during this time.
I applied this stack plus
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of such problems with eLBC, but was unable
Joakim Tjernlund wrote:
BTW, you could add a test and printk in do_page_fault on address 0x00f0.
if that ever hits there is a problem with dcbX fixup.
It doesn't get any 0xf0 faults.
FWIW, I'm not seeing the segfault any more, but I still get the lockup.
-Scott
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 14/10/2009 21:23:02:
Joakim Tjernlund wrote:
BTW, you could add a test and printk in do_page_fault on address 0x00f0.
if that ever hits there is a problem with dcbX fixup.
It doesn't get any 0xf0 faults.
FWIW, I'm
Joakim Tjernlund wrote:
With that, I don't see the hard lockup, but things get stuck during
You needed both to loose the hard lockup? I would think
it should be enough to revert the various copy routines stuff?
No, but when I just reverted the patch and didn't change the TLB error handler,
Roberto Guerra wrote:
I've been learning how to modify the dts from
http://www.mjmwired.net/kernel/Documentation/powerpc/dts-bindings/mtd-physmap.txt#49
The original mpc8272ads.dts represents four 8-bit JEDEC Sharp flash
chips in 1 SIMM module:
[snip]local...@f0010100 {
On Thu, Oct 15, 2009 at 01:05:47PM +0200, Christian Borntraeger wrote:
The fact that struct console-write returns void indicates that the console
layer is not interested in errors. We have two policies we can implement:
1. drop console messages if case of congestion but keep the system going
On Thu, Oct 15, 2009 at 02:19:30PM +0200, Richard Cochran wrote:
-Original Message- From: Scott Wood [mailto:scottw...@freescale.com]
Because that would be three times the device trees to maintain, and a
source of user confusion.
I wonder which is more confusing for the user:
1
Christian Borntraeger wrote:
Right. Looking at more drivers it seems that both ways (waiting and dropping)
are used.
Hmmm, if we are ok with having both options, we should let the hvc backend
decide if it wants to drain or to discard.
I'd say the dropping approach is quite undesirable
Christian Borntraeger wrote:
About the backends, there are some that spin until the text is delivered (e.g.
virtio) , others can drop (e.g. iucv is a connection oriented protocol and it
will (and has to) drop if there is no connection).
Sure, dropping due to not having a connection makes
Scott Wood wrote:
Felix Radensky wrote:
Yes, NAND and NOR are on the same local bus controller.
Maybe powerpc folks can provide some insight here.
Is it possible that simultaneous access to NOR and NAND
on MPC8536 can result in NAND timeouts ?
I've heard other reports of such problems
Joakim Tjernlund wrote:
Now updated with Scott's remarks.
There is still(probably) a trivial conflict in pte-8xx.h
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
8xx: Update TLB asm so it behaves as linux mm expects.
8xx: Tag DAR with 0x00f0 to catch buggy instructions.
8xx:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously with NAND or NOR ?
AFAICT, the problem is NAND being accessed simultaneously with anything else
on
On Fri, Oct 16, 2009 at 03:46:45PM +1100, Benjamin Herrenschmidt wrote:
On Thu, 2009-10-15 at 13:57 -0500, Scott Wood wrote:
I'd say the dropping approach is quite undesirable (significant
potential for output loss unless the buffer is huge), unless there's
simply no way to safely spin
On Fri, Oct 16, 2009 at 08:31:19AM +0200, Richard Cochran wrote:
-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
Subject: Re: [PATCH] * mpc8313erdb.dts: Fixed eTSEC interrupt assignment.
On Thu, Oct 15, 2009 at 02:19:30PM +0200, Richard Cochran wrote:
2
Roberto Guerra wrote:
mtdparts=phys:1600K(ROM)ro,6M(root),512K(U-Boot)ro,512K(unused)
rootfstype=jffs2
= bootm 20 - 40
snip
physmap platform flash device: 0080 at ff80
physmap-flash.0: Found 1 x16 devices at 0x0 in 16-bit bank
Amd/Fujitsu Extended Query Table at 0x0040
On Sun, Oct 18, 2009 at 11:38:13AM +0200, Felix Radensky wrote:
Hi, Scott
Scott Wood wrote:
On Fri, Oct 16, 2009 at 07:01:43AM +0200, Felix Radensky wrote:
Thanks for confirmation. So the real problem is eLBC ?
What happens if I access other devices on eLBC (e.g. FPGA)
simultaneously
Felix Radensky wrote:
OK, no problem. I just wanted to get an idea of what should be done.
Should the NOR code poll some eLBC register to wait for completion of
NAND special operation ? Can you tell what register is relevant ?
I was thinking you'd just share a mutex with the NAND code.
-Scott
On Tue, Oct 20, 2009 at 12:01:19PM +0200, Richard Cochran wrote:
-Original Message-
From: Scott Wood [mailto:scottw...@freescale.com]
What problems have you been having with upstream kernels on mpc8313erdb,
other than this IRQ issue? It should work, though the BSP may have extra
Wolfgang Denk wrote:
Dear Vivek Mahajan,
In message 1256129459-10685-2-git-send-email-vivek.maha...@freescale.com you
wrote:
Adds documentation for Freescale's QorIQ based cache-sram as under:-
* How to enable it from a low level driver
* How to set its size
...
+The size of the above
Felix Radensky wrote:
Are you aware of Freescale plans to fix the problem in new silicon
revisions ?
I don't know anything yet -- still trying to get in touch with the
relevant hardware people.
Also, can you please tell what CPUs are affected by this, except 8536
and 8572.
I suppose
On Tue, Oct 27, 2009 at 10:16:17AM +0100, Joakim Tjernlund wrote:
Benjamin Herrenschmidt b...@kernel.crashing.org wrote on 27/10/2009
01:00:53:
On Mon, 2009-10-26 at 16:26 -0700, Dan Malek wrote:
Just be careful the get_user() doesn't regenerate the same
translation error you are
Jonathan Haws wrote:
Okay, I now have access to the flash memory, however when I write to it the
writes do not take. I have tried calling msync() on the mapping to no avail.
I have opened the fd with O_SYNC, but cannot get things to work right.
Here are the calls:
int fd =
Jonathan Haws wrote:
flash[0] = 0x1234;
msync(flash, NOR_FLASH_SIZE, MS_SYNC | MS_INVALIDATE);
printf(flash[0] = %#04x\n, flash[0]);
That prints flash[0] = 0x7f45. I have verified that I am reading
the correct values. I can display the flash contents in U-Boot and
On Tue, Oct 27, 2009 at 04:52:40PM -0600, Jonathan Haws wrote:
Will the device respond to 0x1234 being written at offset zero? You
generally have to poke these things pretty specifically in order to
get
them to go into command mode.
It should because that is the first data location
On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
Joakim Tjernlund/Transmode wrote on 17/10/2009 13:24:18:
Rex Feany rfe...@mrv.com wrote on 16/10/2009 22:25:41:
Thus spake Joakim Tjernlund (joakim.tjernl...@transmode.se):
Right, it is the pte table walk that is
On Fri, Oct 30, 2009 at 04:08:55PM +0100, Alessandro Rubini wrote:
asm(eieio; sync);
Hmm...
: : : memory
And, doesn't ; start a comment in assembly? (no, not on powerpc it seems)
';' is an instruction separator on all GNU as targets that I'm familiar
with (though a quick manual
On Fri, Oct 30, 2009 at 12:16:07PM -0500, Scott Wood wrote:
On Sat, Oct 17, 2009 at 02:01:38PM +0200, Joakim Tjernlund wrote:
+ mfspr r10, SPRN_SRR0
DO_8xx_CPU6(0x3780, r3)
mtspr SPRN_MD_EPN, r10
mfspr r11, SPRN_M_TWB /* Get level 1 table entry address */
- lwz
Joakim Tjernlund wrote:
and things seem to work. You could probably replace the rlwinm by
subtracting PAGE_OFFSET from swapper_pg_dir instead.
Just guessing here, do you mean:
lis r11, (swapper_pg_dir-PAGE_OFFSET)@h
ori r11, r11, (swapper_pg_dir-PAGE_OFFSET)@l
Kumar Gala wrote:
On Nov 5, 2009, at 10:57 AM, Scott Wood wrote:
Kumar Gala wrote:
On Sep 23, 2009, at 2:01 PM, Anton Vorontsov wrote:
Currently 83xx PMC driver clears deep_sleeping variable very early,
before devices are resumed. This makes fsl_deep_sleep() unusable in
drivers' resume
Kumar Gala wrote:
On Nov 5, 2009, at 1:48 PM, Scott Wood wrote:
As for patch 3, Ben objected to the sleep-nexus stuff on IRC.
Is sleep-nexus new? I thought we've had that for a bit.
It's been around in a few dts files, but as was noted, nothing uses this
stuff yet.
-Scott
Anton Vorontsov wrote:
On Thu, Nov 05, 2009 at 02:03:14PM -0600, Scott Wood wrote:
Kumar Gala wrote:
On Nov 5, 2009, at 1:48 PM, Scott Wood wrote:
As for patch 3, Ben objected to the sleep-nexus stuff on IRC.
Is sleep-nexus new? I thought we've had that for a bit.
It's been around in a few
On Wed, Nov 04, 2009 at 02:38:32PM +0100, Joakim Tjernlund wrote:
Here is the latest(last?) round of this series. I
hope I got everything right now.
Scott and Rex, please test and send ACK/NACK.
Jocke
Joakim Tjernlund (8):
8xx: invalidate non present TLBs
This works, and is an
On Mon, Nov 09, 2009 at 03:53:21PM -0600, Scott Wood wrote:
On Fri, Nov 06, 2009 at 10:29:44AM +0100, Joakim Tjernlund wrote:
With this, the kernel hangs after Mount-cache hash table entries: 512.
Somewhat surprising result. I didn't expect you would even hit this
condition now as we
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 00:00:04:
syscall_exit_cont, SRR0/SRR1 were being loaded immediately prior to a page
boundary, with the rfi after the page boundary. On crossing the boundary,
we take an ITLB miss (which goes from possibility
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 22:36:32:
Joakim Tjernlund wrote:
yes, maybe there is a way around that. Perhaps by using one of the
pinned entries for loaded modules, i.e avoid ITLB misses for kernel space?
Not sure what you mean... loaded
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 10/11/2009 23:02:10:
Joakim Tjernlund wrote:
It wasn't the CPU15 workaround that I was worried about taking down the
pinning -- but rather the CPU15 bug itself causing bad code to be
executed inside the pinned kernel mapping
Scott Wood wrote:
Joakim Tjernlund wrote:
Why does not pinning interact well with CPU15? If pinned, you never get
a TLB miss for kernel text so that should mitigate the CPU15 problem.
The nature of the workaround for CPU15 is that we can't keep it pinned
-- we have to take an ITLB miss
On Wed, Nov 11, 2009 at 01:06:10AM +0100, Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 11/11/2009 00:21:18:
Where would you put the dcbi? How do you regain control after that
cache line has been refilled, but before code flows back to the bad branch?
The dcbi would
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 11/11/2009 16:26:53:
On Wed, Nov 11, 2009 at 01:06:10AM +0100, Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 11/11/2009 00:21:18:
Where would you put the dcbi? How do you regain control after that
cache
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 12/11/2009 20:45:59:
One other concern with pinning on 8xx -- could it cause problems with
uncached DMA mappings? What happens if a speculative load pulls in a
cache line in an area that's supposed to be uncached?
hmm, why
Joakim Tjernlund wrote:
Anyhow, lets start simple and just do the pinned ITLB so the
new TLB code can be applied. Can you confirm this works for you?
It works (after changing #ifdef 1 to #if 1).
-Scott
___
Linuxppc-dev mailing list
Ron Madrid wrote:
I wrote a custom driver for an MPC8313 based board. Everything seems to
have been working for a long time, but now one of my IOCTL functions seems
to be having a problem. I'm getting a Bus error reported by my
application and also a kernel Oops. Here's what the kernel is
Ron Madrid wrote:
--- On Fri, 11/13/09, Scott Wood scottw...@freescale.com wrote:
From: Scott Wood scottw...@freescale.com
Subject: Re: Bus Error on MPC8313
To: Ron Madrid ron_mad...@sbcglobal.net
Cc: linuxppc-...@ozlabs.org
Date: Friday, November 13, 2009, 11:33 AM
Ron Madrid wrote:
I wrote
Ron Madrid wrote:
Are there any filesystems mounted on NAND? There are
some issues with transactions timing out if there's
contention with a long-running NAND operation.
Yes, a JFFS2. If that is the case, is there any sort of
workaround?
I've just posted some patches to linuxppc-dev and
We want error information even if the kernel hasn't been built for verbose
debugging.
Signed-off-by: Scott Wood scottw...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c | 13 -
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b
will fail.
Signed-off-by: Scott Wood scottw...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c
index ddd37d2..58db278 100644
--- a/drivers/mtd/nand
sequences, it also cleans up some
cruft in SEQIN that isn't needed since we cannot program partial pages
outside of OOB.
Signed-off-by: Scott Wood scottw...@freescale.com
Reported-by: Suchit Lepcha suchit.lep...@freescale.com
---
drivers/mtd/nand/fsl_elbc_nand.c | 66
On Mon, Nov 16, 2009 at 04:58:53PM +0300, Dmitry Eremin-Solenikov wrote:
+ fl...@0,1 {
+ #address-cells = 1;
+ #size-cells = 1;
+ compatible = cfi-flash;
+ reg = 0x0 0x80 0x80;
+
On Sun, Nov 15, 2009 at 06:09:27PM +0100, Joakim Tjernlund wrote:
[I used the wrong branch, this will hopefully not conflict]
This is hopfully the last iteration of the series.
Rex Scott, please test and signoff.
Changes since last version:
- Added mandatory pinning of iTLB
- Added DTLB
On Mon, Nov 16, 2009 at 03:00:09PM -0600, Scott Wood wrote:
On Sun, Nov 15, 2009 at 06:09:27PM +0100, Joakim Tjernlund wrote:
[I used the wrong branch, this will hopefully not conflict]
This is hopfully the last iteration of the series.
Rex Scott, please test and signoff.
Changes
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 16/11/2009 22:27:41:
On Mon, Nov 16, 2009 at 03:00:09PM -0600, Scott Wood wrote:
On Sun, Nov 15, 2009 at 06:09:27PM +0100, Joakim Tjernlund wrote:
[I used the wrong branch, this will hopefully not conflict]
This is hopfully
On Tue, Nov 17, 2009 at 10:50:53PM +, Thomas Gleixner wrote:
Index: linux-2.6/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
===
--- linux-2.6.orig/arch/powerpc/platforms/82xx/pq2ads-pci-pic.c
+++
Joakim Tjernlund wrote:
Scott Wood scottw...@freescale.com wrote on 17/11/2009 01:40:11:
No... I only meant that the ITLB pinning got rid of the boot hang.
When I mentioned the EFAULTs before you said, No surprise as the it
seems like the DAR decoding is broken. I thought you meant you'd
Joakim Tjernlund wrote:
Yeah, those are the ones that will trigger a dcbX TLB fault,
copy_tofrom_user would be my guess. Perhaps I missed something
in the conversions? That is, maybe some of these routines are plain wrong now
for
8xx due to some other bug?
A small test program in user space
On Wed, Nov 18, 2009 at 03:53:27PM -0800, Ming Lei wrote:
I used the vanilla linux 2.6.30 and compiled with mpc85xx_defconfig(enable
CONFIG_BOOK_WDT) and then ran on 8548CDS and soon after I saw the prompt I
hit this watchdog.
bash-2.04# PowerPC Book-E Watchdog Exception
NIP: c000b740
On Thu, Nov 19, 2009 at 08:29:19AM -0600, Kumar Gala wrote:
+config FSL_85XX_CACHE_SRAM_BASE
+ hex
+ depends on FSL_85XX_CACHE_SRAM
+ default 0xfff0
+
I really don't like setting the physical address this way, can we
not do this via the device tree?
At a high level I think
On Thu, Nov 19, 2009 at 11:45:32PM -0700, Mahajan Vivek-B08308 wrote:
I really don't like setting the physical address this way,
can we not do this via the device tree?
Cache-sram does not have any device tree entry since it is not a
hardware as such. Putting it under chosen can be
Benjamin Herrenschmidt wrote:
On Fri, 2009-11-27 at 11:57 +0100, Joakim Tjernlund wrote:
Scott and Rex, I think we need you s-o-b to make it into the kernel proper.
Marcelo and Vitaly, I noticed you guys are listed as 8xx maintainers.
Have you seen this? What do you think?
I think Marcelo
Mahajan Vivek-B08308 wrote:
From: Wood Scott-B07421
Sent: Friday, November 20, 2009 11:09 PM
Cache-sram does not have any device tree entry since it is not a
hardware as such. Putting it under chosen can be another option.
I think, Scott (cc'ed) was of the opinion that since 32b
base address
On Mon, Dec 07, 2009 at 11:53:22AM +0800, 林志平 wrote:
Does dtc1.2.0 can compile dts files under linux2.6.23?
Probably not -- 2.6.23 is very old, and I think newer dtcs only support the
newer dts syntax.
Another question is that I found linux2.6.31 does not support
board mpc8544ds,
It should.
On Sun, Dec 06, 2009 at 10:41:25PM -0800, ajij...@gmail.com wrote:
Hi
We have an MPC8343EA based custom board.
I am not able to get Linux up and running in this. No serial output to debug
further.
U-boot shows correct 'bdinfo' 'clocks' output.
inux hangs at machine_probe.
Check
Mark Ware wrote:
Mark Ware wrote:
CPM2 Port C interrupts can be either falling edge, or either edge.
Other external interrupts are either falling edge or active low.
[snip]
+ /* Port C interrupts are either IRQ_TYPE_EDGE_FALLING or
+* IRQ_TYPE_EDGE_BOTH (default). All others
林志平 wrote:
Another question is that I found linux2.6.31 does not support
board mpc8544ds,
It should. What problems do you see?
= bootm 0x100 0x180 0x80
## Booting kernel from Legacy Image at 0100 ...
Image Name: Linux-2.6.31
Image Type: PowerPC Linux
Anton Vorontsov wrote:
+ if ((flow_type != IRQ_TYPE_EDGE_BOTH)
+ (flow_type != IRQ_TYPE_EDGE_FALLING)) {
I'd place one more tab here.
Or better, align one flow_type with the other.
-Scott
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林志平 wrote:
Yes mcp85xx_defconfig does not work, I can see mpc8540ads in the
menuconfig, but no mpc8544ds.
mpc8544ds is supported by CONFIG_MPC85xx_DS.
CONFIG_MPC85XX_DS does not exist. Only mpc85xx_defconfig in
arch/powerpc/configs
I'm looking right at it, in
to add an Ack to this version?
Acked-by: Anton Vorontsov avoront...@ru.mvista.com
Acked-by: Scott Wood scottw...@freescale.com
-Scott
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Anton Vorontsov wrote:
Hi all,
This is quite late resend, sorry.
Only the third patch has changed, i.e. I got rid of sleep-nexus
stuff per Scott and Benjamin suggestions.
Acked-by: Scott Wood scottw...@freescale.com
-Scott
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