On Mon, Nov 17, 2014 at 12:23 PM, Michael Ellerman m...@ellerman.id.au wrote:
On Fri, 2014-11-14 at 14:42 +0530, Vineeth Vijayan wrote:
Now there is no way to disable TEXT randomization on a PPC32/PPC64
machine. Text randomization happens even in the case of echo 0
/proc/sys/kernel
On Mon, Nov 17, 2014 at 12:23 PM, Michael Ellerman m...@ellerman.id.au
wrote:
On Fri, 2014-11-14 at 14:42 +0530, Vineeth Vijayan wrote:
Now there is no way to disable TEXT randomization on a PPC32/PPC64
machine. Text randomization happens even in the case of echo 0
/proc/sys/kernel
On Fri, Nov 14, 2014 at 11:50 AM, Michael Ellerman m...@ellerman.id.au wrote:
On Fri, 2014-11-14 at 11:03 +0530, Vineeth Vijayan wrote:
ping !
any update on this ? As i understand, only powerpc and s390 uses the
randomize_et_dyn call; for all other architecture this is an obsolete
function
is redundant and is removed.
Signed-off-by: Vineeth Vijayan vvija...@mvista.com
---
arch/powerpc/Kconfig |1 +
arch/powerpc/include/asm/elf.h |3 +--
arch/powerpc/kernel/process.c |9 -
3 files changed, 2 insertions(+), 11 deletions(-)
diff --git a/arch/powerpc
ping !
any update on this ? As i understand, only powerpc and s390 uses the
randomize_et_dyn call; for all other architecture this is an obsolete
function call.
this call for another patch where randomize_et_dyn is removed.
On Wed, Oct 15, 2014 at 12:08 PM, Vineeth Vijayan vvija...@mvista.com
ping !
any update on this ? As i understand, only powerpc and s390 uses the
randomize_et_dyn call; for all other architecture this is an obsolete
function call.
this call for another patch where randomize_et_dyn is removed.
Vineeth
On Wed, Oct 15, 2014 at 12:08 PM, Vineeth Vijayan vvija
On Wed, Oct 15, 2014 at 7:38 AM, Michael Ellerman m...@ellerman.id.au wrote:
On Fri, 2014-10-10 at 05:45:26 UTC, Vineeth Vijayan wrote:
Right now there is no way to disable TEXT randomization on a PPC32
machine. text randomization happens even in the case of echo 0
/proc/sys/kernel
Right now there is no way to disable TEXT randomization on a PPC32
machine. text randomization happens even in the case of echo 0
/proc/sys/kernel/randomize_va_space
This happens due to the incorrect definition of ELF_ET_DYN_BASE at
arch/powerpc/include/asm/elf.h
Signed-off-by: Vineeth Vijayan
that RST_CTL
is at offset 0x40 and the RST is the 7th bit of same.
then how's has-rstcr/reboot works ?
Vineeth
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Again, warm-reboot WORKS. there's no issue with that.
My ONLY concern is i am not able to understand how it works; the ref.manual
information and the code doesnt match.
Vineeth
On Fri, Aug 8, 2014 at 12:35 PM, Priyanka Jain priyanka.j...@freescale.com
wrote:
Thanks Vineeth for pointing
Hi,
I've added a VDSO patch on my 2.6.32 kernel. When i enabled PREMPT_RT i am
getting the below oops messages.
What is the reason for this ? When googled, it was mentioned in many places
that it is caused by the get_cpu()/put_cpu() preempt disabled region.
Can someone help me to understand this
Hi,
I've added a VDSO patch on my 2.6.32 kernel. When i enabled PREMPT_RT i am
getting the below oops messages.
What is the reason for this ? When googled, it was mentioned in many places
that it is caused by the get_cpu()/put_cpu() preempt disabled region.
Can someone help me to understand this
When i connect my 500GB seagate HD on a P5020DS, its not getting mounted.
This is the dmesg log;
am i supposed to change some configuration ?
/ # dmesg
usb 1-1: new high speed USB device using fsl-ehci and address 5
usb 1-1: configuration #1 chosen from 1 choice
scsi2 : SCSI emulation for USB
or modified middle ware driver for rionet/ or any
code which uses the low level driver apis with MMIO DMA??
Thanks
Vineeth
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You can disable the cache with the help of TLBs. See where it is creating
TLBs for the memory regions for that processor.
On Wed, Mar 14, 2012 at 8:07 AM, hellohello hellohello...@163.com wrote:
How to make a memory region to be cache disabled in linux?
I'm porting mpc83XX from vxworks to
...@freescale.comwrote:
On 12/12/2011 11:33 PM, Vineeth wrote:
Do we have a linux port available for freescale P5010 processor (with
single E5500 core) ?
/(found arch/powerpc/platforms/pseries ; and a some details on
kernel/cputable.c /)
p5010 is basically a p5020 with one core and memory complex
Do we have a linux port available for freescale P5010 processor (with
single E5500 core) ?
*(found arch/powerpc/platforms/pseries ; and a some details on
kernel/cputable.c *)
Is there any reference board which uses this processor ? any reference in
DTS file also will be helpful.
Thanks
Vineeth
Do we have AFDX support in Linux/Rt-Linux ?
tried grep.couldnt find any.
Thanks
Vineeth
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interrupts IRQ_NO,POLARITY
i2c@3000 {
#address-cells = 1;
#size-cells = 0;
cell-index = 0;
compatible = fsl-i2c;
reg = 0x3000 0x100;
interrupts = 43 2;
interrupt-parent = mpic;
dfsrr;
};
connected with
our processor. Our plan is to use the timer of MPC107 and register our
timer_interrupt function with this timer interrupt. I think that's the only
workaround left now.
Thanks
Vineeth
On Thu, Sep 22, 2011 at 11:52 AM, MohanReddy koppula mohanredd...@gmail.com
wrote:
I had the same issue
embedded60x port of linux3.0.3; we've written the dts file with
proper clock-frequency/timebase-frequency values.
Do you think we might've missed some configuration in the timer perspective
?
On Fri, Sep 16, 2011 at 10:33 PM, Scott Wood scottw...@freescale.comwrote:
On 09/16/2011 06:43 AM, Vineeth
or the
timer ??
Thanks
Vineeth
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gives better idea about the ranges property ?
Thanks
Vineeth
obc7410.dts
Description: Binary data
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PM, tiejun.chen tiejun.c...@windriver.comwrote:
Vineeth wrote:
Hi,
We are trying to port linux 2.6.38 on MPC7410 based board (This is a
preparatory design by our customer)
System architecture is as follows,
MPC7410 = MPC107 = PCI_to_LOCAL(plx9052) = UART
MPCXXX should
Hi,
We have a MPC7410 based board and we are trying to port Linux on the same.
the Board Architecture/UART connection is as follows
*MPC7410 --- MPC107(PCI Bridge) --- PLX9052(PCI-Local Bus Bridge) ---
UART*
The address mapping is as follows
PLX9052 @ 0xDB00_
UART @
,PPC44x_TLB_PAGEID /* Load the pageid fields */
tlbwe r4,r0,PPC44x_TLB_XLAT /* Load the translation fields */
tlbwe r5,r0,PPC44x_TLB_ATTRIB /* Load the attrib/access fields */
-
Is this can be considered as a good patch ?
Thanks
Vineeth _
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Vineeth _
On Mon, Oct 12, 2009 at 7:04 PM, Vineeth _ blackli...@gmail.com wrote:
Hi Wolfgang,
The link says about the initialization of the SDRAM; Does it
applicable in our case, where we have SRAM on our board. Does the
initialization means just clearing the memory in case of SRAM ? We
tried
a TLB of 16MB for the SRAM which is not cachable.
-Vineeth
On Fri, Oct 9, 2009 at 5:03 PM, Wolfgang Denk w...@denx.de wrote:
Dear Vineeth _,
In message a9b543570910090320t1444f8f1qf4c8ab7dbbef6...@mail.gmail.com you
wrote:
We ported the uboot Memory test and tested the 15MB ram
.
Ex, use mtest in uboot to check memory. For ICE, it should be an
detailed memory test function like hardware diagnostic.
2009/9/24 Benjamin Herrenschmidt b...@kernel.crashing.org:
On Wed, 2009-09-23 at 20:19 +0530, Vineeth _ wrote:
I am trying to port linux on IBM powerpc-440x5. I have
clue or details on this.
Thanks Regards,
Vineeth
LINUX BOOT LOG
Initialized the System
Initialized the UART
Copying Linux Image to RAM !!!
Copying Image Done
-KERNEL ENTRY-
-
zImage
to be hanged here !
Thanks in advance,
Vineeth
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