Hi Tim,
in message 3A75F8A8.64ADB0C at vacuumgenesis.com you wrote:
Has anyone had any luck with the 860T FEC driver in the 2.4 kernel (I am
using the 01/13/01 snapshot from FSMLabs). It is certainly not working
out-of-the-box as it were. For example, it tries calling mii_queue with
No, it
Philip Decker wrote:
If there are none, and I or my employer developed a flash memory card that
plugged into the Walnut's 200-pin proprietary expansion connector, J36, how
many of you would want any? If interested, email me:
While I have no interest in a memory card that fits that connector
At 10:05 PM 1/29/01 +0100, Wolfgang Grandegger wrote:
Hello,
I'm currently debugging a task stack initialization problem in RTAI
on MPC8xx. The task is switched by calling rt_startup() via blr
(or rfi in RTLinux). The objdump of rtai_sched.o shows the following
function prolog:
rtai_sched.o:
In message 4.3.2.20010130074919.00bb0a80 at falcon.si.com
Jerry Van Baren wrote:
One of the differences between the ABI and EABI is that the EABI
requires 8 byte alignment of the stack and the ABI requires 16 byte
alignment (EABI, p.28).
Yes, ok. But what is implemented by GCC and glibc? The
Wolfgang Denk wrote:
In message 4.3.2.20010130074919.00bb0a80 at falcon.si.com
Jerry Van Baren wrote:
One of the differences between the ABI and EABI is that the EABI
requires 8 byte alignment of the stack and the ABI requires 16 byte
alignment (EABI, p.28).
Yes, ok. But what is
At 03:46 PM 1/30/01 +0100, Wolfgang Denk wrote:
In message 4.3.2.20010130074919.00bb0a80 at falcon.si.com
Jerry Van Baren wrote:
One of the differences between the ABI and EABI is that the EABI
requires 8 byte alignment of the stack and the ABI requires 16 byte
alignment (EABI, p.28).
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Hi Ralph,
in message 3A76F163.406CBFDB at raleigh.ibm.com you wrote:
I am writing a character device driver. I want this device driver to
return an error if the user request less than say 1024 byte of data.
What errno should I use? Is it legal to return an error if not enouth
EINVAL
We are working on a Linux port to 860 cards that have a PLX 9060 PLX 9054
PCI Bus master chips.
My Co-worker Steve has gotten some advice example code for a PLX9080
implementation from Adrian Cox, (Thanks loads!).
I have some general basic questions here that I am posting to the list in
Jan Rovins wrote:
Our boards memory map is as follows
PCI chip interface registers: 0xC100, - 0xC101,
PCI I/O Space: 0x6000, - 0x8000,
PCI Mem Space: 0x4000, - 0x5FFF,
OK.
I am looking for some clear explanations of the following io.h
Is anyone out there using the Abatron BDI2000 to set hardware breakpoints on
data access (on 405GP)? I'm probably just doing something dumb, but I don't
see it. Any ideas?
Thanks,
Brian
BDIbd w 0xc019c390
# syntax is BDx [R|W]
BDIbdx w 0xc019c390
# syntax error in command
BDIbd w c019c390
#
Dan I worked on it about 40 hours this past weekend, still no go.
Dan The problem for me still continues to be interrupt routing on
Dan this board. The 8240 or 107 have the EPIC, which is like
Dan OpenPIC but not really. This is further complicated by the
Dan 8259 cascade,
I reflashed my BDI2000 (loader=1.03, firmware=1.01, logic=1.01).
Unfortunately I get the same results. I will contact Abatron. Perhaps
there is a bug in this version of the command parser.
Thanks,
Brian
-Original Message-
From: Wolfgang Denk [mailto:[EMAIL PROTECTED]
Sent: Tuesday,
Wolfgang Denk wrote:
BTW: I've sent all these patches to Dan and Cort and Ben, so I hope
at least part of it will make it in the official sources.
Thanks! I finally got it up and running, and have ethernet!!!. I had to
make some changes WRT some of the MII commands, which I don't think
Hi,
Can anyone please tell me what, if any, distribution of 2.4.x linux is 'best'
as a
starting point for porting to our custom 8240 board? I realize 2.4.x,
especially for
PPC, is being updated daily. Any advice will be greatly appreciated.
I'm also somewhat aware of RTlinux and others, but
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