[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a regression in ContinuationIndenter (#88414) (PR #89412)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/89412 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] 6dbaa89 - [clang-format] Fix a regression in ContinuationIndenter (#88414)

Author: Owen Pan Date: 2024-04-26T16:58:03-07:00 New Revision: 6dbaa89433f785799797d14e4c36805998fc6bad URL: https://github.com/llvm/llvm-project/commit/6dbaa89433f785799797d14e4c36805998fc6bad DIFF: https://github.com/llvm/llvm-project/commit/6dbaa89433f785799797d14e4c36805998fc6bad.diff

[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a regression in ContinuationIndenter (#88414) (PR #89412)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/89412 >From 6dbaa89433f785799797d14e4c36805998fc6bad Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Fri, 12 Apr 2024 10:12:24 -0700 Subject: [PATCH] [clang-format] Fix a regression in ContinuationIndenter (#88414)

[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a regression in annotating TrailingReturnArrow (#86624) (PR #89415)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/89415 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] 51ff7f3 - [clang-format] Fix a regression in annotating TrailingReturnArrow (#86624)

Author: Owen Pan Date: 2024-04-26T16:56:54-07:00 New Revision: 51ff7f38b633f72ef2d4a6bb4a5660a39c1cf611 URL: https://github.com/llvm/llvm-project/commit/51ff7f38b633f72ef2d4a6bb4a5660a39c1cf611 DIFF: https://github.com/llvm/llvm-project/commit/51ff7f38b633f72ef2d4a6bb4a5660a39c1cf611.diff

[llvm-branch-commits] [clang] release/18.x: [clang-format] Fix a regression in annotating TrailingReturnArrow (#86624) (PR #89415)

https://github.com/llvmbot updated https://github.com/llvm/llvm-project/pull/89415 >From 51ff7f38b633f72ef2d4a6bb4a5660a39c1cf611 Mon Sep 17 00:00:00 2001 From: Owen Pan Date: Tue, 2 Apr 2024 14:48:14 -0700 Subject: [PATCH] [clang-format] Fix a regression in annotating TrailingReturnArrow

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

https://github.com/tstellar closed https://github.com/llvm/llvm-project/pull/90204 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] b544217 - [AMDGPU] Fix setting nontemporal in memory legalizer (#83815)

Author: Mirko Brkušanin Date: 2024-04-26T13:35:58+01:00 New Revision: b544217fb31ffafb9b072de53a28c71acc169cf8 URL: https://github.com/llvm/llvm-project/commit/b544217fb31ffafb9b072de53a28c71acc169cf8 DIFF:

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/preames approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (PR #90267)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Paul Kirth (ilovepi) Changes With the tag merging in place, we can safely change the default for +seq-cst-trailing-fence to the default, according to the recommendation in

[llvm-branch-commits] Reapply "[llvm][RISCV] Enable trailing fences for seq-cst stores by default (#87376)" (PR #90267)

https://github.com/ilovepi created https://github.com/llvm/llvm-project/pull/90267 With the tag merging in place, we can safely change the default for +seq-cst-trailing-fence to the default, according to the recommendation in

[llvm-branch-commits] [llvm] [MTE] add stack frame history buffer (PR #86356)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/86356 >From a64c5d63a4df7f59845291ca0d634466713b1ff8 Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Fri, 29 Mar 2024 16:53:52 -0700 Subject: [PATCH] update Created using spr 1.3.4 ---

[llvm-branch-commits] [llvm] [MTE] add stack frame history buffer (PR #86356)

https://github.com/fmayer updated https://github.com/llvm/llvm-project/pull/86356 >From a64c5d63a4df7f59845291ca0d634466713b1ff8 Mon Sep 17 00:00:00 2001 From: Florian Mayer Date: Fri, 29 Mar 2024 16:53:52 -0700 Subject: [PATCH] update Created using spr 1.3.4 ---

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/topperc approved this pull request. LGTM https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/6] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -47,6 +47,12 @@ include "RISCVSchedSiFiveP600.td" include "RISCVSchedSyntacoreSCR1.td" include "RISCVSchedXiangShanNanHu.td" +//===--===// +// RISC-V profiles supported.

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/4vtomat approved this pull request. LGTM~ https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

@@ -51,6 +51,14 @@ def Feature64Bit def FeatureDummy : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">; +class RISCVProfile features> +: SubtargetFeature; + +def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; +def RVI20U64 :

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/5] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

https://github.com/arsenm approved this pull request. https://github.com/llvm/llvm-project/pull/90204 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] cb37105 - Revert "[TableGen] Ignore inaccessible memory when checking pattern flags (#9…"

Author: Jay Foad Date: 2024-04-26T14:47:16+01:00 New Revision: cb37105c23926b07488c2f0a9a603634d9be4936 URL: https://github.com/llvm/llvm-project/commit/cb37105c23926b07488c2f0a9a603634d9be4936 DIFF: https://github.com/llvm/llvm-project/commit/cb37105c23926b07488c2f0a9a603634d9be4936.diff

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/asb commented: Probably best reviewed by someone who has more familiarity with RISCVTargetDefEmitter, but I took a look anyway. I think this direction is OK, though I can't help but feel moving from the ISA naming strings to the more verbose listing of features is a bit of

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

@@ -51,6 +51,14 @@ def Feature64Bit def FeatureDummy : SubtargetFeature<"dummy", "Dummy", "true", "Dummy">; +class RISCVProfile features> +: SubtargetFeature; + +def RVI20U32 : RISCVProfile<"rvi20u32", [Feature32Bit, FeatureStdExtI]>; +def RVI20U64 :

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/asb edited https://github.com/llvm/llvm-project/pull/90187 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -0,0 +1,204 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/4vtomat deleted https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/4vtomat edited https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -0,0 +1,204 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

llvmbot wrote: @llvm/pr-subscribers-backend-amdgpu Author: Jay Foad (jayfoad) Changes Iterator MI can advance in insertWait() but we need original instruction to set temporal hint. Just move it before handling volatile. --- Patch is 32.67 KiB, truncated to 20.00 KiB below, full version:

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

https://github.com/jayfoad milestoned https://github.com/llvm/llvm-project/pull/90204 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] [AMDGPU] Fix setting nontemporal in memory legalizer (#83815) (PR #90204)

https://github.com/jayfoad created https://github.com/llvm/llvm-project/pull/90204 Iterator MI can advance in insertWait() but we need original instruction to set temporal hint. Just move it before handling volatile. >From b544217fb31ffafb9b072de53a28c71acc169cf8 Mon Sep 17 00:00:00 2001 From:

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -0,0 +1,204 @@ +//===-- RISCVProfiles.td - RISC-V Profiles -*- tablegen -*-===// +// +// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. +// See https://llvm.org/LICENSE.txt for license information. +// SPDX-License-Identifier:

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { VentanaVeyron, }; // clang-format on + + enum RISCVProfileEnum : uint8_t { +Unspecified, +RVI20U32, +RVI20U64, +RVA20U64, +RVA20S64, +RVA22U64, +RVA22S64, +

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -65,10 +65,27 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { VentanaVeyron, }; // clang-format on + + enum RISCVProfileEnum : uint8_t { kito-cheng wrote: This can remove https://github.com/llvm/llvm-project/pull/84877

[llvm-branch-commits] [flang] [flang][OpenMP] Don't pass clauses to op-generating functions anymore (PR #90108)

https://github.com/tblah approved this pull request. LG. Thanks for the cleanup https://github.com/llvm/llvm-project/pull/90108 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [flang] [flang][OpenMP] Pass symTable to all genXYZ functions, NFC (PR #90090)

https://github.com/tblah approved this pull request. LGTM, thanks https://github.com/llvm/llvm-project/pull/90090 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/4] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [flang] [flang][OpenMP] Implement getIterationVariableSymbol helper function,… (PR #90087)

https://github.com/tblah approved this pull request. LG https://github.com/llvm/llvm-project/pull/90087 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

@@ -138,6 +155,8 @@ class RISCVSubtarget : public RISCVGenSubtargetInfo { /// initializeProperties(). RISCVProcFamilyEnum getProcFamily() const { return RISCVProcFamily; } + RISCVProfileEnum getRISCVProfile() const { return RISCVProfile; } + kito-cheng

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

llvmbot wrote: @llvm/pr-subscribers-backend-risc-v Author: Pengcheng Wang (wangpc-pp) Changes So we can only mantain one place. --- Full diff: https://github.com/llvm/llvm-project/pull/90187.diff 3 Files Affected: - (modified) llvm/lib/TargetParser/RISCVISAInfo.cpp (+2-35) -

[llvm-branch-commits] [RISCV] Generate profiles from RISCVProfiles.td (PR #90187)

https://github.com/wangpc-pp created https://github.com/llvm/llvm-project/pull/90187 So we can only mantain one place. ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [LoongArch][Codegen] Add support for TLSDESC (PR #90159)

xry111 wrote: > > > [wangleiat](https://github.com/wangleiat) wants to merge 1 commit into > > > [users/wangleiat/spr/main.loongarchcodegen-add-support-for-tlsdesc-1](https://github.com/llvm/llvm-project/tree/users/wangleiat/spr/main.loongarchcodegen-add-support-for-tlsdesc-1) > > > from > >

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp updated https://github.com/llvm/llvm-project/pull/84877 >From ec68548a470d6d9032a900a725e95b92691657b2 Mon Sep 17 00:00:00 2001 From: Wang Pengcheng Date: Tue, 12 Mar 2024 14:28:09 +0800 Subject: [PATCH 1/3] =?UTF-8?q?[=F0=9D=98=80=F0=9D=97=BD=F0=9D=97=BF]=20in?=

[llvm-branch-commits] [clang] [llvm] [RISCV] Add subtarget features for profiles (PR #84877)

https://github.com/wangpc-pp edited https://github.com/llvm/llvm-project/pull/84877 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [IRCE] Skip icmp ptr in `InductiveRangeCheck::parseRangeCheckICmp` (#89967) (PR #90182)

llvmbot wrote: @llvm/pr-subscribers-llvm-transforms Author: None (llvmbot) Changes Backport 22da5a6e34ed6146752b24d9156a678b50fddaef Requested by: @nikic --- Full diff: https://github.com/llvm/llvm-project/pull/90182.diff 2 Files Affected: - (modified)

[llvm-branch-commits] [llvm] release/18.x: [IRCE] Skip icmp ptr in `InductiveRangeCheck::parseRangeCheckICmp` (#89967) (PR #90182)

llvmbot wrote: @nikic What do you think about merging this PR to the release branch? https://github.com/llvm/llvm-project/pull/90182 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org

[llvm-branch-commits] [llvm] release/18.x: [IRCE] Skip icmp ptr in `InductiveRangeCheck::parseRangeCheckICmp` (#89967) (PR #90182)

https://github.com/llvmbot milestoned https://github.com/llvm/llvm-project/pull/90182 ___ llvm-branch-commits mailing list llvm-branch-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/llvm-branch-commits

[llvm-branch-commits] [llvm] release/18.x: [IRCE] Skip icmp ptr in `InductiveRangeCheck::parseRangeCheckICmp` (#89967) (PR #90182)

https://github.com/llvmbot created https://github.com/llvm/llvm-project/pull/90182 Backport 22da5a6e34ed6146752b24d9156a678b50fddaef Requested by: @nikic >From 6fdc67c416017f66a4ed51f6b6c010d5151176dc Mon Sep 17 00:00:00 2001 From: Yingwei Zheng Date: Fri, 26 Apr 2024 16:25:33 +0800 Subject:

[llvm-branch-commits] [LoongArch][Codegen] Add support for TLSDESC (PR #90159)

wangleiat wrote: > > [wangleiat](https://github.com/wangleiat) wants to merge 1 commit into > > [users/wangleiat/spr/main.loongarchcodegen-add-support-for-tlsdesc-1](https://github.com/llvm/llvm-project/tree/users/wangleiat/spr/main.loongarchcodegen-add-support-for-tlsdesc-1) > > from > >

[llvm-branch-commits] [LoongArch][Codegen] Add support for TLSDESC (PR #90159)

xry111 wrote: > [wangleiat](https://github.com/wangleiat) wants to merge 1 commit into > [users/wangleiat/spr/main.loongarchcodegen-add-support-for-tlsdesc-1](https://github.com/llvm/llvm-project/tree/users/wangleiat/spr/main.loongarchcodegen-add-support-for-tlsdesc-1) > from >