Am 12.02.2013 21:49, schrieb Michel Dänzer:
On Die, 2013-02-12 at 18:13 +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Mark all the operands that can also have an immediate.
Signed-off-by: Christian König christian.koe...@amd.com
---
Am 13.02.2013 01:20, schrieb Tom Stellard:
On Tue, Feb 12, 2013 at 06:13:19PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
SIInstrFormats.td should contain the instruction encoding definitions
and everything else should go in SIInstrInfo.td. I got this
On Mit, 2013-02-13 at 10:16 +0100, Christian König wrote:
Am 12.02.2013 21:49, schrieb Michel Dänzer:
On Die, 2013-02-12 at 18:13 +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Mark all the operands that can also have an immediate.
Signed-off-by:
Am 13.02.2013 01:39, schrieb Tom Stellard:
[SNIP]
Way back when I first started working on the backend I was using
immediate operands in instructions defined to only uses registers, and
it worked most of the time, but I ran into a few cases where some of the
passes weren't able to handle it.
Ouch. Thanks for catching that -- are there any other similar things I
need to be aware of?
On Wed, Feb 13, 2013 at 8:19 PM, Kenneth Graunke kenn...@whitecape.org wrote:
On 02/08/2013 01:19 AM, Chris Forbes wrote:
V2: - emit `sample` parameter properly for multisample texelFetch()
- fix
Am 13.02.2013 08:00, schrieb Michel Dänzer:
On Die, 2013-02-12 at 19:39 -0500, Tom Stellard wrote:
On Tue, Feb 12, 2013 at 06:13:22PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Seems to be allot simpler, and also paves the
way for further improvements.
[...]
This patch implements a stub for GL_EXT_discard_framebuffer with
required checks listed by the extension specification. This extension
is required by GLBenchmark 2.5 when compiled with OpenGL ES 2.0
as the rendering backend.
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
On Tue, Feb 12, 2013 at 10:45:27PM +0100, Vincent Lejeune wrote:
It fixes around 100 tfb piglit tests and 16 glean tests.
NOTE: This is a candidate for the Mesa stable branch.
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
lib/Target/R600/AMDILISelDAGToDAG.cpp | 2 ++
On 02/12/2013 06:11 PM, Marek Olšák wrote:
Broken by 624528834f53f54c7a934f929769b7e6b230a0b1.
---
src/mesa/state_tracker/st_atom_texture.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_texture.c
On 02/12/2013 06:11 PM, Marek Olšák wrote:
---
src/mesa/state_tracker/st_cb_drawpixels.c | 28 +++
src/mesa/state_tracker/st_cb_texture.c| 30 ++---
src/mesa/state_tracker/st_format.c| 35 +
On 02/12/2013 11:04 PM, Tapani Pälli wrote:
On 02/12/2013 08:45 PM, Eric Anholt wrote:
Tapani Pälli tapani.pa...@intel.com writes:
On 02/12/2013 12:38 AM, Eric Anholt wrote:
Tapani Pälli tapani.pa...@intel.com writes:
---
src/mapi/glapi/gen/es_EXT.xml | 13 +
On Wed, Feb 13, 2013 at 4:03 PM, Brian Paul bri...@vmware.com wrote:
On 02/12/2013 06:11 PM, Marek Olšák wrote:
Broken by 624528834f53f54c7a934f929769b7e6b230a0b1.
---
src/mesa/state_tracker/st_atom_texture.c | 14 ++
1 file changed, 10 insertions(+), 4 deletions(-)
diff
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, pass the parameter slot as an operand to V_INTERP_MOV_F32
instead of hardcoding it there, and add a special register class
From: Michel Dänzer michel.daen...@amd.com
Requires corresponding LLVM R600 backend fix to work correctly, but even
without that it doesn't hang anymore.
13 more little piglits.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
https://bugs.freedesktop.org/show_bug.cgi?id=59187
--- Comment #2 from Ian Romanick i...@freedesktop.org ---
*** Bug 60481 has been marked as a duplicate of this bug. ***
--
You are receiving this mail because:
You are the assignee for the bug.
___
From: Michel Dänzer michel.daen...@amd.com
It's the reciprocal of the register value.
Fixes piglit fragcoord_w and glsl-fs-fragcoord-zw-perspective.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
On Wed, Feb 13, 2013 at 04:34:23PM +0100, Michel Dänzer wrote:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, pass the parameter slot as an operand to
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, pass the parameter slot as an operand to V_INTERP_MOV_F32
instead of hardcoding it there, and add a special register class
On Wed, Feb 13, 2013 at 05:07:43PM +0100, Michel Dänzer wrote:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, pass the parameter slot as an operand to
On Wed, Feb 13, 2013 at 10:18:23AM +0100, Christian König wrote:
Am 13.02.2013 01:20, schrieb Tom Stellard:
On Tue, Feb 12, 2013 at 06:13:19PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
SIInstrFormats.td should contain the instruction encoding definitions
On Wed, Feb 13, 2013 at 10:34:12AM +0100, Christian König wrote:
Am 13.02.2013 01:39, schrieb Tom Stellard:
[SNIP]
Way back when I first started working on the backend I was using
immediate operands in instructions defined to only uses registers, and
it worked most of the time, but I
On Tue, Feb 12, 2013 at 06:13:24PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrInfo.td|4
lib/Target/R600/SIInstructions.td |5 +
2 files changed, 9
There's just the one cleanup on patch 10 that you mentioned, but
otherwise the series looks good to me. Should we mark all these patches
as candidates for the stable branch?
For the series:
Reviewed-by: Tom Stellard thomas.stell...@amd.com
On Tue, Feb 12, 2013 at 06:13:13PM +0100, Christian
On Wed, Feb 13, 2013 at 11:24:24AM -0500, Tom Stellard wrote:
On Tue, Feb 12, 2013 at 06:13:24PM +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
Signed-off-by: Christian König christian.koe...@amd.com
---
lib/Target/R600/SIInstrInfo.td|4
From: Tom Stellard thomas.stell...@amd.com
In some cases, we were losing track of live implicit registers which
was creating dead defs and causing the scheduler to produce invalid
code.
NOTE: This is a candidate for the Mesa stable branch.
---
lib/Target/R600/AMDGPUIndirectAddressing.cpp | 35
From: Tom Stellard thomas.stell...@amd.com
Kernel function arguments are lowered to loads from the PARAM_I address
space. When creating these load instructions, we were initializing
their MachinePointerInfo with an Arguement object that was not attached
to any function. This was causing the
From: Tom Stellard thomas.stell...@amd.com
This stops the Machine Verifier from complaining about uses of undefined
physical registers.
NOTE: This is a candidate for the Mesa stable branch.
---
lib/Target/R600/R600RegisterInfo.cpp |6 ++
1 files changed, 6 insertions(+), 0 deletions(-)
From: Tom Stellard thomas.stell...@amd.com
NOTE: This is a candidate for the Mesa stable branch.
---
lib/Target/R600/R600RegisterInfo.td |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/lib/Target/R600/R600RegisterInfo.td
b/lib/Target/R600/R600RegisterInfo.td
index
From: Vadim Girlin vadimgir...@gmail.com
This is a skeleton for a pre-RA MachineInstr scheduler strategy. Currently
it only tries to expose more parallelism for ALU instructions (this also
makes the distribution of GPR channels more uniform and increases the
chances of ALU instructions to be
Am 13.02.2013 17:07, schrieb Michel Dänzer:
From: Michel Dänzer michel.daen...@amd.com
The important fix is that the constant interpolation value is stored in the
parameter slot P0, which is encoded as 2.
In addition, pass the parameter slot as an operand to V_INTERP_MOV_F32
instead of
---
src/gallium/drivers/r600/r600_asm.c | 7 ++-
src/gallium/drivers/r600/r600_asm.h | 1 +
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_asm.c
b/src/gallium/drivers/r600/r600_asm.c
index 3632aa5..eacdb0c 100644
---
On Mit, 2013-02-13 at 11:34 -0500, Tom Stellard wrote:
There's just the one cleanup on patch 10 that you mentioned, but
otherwise the series looks good to me. Should we mark all these patches
as candidates for the stable branch?
I think so, at least the parts which prevent things such as
Am 13.02.2013 18:11, schrieb Michel Dänzer:
On Mit, 2013-02-13 at 11:34 -0500, Tom Stellard wrote:
There's just the one cleanup on patch 10 that you mentioned, but
otherwise the series looks good to me. Should we mark all these patches
as candidates for the stable branch?
I think so, at least
On Mit, 2013-02-13 at 18:17 +0100, Christian König wrote:
Am 13.02.2013 18:11, schrieb Michel Dänzer:
On Mit, 2013-02-13 at 11:34 -0500, Tom Stellard wrote:
There's just the one cleanup on patch 10 that you mentioned, but
otherwise the series looks good to me. Should we mark all these
On 02/13/2013 01:39 AM, Chris Forbes wrote:
Ouch. Thanks for catching that -- are there any other similar things I
need to be aware of?
Not that I can think of, no.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
From: Michel Dänzer michel.daen...@amd.com
9 more little piglits with radeonsi.
NOTE: This is a candidate for the Mesa stable branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
lib/Target/R600/SIInstructions.td | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git
From: Michel Dänzer michel.daen...@amd.com
16 more little piglits with radeonsi.
NOTE: This is a candidate for the Mesa stable branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
lib/Target/R600/SIInstructions.td | 5 +
1 file changed, 5 insertions(+)
diff --git
From: Michel Dänzer michel.daen...@amd.com
24 more little piglits with radeonsi.
NOTE: This is a candidate for the Mesa stable branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
lib/Target/R600/SIInstructions.td | 4
1 file changed, 4 insertions(+)
diff --git
On Wed, Feb 13, 2013 at 04:34:24PM +0100, Michel Dänzer wrote:
From: Michel Dänzer michel.daen...@amd.com
Requires corresponding LLVM R600 backend fix to work correctly, but even
without that it doesn't hang anymore.
13 more little piglits.
NOTE: This is a candidate for the 9.1 branch.
From: Tom Stellard thomas.stell...@amd.com
This way llvm_wrapper.cpp is compiled with -DHAVE_LLVM=0x
---
src/gallium/drivers/r600/Makefile.am | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/Makefile.am
b/src/gallium/drivers/r600/Makefile.am
From: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/llvm_wrapper.cpp | 4
src/gallium/drivers/radeon/radeon_llvm_emit.cpp | 9 -
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/llvm_wrapper.cpp
Thanks, committed.
On 02/11/2013 10:42 PM, Tapani Pälli wrote:
From: bma bo...@windriver.com
Detect a duplicate Shader type as and error instead of silently allowing
it, restrict to ES2 API.
v2: Tapani Pälli tapani.pa...@intel.com
- make the check run time instead of compile time
On 02/13/2013 04:38 AM, Tapani Pälli wrote:
This patch implements a stub for GL_EXT_discard_framebuffer with
required checks listed by the extension specification. This extension
is required by GLBenchmark 2.5 when compiled with OpenGL ES 2.0
as the rendering backend.
Signed-off-by: Tapani
On 02/13/2013 02:25 PM, Chad Versace wrote:
On 02/13/2013 04:38 AM, Tapani Pälli wrote:
This patch implements a stub for GL_EXT_discard_framebuffer with
required checks listed by the extension specification. This extension
is required by GLBenchmark 2.5 when compiled with OpenGL ES 2.0
as the
On Tue, Feb 12, 2013 at 8:06 PM, Marek Olšák mar...@gmail.com wrote:
I should say fix, but it has never been used until now.
S8Z24 is the format equivalent to the GL_UNSIGNED_INT_24_8 packing,
so we'll start to see it more often with st/mesa now making smart decisions
about formats.
The
Hi,
Last month I finally found the time to work on the rewrite of my
previous shader optimization branch, now it's mostly done in terms of
the correctness of produced code and feature support (at least on
evergreen), though it's still a work in progress in terms of the
efficiency of
Kenneth Graunke kenn...@whitecape.org writes:
Meta-instructions that implicitly write then read/consume a MRF value
don't pose write-after-write conflicts with each other, since they're
actually:
- Write value 1, then consume it.
- Write value 2, then consume it.
OK, here's the case I'm
On 02/06/2013 05:29 PM, Eric Anholt wrote:
We'd been ad-hoc inserting instructions in some SEND messages with no
knowledge of when it was required (so extra instructions), but not all SENDs
(so not often enough). This should do much better than that, though it's
still flow-control-ignorant.
On 02/13/2013 06:31 PM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
Meta-instructions that implicitly write then read/consume a MRF value
don't pose write-after-write conflicts with each other, since they're
actually:
- Write value 1, then consume it.
- Write value 2,
Kenneth Graunke kenn...@whitecape.org writes:
On 02/13/2013 06:31 PM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
Meta-instructions that implicitly write then read/consume a MRF value
don't pose write-after-write conflicts with each other, since they're
actually:
-
On 02/13/2013 05:23 PM, Ian Romanick wrote:
On 02/12/2013 11:04 PM, Tapani Pälli wrote:
On 02/12/2013 08:45 PM, Eric Anholt wrote:
Tapani Pälli tapani.pa...@intel.com writes:
On 02/12/2013 12:38 AM, Eric Anholt wrote:
Tapani Pälli tapani.pa...@intel.com writes:
---
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