Check if any of the callocs fail and report it with _mesa_error
if needed.
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
---
src/mesa/main/attrib.c | 106 -
1 file changed, 104 insertions(+), 2 deletions(-)
diff --git
Check memory allocations before using them.
I am a bit iffy with this one though in the patches;
--
end:
if (head != NULL) {
...
}
--
When everything works it works but could not be certain if it work perfect
when something fails. If memory allocations start to return NULL
this attribute stack
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
---
src/glx/clientattrib.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/glx/clientattrib.c b/src/glx/clientattrib.c
index 1b306ea..a26906f 100644
--- a/src/glx/clientattrib.c
+++ b/src/glx/clientattrib.c
@@ -76,6
Check if any of the callocs fail and report it with _mesa_error
if needed.
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
---
src/mesa/main/attrib.c | 34 ++
1 file changed, 30 insertions(+), 4 deletions(-)
diff --git a/src/mesa/main/attrib.c
On 11/30/2013 03:29 PM, Chris Forbes wrote:
This series enables the compressed multisample layout for multisample
textures.
Previously we would only use CMS for renderbuffers, since our texelFetch()
implementation didn't understand it.
Changes from V1:
- Include fix for Haswell's second
Signed-off-by: Juha-Pekka Heikkila juhapekka.heikk...@gmail.com
---
src/glx/dri2_glx.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/glx/dri2_glx.c b/src/glx/dri2_glx.c
index 3b33312..bfeebed 100644
--- a/src/glx/dri2_glx.c
+++ b/src/glx/dri2_glx.c
@@ -676,6 +676,10 @@
On 30 November 2013 15:30, Chris Forbes chr...@ijw.co.nz wrote:
The bspec says:
SW must program the sample mask value in this field so that it matches
with 3DSTATE_SAMPLE_MASK
I haven't observed this to actually fix anything, but stumbled across it
while adding the rest of the support for
https://bugs.freedesktop.org/show_bug.cgi?id=72230
Priority: medium
Bug ID: 72230
Assignee: mesa-dev@lists.freedesktop.org
Summary: Unable to extract MesaLib-10.0.0.tar.{gz,bz2} with
bsdtar
Severity: major
On 1 December 2013 00:24, Chris Forbes chr...@ijw.co.nz wrote:
We need to emit extra shader code in this case to sample the
MCS surface first; we can't just blindly do this all the time
since IVB will sometimes try to access the MCS surface even if
disabled.
V3: Use actual MSAA layout from
On 30 November 2013 15:30, Chris Forbes chr...@ijw.co.nz wrote:
Signed-off-by: Chris Forbes chr...@ijw.co.nz
---
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 42
+-
2 files changed, 36 insertions(+), 7
On 30 November 2013 15:29, Chris Forbes chr...@ijw.co.nz wrote:
This series enables the compressed multisample layout for multisample
textures.
Previously we would only use CMS for renderbuffers, since our texelFetch()
implementation didn't understand it.
Changes from V1:
- Include fix for
https://bugs.freedesktop.org/show_bug.cgi?id=72230
a.ra...@arcor.de changed:
What|Removed |Added
CC||a.ra...@arcor.de
--
You are
https://bugs.freedesktop.org/show_bug.cgi?id=72230
Patrick Steinhardt p...@pks.im changed:
What|Removed |Added
CC||p...@pks.im
--
You are
Oops -- when I wrote the comment I was still hoping this would have
some visible effect on the problem I was hunting; never updated it.
On Tue, Dec 3, 2013 at 4:51 AM, Paul Berry stereotype...@gmail.com wrote:
On 30 November 2013 15:30, Chris Forbes chr...@ijw.co.nz wrote:
The bspec says:
SW
Yes, that's nicer. Will fix.
On Tue, Dec 3, 2013 at 5:04 AM, Paul Berry stereotype...@gmail.com wrote:
On 1 December 2013 00:24, Chris Forbes chr...@ijw.co.nz wrote:
We need to emit extra shader code in this case to sample the
MCS surface first; we can't just blindly do this all the time
Paul,
You had some patches a while ago that did CMS - UMS conversion, but
ended up not being needed -- if we wanted ot resurrect the conversion
code itself, it would now be straightforward to get CMS for signed
integer surfaces as well, until we see the app try to mask off
channels.
Do you think
On 2 December 2013 10:01, Chris Forbes chr...@ijw.co.nz wrote:
Paul,
You had some patches a while ago that did CMS - UMS conversion, but
ended up not being needed -- if we wanted ot resurrect the conversion
code itself, it would now be straightforward to get CMS for signed
integer surfaces
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 34 ++
src/mesa/drivers/dri/i965/brw_cfg.h | 3 +++
2 files changed, 37 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index e9d2bb8..cfe43d2 100644
---
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
make_list is just a one-line wrapper and was confusingly called by
NULL objects. E.g., cur_if == NULL; cur_if-make_list(mem_ctx).
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 20 +++-
src/mesa/drivers/dri/i965/brw_cfg.h | 2 --
2 files changed, 7 insertions(+), 15 deletions(-)
Unnecessary since last commit.
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index 83c3c34..c89767b 100644
--- a/src/mesa/drivers/dri/i965/brw_cfg.cpp
Useful for finding the associated control flow instructions, given a
block ending in one.
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 31 ---
src/mesa/drivers/dri/i965/brw_cfg.h | 10 ++
2 files changed, 38 insertions(+), 3 deletions(-)
diff --git
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 1 -
src/mesa/drivers/dri/i965/brw_cfg.h | 4 +++-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index c89767b..613aa80 100644
---
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 33 -
src/mesa/drivers/dri/i965/brw_cfg.h | 10 +-
2 files changed, 17 insertions(+), 26 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index
This is the last thing that register_coalesce() still handled.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index eecde62..168411c 100644
---
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
b/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
index
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 147 ---
src/mesa/drivers/dri/i965/brw_fs.h | 1 -
2 files changed, 148 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 168411c..ad1323c 100644
---
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_cfg.cpp
b/src/mesa/drivers/dri/i965/brw_cfg.cpp
index 9391b36..eb84640 100644
--- a/src/mesa/drivers/dri/i965/brw_cfg.cpp
+++
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 10 +-
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index ad1323c..2d41c3f 100644
---
---
src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_copy_propagation.cpp
I translated copysign(0.0f, x) a little too literally.
---
src/glsl/lower_instructions.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/glsl/lower_instructions.cpp b/src/glsl/lower_instructions.cpp
index d01879c..8f8d448 100644
--- a/src/glsl/lower_instructions.cpp
parent_mem_ctx was unused since db47074a, so remove the two wrappers
around create() and make create() the constructor.
---
src/mesa/drivers/dri/i965/brw_cfg.cpp | 13 +
src/mesa/drivers/dri/i965/brw_cfg.h | 5 +
On 11/26/2013 07:13 PM, Paul Berry wrote:
On 26 November 2013 17:34, Chad Versace chad.vers...@linux.intel.comwrote:
Pre-patch, the workaround was applied to only HSW GT3. However, the
workaround also fixes render corruption on the HSW GT1 Chromebook,
codenamed Falco.
CC: Anuj Phogat
On 25 November 2013 11:08, Ian Romanick i...@freedesktop.org wrote:
On 11/22/2013 03:08 PM, Paul Berry wrote:
The ARB_geometry_shader4 spec says, in the list of conditions necessary
for framebuffer completeness:
* If any framebuffer attachment is layered, all attachments must
have
Yes, we could avoid having four copies of essentially the same code by
using templates here.
---
src/mesa/drivers/dri/i965/brw_fs.h | 8
src/mesa/drivers/dri/i965/brw_shader.h | 8
src/mesa/drivers/dri/i965/brw_vec4.h | 16
3 files changed, 32
Useful because the total number of uniform components might exceed
MAX_UNIFORMS * 4 in some cases because of the image metadata we'll be
passing as push constants.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 2 +-
The same effect can be achieved using a combination of ::stride and
::subreg_offset. Remove the less flexible ::smear to keep the data
members of fs_reg orthogonal.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 23 +-
src/mesa/drivers/dri/i965/brw_fs.h
There doesn't seem to be any reason for it to be a method, and it's
surprising that the expression 'reg.retype(t)' doesn't retype its
object but rather it creates a temporary with the new type. Use
'retype(reg, t)' instead.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 8
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 29 +++---
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
.../drivers/dri/i965/brw_fs_copy_propagation.cpp | 7 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 8 +++---
This way it can be used anywhere. I need it from the visitor.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 --
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 28 +---
src/mesa/drivers/dri/i965/brw_program.c | 10 +
The same effect can be achieved using ::subreg_offset. Remove the
less flexible alternative and define a convenience function to keep
the fs_reg interface sane.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 9 ++---
src/mesa/drivers/dri/i965/brw_fs.h | 11 ++-
Like the VEC4 back-end does. It will make dynamic allocation of the
param_size array easier in a future commit.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 51 +---
src/mesa/drivers/dri/i965/brw_fs.h | 3 ++
src/mesa/drivers/dri/i965/brw_fs_fp.cpp |
It would be nice if we could have a single 'reg_offset' field
expressed in bytes that would serve the purpose of both, but the
semantics of 'reg_offset' are quite complex currently (it's measured
in units of one, eight or sixteen dwords depending on the register
file and the dispatch width) and
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 8
src/mesa/drivers/dri/i965/brw_vec4.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 73f91a0..4458e76 100644
---
Most of the VEC4 back-end agrees on src_reg::swizzle being one of the
BRW_SWIZZLE macros defined in brw_reg.h, except in two places where we
use Mesa's SWIZZLE macros. There is even a doxygen comment saying
that Mesa's macros are the right ones. They are incompatible swizzle
representations (3
---
src/mesa/drivers/dri/i965/brw_fs_fp.cpp | 131 +++-
1 file changed, 62 insertions(+), 69 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
b/src/mesa/drivers/dri/i965/brw_fs_fp.cpp
index b537a5a..5433023 100644
---
Until now it was only being taken into account in the VEC4 back-end
but not in the FS back-end. Do it in both cases.
---
src/mesa/drivers/dri/i965/brw_fs.h | 2 +-
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 10 ++
src/mesa/drivers/dri/i965/brw_shader.h | 7
---
src/mesa/drivers/dri/i965/brw_vec4.h | 24
1 file changed, 24 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index db1604a..8ce3a5e 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.h
+++
---
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index 951560b..b19b40d 100644
---
---
src/mesa/drivers/dri/i965/brw_reg.h | 2 ++
src/mesa/drivers/dri/i965/brw_vec4_vp.cpp | 33 +--
2 files changed, 11 insertions(+), 24 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 66f6aad..37a2ca9
This will be used by the generic implementation of the image and
atomic counter built-ins to extract the register location of its
arguments without having to be aware of the actual visitor type.
---
src/mesa/drivers/dri/i965/brw_fs.h | 3 +++
---
src/mesa/drivers/dri/i965/brw_reg.h | 21 +
1 file changed, 21 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_reg.h
b/src/mesa/drivers/dri/i965/brw_reg.h
index 37a2ca9..2591cbf 100644
--- a/src/mesa/drivers/dri/i965/brw_reg.h
+++
---
src/mesa/drivers/dri/i965/brw_clip_util.c | 2 +-
src/mesa/drivers/dri/i965/brw_reg.h | 40 +++
2 files changed, 31 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_clip_util.c
b/src/mesa/drivers/dri/i965/brw_clip_util.c
index
Add assertion that the register is not in the HW_REG or IMM file,
calculate the conjunction of the old and new mask instead of replacing
the old [consistent with the behavior of brw_writemask(), causes no
functional changes right now], make it static inline to let the
compiler do a slightly better
---
src/mesa/drivers/dri/i965/brw_context.h | 5 +
src/mesa/drivers/dri/i965/brw_shader.cpp | 7 +++
2 files changed, 12 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 1387aa9..3f2edcf 100644
---
This defines a backend_reg class that contains most of the common
member variables present in the fs and vec4 register classes. It's
simply a location in the register file and doesn't know about indirect
addressing or funky align1/align16 access modes.
Some of the image lowering code coming up
This is a series of assorted clean-up and refactoring changes in
preparation for the actual series implementing shader images. The
most important changes in this series are PATCH 06, that defines the
register representation class used by the image built-in lowering
code, and PATCH 07-08, that add
There doesn't seem to be any reason for nr_params, nr_pull_params,
param, and pull_param to be duplicated in the stage-specific
subclasses of brw_stage_prog_data. Moving their definition to the
common base class will allow some code sharing in a future commit, the
removal of
This moves most of the surface state set-up logic that can be shared
between textures and shader images to a separate function.
---
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 102 +-
1 file changed, 62 insertions(+), 40 deletions(-)
diff --git
---
src/mesa/drivers/dri/i965/brw_defines.h| 1 +
src/mesa/drivers/dri/i965/brw_eu.h | 8
src/mesa/drivers/dri/i965/brw_eu_emit.c| 49 ++
src/mesa/drivers/dri/i965/brw_fs.cpp | 1 +
---
src/mesa/drivers/dri/i965/brw_defines.h | 3 +++
src/mesa/drivers/dri/i965/gen7_gs_state.c | 4 +++-
src/mesa/drivers/dri/i965/gen7_vs_state.c | 13 -
src/mesa/drivers/dri/i965/gen7_wm_state.c | 3 +++
4 files changed, 17 insertions(+), 6 deletions(-)
diff --git
This will be used to pass image information to the shader when we
cannot use typed surface reads and writes. All entries except
surface_idx and size are otherwise unused and will get eliminated by
the uniform packing pass. size will be used for bounds checking with
some image formats and will be
And remove duplicated definition of OWORD_DUAL_BLOCK_WRITE.
---
src/mesa/drivers/dri/i965/brw_defines.h | 8 +++-
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 2 +-
2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 51 +--
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 10 ++
2 files changed, 50 insertions(+), 11 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
---
src/mesa/drivers/dri/i965/brw_context.h | 2 +
src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 24
src/mesa/drivers/dri/i965/brw_state.h| 3 ++
src/mesa/drivers/dri/i965/brw_state_upload.c | 6 +++
src/mesa/drivers/dri/i965/brw_vs_surface_state.c |
---
src/mesa/drivers/dri/i965/brw_vec4.h | 9 --
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 109 +
2 files changed, 19 insertions(+), 99 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.h
b/src/mesa/drivers/dri/i965/brw_vec4.h
index
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 36 +++--
src/mesa/drivers/dri/i965/brw_fs.h | 4 +++
src/mesa/drivers/dri/i965/brw_shader.cpp | 25 +++
src/mesa/drivers/dri/i965/brw_shader.h | 4 +++
Until now atomic counter built-ins were handled in a way that
prevented the visitor from encountering atomic counter IR variables
and dereferences directly. In the new surface lowering code it's
going to be more convenient to be able to call back into the visitor
to let it handle the ugly details
---
src/mesa/drivers/dri/i965/brw_defines.h | 2 +
src/mesa/drivers/dri/i965/brw_eu.h | 4 ++
src/mesa/drivers/dri/i965/brw_eu_emit.c | 69
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +
---
src/mesa/drivers/dri/i965/brw_fs.h | 9 --
src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 38 --
src/mesa/drivers/dri/i965/brw_vec4.h | 9 --
src/mesa/drivers/dri/i965/brw_vec4_generator.cpp | 40
4 files
Change brw_untyped_atomic() and brw_untyped_surface_read() to take the
surface index as a register instead of a constant, construct the
message descriptor dynamically by OR'ing the surface index and other
descriptor bits together and use the non-immediate variant of SEND to
submit the surface
---
src/mesa/drivers/dri/i965/brw_defines.h| 4 +
src/mesa/drivers/dri/i965/brw_eu.h | 25
src/mesa/drivers/dri/i965/brw_eu_emit.c| 166 +
src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +
---
src/mesa/drivers/dri/i965/brw_fs.h | 9 --
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 138 ---
2 files changed, 18 insertions(+), 129 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.h
b/src/mesa/drivers/dri/i965/brw_fs.h
index
---
src/mesa/drivers/dri/i965/brw_context.h | 10 ++
src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 175 ++
2 files changed, 185 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 20
1 file changed, 20 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
index 26300a6..dc6d35e 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++
Until now atomic counter built-ins were handled in a way that
prevented the visitor from encountering atomic counter IR variables
and dereferences directly. In the new surface lowering code it's
going to be more convenient to be able to call back into the visitor
to let it handle the ugly details
---
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 54 ---
src/mesa/drivers/dri/i965/intel_batchbuffer.h | 2 +
2 files changed, 34 insertions(+), 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
---
src/mesa/drivers/dri/i965/intel_reg.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/drivers/dri/i965/intel_reg.h
b/src/mesa/drivers/dri/i965/intel_reg.h
index 13b68cc..23bf0ac 100644
--- a/src/mesa/drivers/dri/i965/intel_reg.h
+++ b/src/mesa/drivers/dri/i965/intel_reg.h
@@
---
src/mesa/drivers/dri/i965/brw_context.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_context.c
b/src/mesa/drivers/dri/i965/brw_context.c
index 6de6759..ce8c311 100644
--- a/src/mesa/drivers/dri/i965/brw_context.c
+++
---
src/mesa/drivers/dri/i965/intel_extensions.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
index ab27d43..5145034 100644
--- a/src/mesa/drivers/dri/i965/intel_extensions.c
+++
---
src/mesa/drivers/dri/i965/brw_program.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_program.c
b/src/mesa/drivers/dri/i965/brw_program.c
index 094deeb..44af46f 100644
--- a/src/mesa/drivers/dri/i965/brw_program.c
+++
https://bugs.freedesktop.org/show_bug.cgi?id=72230
--- Comment #1 from Emil Velikov emil.l.veli...@gmail.com ---
Created attachment 90116
-- https://bugs.freedesktop.org/attachment.cgi?id=90116action=edit
include only one copy of VERSION in tarball
Seems like adding VERSION to EXTRA_FILES was
The VERSION file is tracked by git (git ls-files), thus
adding it to EXTRA_FILES will result in a duplicate copy
within the final tarball.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=72230
Cc: 10.0 mesa-sta...@lists.freedesktop.org
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
https://bugs.freedesktop.org/show_bug.cgi?id=72230
--- Comment #2 from Patrick Steinhardt p...@pks.im ---
I can confirm the attached patch fixes the problem. Thanks.
--
You are receiving this mail because:
You are the assignee for the bug.
___
+fs_reg::fs_reg(const backend_reg reg)
+{
+ init();
+ *static_castbackend_reg *(this) = reg;
This is a bit gross...
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
Chris Forbes chr...@ijw.co.nz writes:
+fs_reg::fs_reg(const backend_reg reg)
+{
+ init();
+ *static_castbackend_reg *(this) = reg;
This is a bit gross...
Would you prefer 'this-operator=(reg);'?
Meh... :)
pgphocK2Fll37.pgp
Description: PGP signature
Ideally, we wouldn't need init() and you could just have a
copy-constructor do the right thing, I think -- currently, all the
backend_reg fields get initialized 3 times:
- backend_reg ctor
- init() blasting everything to zero
- this assignment
On Tue, Dec 3, 2013 at 9:22 AM, Francisco Jerez
Chris Forbes chr...@ijw.co.nz writes:
Ideally, we wouldn't need init() and you could just have a
copy-constructor do the right thing, I think -- currently, all the
backend_reg fields get initialized 3 times:
- backend_reg ctor
- init() blasting everything to zero
- this assignment
Yeah, I
On 12/01/2013 01:53 AM, Tapani Pälli wrote:
Commit a594cec broke EGL X11 backend by adding dependency between
X11 and DRM backends requiring HAVE_EGL_PLATFORM_DRM defined for X11.
This patch fixes the issue by adding additional define for libdrm
detection independent of which backend is being
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 +-
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index f10f5c0..f3b121a 100644
---
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_disasm.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 97f8906..0a45f05 100644
---
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 7 +++
1 file changed, 7 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 551f0a2..71f5307 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 48 ++--
1 file changed, 46 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index b59ab82..c21239f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 71f5307..13f69f1 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/brw_disasm.c | 2 +-
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_context.h
b/src/mesa/drivers/dri/i965/brw_context.h
index 0a45f05..d25e145 100644
---
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 6 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp | 6 +-
2 files changed, 10 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index c21239f..f10f5c0 100644
---
---
src/mesa/drivers/dri/i965/brw_vec4.cpp | 60 ++
1 file changed, 60 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp
b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index fed6e61..551f0a2 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++
On Mon, Dec 2, 2013 at 11:53 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
The VERSION file is tracked by git (git ls-files), thus
adding it to EXTRA_FILES will result in a duplicate copy
within the final tarball.
Reviewed-by: Matt Turner matts...@gmail.com
Ugh. :(
And since this change makes ENDIF start blocks, I'll squash this
change in as well to make sure dead_control_flow_eliminate continues
working:
diff --git a/src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp
b/src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp
index ad8ed82..63a3e5b 100644
---
total instructions in shared programs: 1519751 - 1519442 (-0.02%)
instructions in affected programs: 10154 - 9845 (-3.04%)
---
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp | 23 +++
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp | 23 ---
2 files
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