On Fri, May 29, 2015 at 12:26:40PM -0700, Kenneth Graunke wrote:
See the corresponding code in brw_vs_surface_state.c.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_gs_surface_state.c | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
This patch implements the binding table enable command which is also
used to allocate a binding table pool where where hardware-generated
binding table entries are flushed into. Each binding table offset in
the binding table pool is unique per each shader stage that are
enabled within a batch.
This is needed since kernel doesn't support RS context save and
restore on BDW yet. So manually disable hw-generated binding tables
when done using it in the batch. Otherwise the GPU would no longer
accept software binding tables submitted by other clients including
but not limited to the Xorg
When hardware-generated binding tables are enabled, use the hw-generated
binding table format when uploading binding table state.
Normally, the CS will will just consume the binding table pointer commands
as pipelined state. When the RS is enabled however, the RS flushes whatever
edited surface
v2: Simplify HW binding table bit definitions and magic constants (Topi)
v3: Add Broadwell support.
Cc: kristian.h.kristen...@intel.com
Cc: topi.pohjolai...@intel.com
Cc: kenn...@whitecape.org
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
Signed-off-by: Abdiel Janulgue
This is passed on the kernel to enable the resource streamer enable bit
on MI_BATCHBUFFER_START
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
---
src/mesa/drivers/dri/i965/brw_context.h | 1 +
src/mesa/drivers/dri/i965/intel_batchbuffer.c | 8 +++-
2 files changed, 8
Unlike normal software binding tables where the driver has to manually
generate and fill a binding table array which are then uploaded to the
hardware, the resource streamer instead presents the driver with an option
to fill out slots for individual binding table indices. The hardware
accumulates
On Sun, 2015-05-31 at 20:41 -0700, Kenneth Graunke wrote:
On Monday, June 01, 2015 11:35:03 AM Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
I'm not sure if we shouldn't enable this everywhere
and rip out the API checks,
discuss,
Signed-off-by: Dave Airlie
On Fri, May 22, 2015 at 02:24:49PM -0400, Connor Abbott wrote:
Signed-off-by: Connor Abbott cwabbo...@gmail.com
Reviewed-by: Topi Pohjolainen topi.pohjolai...@intel.com
---
src/glsl/nir/nir.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/glsl/nir/nir.h
Switch off hardware-generated binding tables and gather push
constants in the blorp. Blorp requires only a minimal set of
simple constants. There is no need for the extra complexity
to program a gather table entry into the pipeline.
Signed-off-by: Abdiel Janulgue abdiel.janul...@linux.intel.com
In that case, it should use the ARB_gpu_shader5 enable bit.
Marek
On Mon, Jun 1, 2015 at 5:41 AM, Kenneth Graunke kenn...@whitecape.org wrote:
On Monday, June 01, 2015 11:35:03 AM Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
I'm not sure if we shouldn't enable this everywhere
and
On Fri, May 22, 2015 at 02:24:50PM -0400, Connor Abbott wrote:
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/nir/nir.h | 4 ++--
src/glsl/nir/nir_instr_compare.c | 8
2 files changed, 6 insertions(+), 6 deletions(-)
diff --git a/src/glsl/nir/nir.h
https://bugs.freedesktop.org/show_bug.cgi?id=90797
Eero Tamminen eero.t.tammi...@intel.com changed:
What|Removed |Added
CC|
Hi,
On 05/29/2015 07:04 PM, Connor Abbott wrote:
On Fri, May 29, 2015 at 6:23 AM, Eero Tamminen
eero.t.tammi...@intel.com wrote:
On 05/28/2015 10:19 PM, Thomas Helland wrote:
One more thing;
Is there a limit where the loop body gets so large that we
want to decide that gah, this sucks, no
On Fri, May 22, 2015 at 02:24:51PM -0400, Connor Abbott wrote:
This can be used for both CSE and value numbering.
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/Makefile.sources | 2 +
src/glsl/nir/nir_instr_hash.c | 255
++
NOP actually has no compact version, but we use it for instruction
alignment for compact kernel. Although it seems working on HW, it is
illegal and might not be valid for any future one.
This trys to get a temporary compact instruction with no effect for
alignment to replace compacted NOP. G45
On Jun 1, 2015 8:41 AM, Pohjolainen, Topi topi.pohjolai...@intel.com
wrote:
On Mon, Jun 01, 2015 at 06:50:24AM -0700, Jason Ekstrand wrote:
On Jun 1, 2015 3:20 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com
wrote:
On Fri, May 22, 2015 at 02:24:50PM -0400, Connor Abbott
On Mon, Jun 01, 2015 at 06:50:24AM -0700, Jason Ekstrand wrote:
On Jun 1, 2015 3:20 AM, Pohjolainen, Topi topi.pohjolai...@intel.com
wrote:
On Fri, May 22, 2015 at 02:24:50PM -0400, Connor Abbott wrote:
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
And update assertions to be more informative.
---
src/egl/drivers/dri2/egl_dri2.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index fe5cbc8..8b915ef 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++
---
src/gallium/auxiliary/gallivm/lp_bld_format_aos.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
b/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
index 3c25c32..efe7170 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
On 01/06/15 14:20, Brian Paul wrote:
---
src/gallium/auxiliary/draw/draw_llvm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/draw/draw_llvm.c
b/src/gallium/auxiliary/draw/draw_llvm.c
index b9e55af..885c27c 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.c
On Jun 1, 2015 3:20 AM, Pohjolainen, Topi topi.pohjolai...@intel.com
wrote:
On Fri, May 22, 2015 at 02:24:50PM -0400, Connor Abbott wrote:
Signed-off-by: Connor Abbott cwabbo...@gmail.com
---
src/glsl/nir/nir.h | 4 ++--
src/glsl/nir/nir_instr_compare.c | 8
2
Many thanks for all the reviews and testing. I've pushed the two
patches.
The remaining sampler_array_indexing tests that fail on SKL (the gs
ones) are because of a separate problem described in this patch:
http://patchwork.freedesktop.org/patch/50676/
I'm not really sure whether that's the
Hello,
I have the pleasure to announce that the X.org Developer Conference 2015
will be held in Toronto, Canada from September 16 to September 18. The
venue is located at Seneca College's campus at York University.
The official page for the event is http://www.x.org/wiki/Events/XDC2015
while the
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 719d081..db190c9 100644
--- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
+++
You did not do changes I suggested but it looks to me that the comments
are still valid.
(http://lists.freedesktop.org/archives/mesa-dev/2015-April/082523.html)
In a nutshell, parameters that get written to should have qualifier
output=true. It could be that it is not strictly required,
---
src/gallium/auxiliary/draw/draw_llvm.c | 4
1 file changed, 4 insertions(+)
diff --git a/src/gallium/auxiliary/draw/draw_llvm.c
b/src/gallium/auxiliary/draw/draw_llvm.c
index b9e55af..885c27c 100644
--- a/src/gallium/auxiliary/draw/draw_llvm.c
+++
---
src/gallium/auxiliary/util/u_format_etc.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_format_etc.c
b/src/gallium/auxiliary/util/u_format_etc.c
index f909b16..63e03ff 100644
--- a/src/gallium/auxiliary/util/u_format_etc.c
+++
---
src/gallium/auxiliary/pipebuffer/pb_buffer_fenced.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/auxiliary/pipebuffer/pb_buffer_fenced.c
b/src/gallium/auxiliary/pipebuffer/pb_buffer_fenced.c
index 3bd9cd7..fc81e11 100644
---
On 06/01/2015 11:13 AM, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed into the
macro be a power of two in the comments. Using software assertions verifies
this to be the case.
Signed-off-by: Nanley Chery
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +--
1 file changed, 5
From: Nanley Chery nanley.g.ch...@intel.com
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 3 +
src/mesa/main/formats.c | 130
From: Nanley Chery nanley.g.ch...@intel.com
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Along with changing the cpp
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove extra newline.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
2 files changed, 6 insertions(+), 24 deletions(-)
diff --git
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed into the
macro be a power of two in the comments. Using software assertions verifies
this to be the case.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
v2: remove extra newlines.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index
From: Nanley Chery nanley.g.ch...@intel.com
v2: correct the spelling of the sRGB variants.
remove spaces around = when setting the enum value.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
.../glapi/gen/KHR_texture_compression_astc.xml | 40 ++
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 6a77c91..10e2a87 100644
From: Nanley Chery nanley.g.ch...@intel.com
v2: alphabetize the extensions.
remove OES ASTC extension.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c | 2 ++
src/mesa/main/mtypes.h | 2 ++
2 files changed, 4 insertions(+)
diff --git
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50 insertions(+)
diff --git a/src/mesa/main/texcompress.c
On 06/01/2015 11:46 AM, Brian Paul wrote:
On 06/01/2015 11:13 AM, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the
macro be a power of two in the comments. Using software assertions
verifies
this to be
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all
From: Nanley Chery nanley.g.ch...@intel.com
In this revision, comments have been taken into account and most rendering
issues have been fixed. Unfortunately, when rendering the reference sRGB
textures, the HW-loaded compressed versions are still rendered darker than
the pre-decoded SW ones. The
From: Nanley Chery nanley.g.ch...@intel.com
- Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
- Don't pass more parameters than necessary.
- Minor code simplifications.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove OES ASTC extension reference.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
On Mon, Jun 1, 2015 at 6:20 AM, Brian Paul bri...@vmware.com wrote:
And update assertions to be more informative.
---
src/egl/drivers/dri2/egl_dri2.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
On Fri, Apr 24, 2015 at 10:54 AM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Thu, Apr 23, 2015 at 4:38 PM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Fri, Apr 17, 2015 at 04:51:23PM -0700, Anuj Phogat wrote:
This refactoring is required by later patches in this series.
Looks good to me.
Reviewed-by: Neil Roberts n...@linux.intel.com
- Neil
Anuj Phogat anuj.pho...@gmail.com writes:
Adding Neil to Cc who committed 4ab8d59.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
___
mesa-dev mailing list
From: Marek Olšák marek.ol...@amd.com
eglCreateContext was failing.
Broken by 03fd6704db9f1d0f203bf8da18bd587c7e35ce60
---
src/mesa/main/version.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/version.c b/src/mesa/main/version.c
index 409e5ae..572f2da 100644
On Mon, Jun 1, 2015 at 12:44 PM, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
eglCreateContext was failing.
Broken by 03fd6704db9f1d0f203bf8da18bd587c7e35ce60
---
src/mesa/main/version.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, May 29, 2015 at 12:33 PM, Chad Versace chad.vers...@intel.com wrote:
On Fri 29 May 2015, Matt Turner wrote:
On Thu, May 28, 2015 at 10:21 AM, Ben Widawsky
@@ -286,7 +284,7 @@ intel_miptree_create_layout(struct brw_context *brw,
mt-logical_height0 = height0;
OPCODE_MOV is in the op_trans[] array.
---
src/mesa/program/prog_to_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 5e104e7..d6f165e 100644
--- a/src/mesa/program/prog_to_nir.c
+++
---
I'm not missing something, am I?
src/mesa/program/prog_to_nir.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 5ca81e5..5e104e7 100644
--- a/src/mesa/program/prog_to_nir.c
+++
On Mon, Jun 1, 2015 at 10:13 AM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
https://bugs.freedesktop.org/show_bug.cgi?id=89018
--- Comment #17 from Sami Liedes sami.lie...@iki.fi ---
I noticed that the game works perfectly for me on Intel HD Graphics 5500 on a
Debian unstable with mesa from Debian unstable (though I think Xorg from
experimental). Loading the same game on
I've merged a bunch of Chris's parser changes into mine,
mainly because the parser needs a bunch of changes to handle
the fact that .name() no longer parses the same, and after
reading the GLSL spec and glslang, and failing every other
way I tried, I produced what looks to be the correct
From: Dave Airlie airl...@redhat.com
This is what it looks like, seems to work fine.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ir.cpp| 4 +++-
src/glsl/ir.h | 1 +
src/glsl/ir_builder.cpp| 6 ++
Emil,
Thank you so much for your reply. I will rebase my patch to mesa master branch
and rerun the tests. I will then send you the test result.
Thanks
Ying
-Original Message-
From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
Sent: Saturday, May 30, 2015 4:57 AM
To: Liu, Ying2
Cc:
On Monday, June 01, 2015 01:03:10 PM Matt Turner wrote:
OPCODE_MOV is in the op_trans[] array.
---
src/mesa/program/prog_to_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/program/prog_to_nir.c b/src/mesa/program/prog_to_nir.c
index 5e104e7..d6f165e
On Monday, June 01, 2015 03:14:24 PM Abdiel Janulgue wrote:
v2: Simplify HW binding table bit definitions and magic constants (Topi)
v3: Add Broadwell support.
Cc: kristian.h.kristen...@intel.com
Cc: topi.pohjolai...@intel.com
Cc: kenn...@whitecape.org
Reviewed-by: Topi Pohjolainen
Matt,
Thank you so much for reviewing my patch. This is my first time sending out
patch to mesa community. Your comments are very helpful. I am in a training
right now. I will update my patch according to the comments after that.
Thanks
Ying
-Original Message-
From: Matt Turner
On Monday, June 01, 2015 01:03:09 PM Matt Turner wrote:
---
I'm not missing something, am I?
src/mesa/program/prog_to_nir.c | 14 +++---
1 file changed, 7 insertions(+), 7 deletions(-)
Nope, I think this was copy and pasted. IIRC these do scalar operations
and splat results,
On Tuesday, June 02, 2015 10:16:11 AM Dave Airlie wrote:
From: Dave Airlie airl...@redhat.com
This is what it looks like, seems to work fine.
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/glsl/ir.cpp| 4 +++-
src/glsl/ir.h
Kenneth Graunke kenn...@whitecape.org writes:
On Monday, June 01, 2015 01:03:10 PM Matt Turner wrote:
OPCODE_MOV is in the op_trans[] array.
---
src/mesa/program/prog_to_nir.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/program/prog_to_nir.c
67 matches
Mail list logo
