Previous patches made it so that we do not need to unspill the same vgrf
with every instruction as long as these instructions come right after
the register was spilled or unspilled. This means that actually spilling
the register is now cheaper in these scenarios, so adjust the spilling
cost
Similar to reads inmmediately after spilling, there is no gain for register
allocation in unspilling the same vgrf in consecutive instructions, since
the gain only comes when there are gaps in the program that don't use the
vgrf. In these scenarios we can simply unspill once and reuse the result
In theory, GRF array access should have been moved to scratch by the time
we got here, so this should never happen. A full piglit run forcing
spilling of all registers seems to confirm this. The FS backend
does not seem to check for this either.
---
When we have code such as this:
mov vgrf1.0.x:F, vgrf2.:F
mov vgrf3.0.x:F, vgrf1.:F
...
mov vgrf3.0.x:F, vgrf1.:F
And vgrf1 is chosen for spilling, we can emit this:
mov vgrf1.0.x:F, vgrf2.:F
gen4_scratch_write hw_reg0:F, vgrf1.:D, 22D
mov vgrf3.0.x:F, vgrf1.:F
...
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_vec4.cpp| 2 +-
src/mesa/drivers/dri/i965/intel_debug.c | 3 ++-
src/mesa/drivers/dri/i965/intel_debug.h | 5 +++--
4 files changed, 7 insertions(+), 5 deletions(-)
diff
---
src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
b/src/mesa/drivers/dri/i965/brw_vec4_reg_allocate.cpp
index cd89edd..a9bf0d8 100644
---
Link to v1:
http://lists.freedesktop.org/archives/mesa-dev/2015-July/089766.html
Changes after review (Curro)
- Drop the patch that asserted that the reg size should always be 1
- Expand this so that we do not unspill a register if we have just
unspilled it as well
- Use
On 28/07/15 09:20, Lofstedt, Marta wrote:
-Original Message-
From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
Behalf Of Samuel Iglesias Gonsálvez
Sent: Tuesday, July 28, 2015 7:24 AM
To: Marta Lofstedt; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH
-Original Message-
From: Samuel Iglesias Gonsálvez [mailto:sigles...@igalia.com]
Sent: Tuesday, July 28, 2015 9:25 AM
To: Lofstedt, Marta; Marta Lofstedt; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH v6 1/4] mesa/es3.1: enable
GL_ARB_shader_image_load_store for GLES
Emit the SELs and MOVs with the same execution controls as the
original MOVs, and the CMP with the same execution controls as the IF.
Also explicitly check that the execution controls of any pair of MOVs
being folded into a SEL are compatible (which is almost always going
to be the case), since
Instead of relying on the default one. This shouldn't lead to any
functional changes because DEP_RESOLVE_MOV overrides the execution
controls of the instruction anyway.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git
The execution size was being left equal to the default of 8/16, which
AFAICT would have overwritten components other than the one we wanted
to initialize and could potentially have corrupted other registers.
---
src/mesa/drivers/dri/i965/brw_fs_combine_constants.cpp | 2 +-
1 file changed, 1
lower_integer_multiplication() was ignoring the execution controls of
the original MUL instruction. Fix it by using the new fs_builder
constructor.
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 7 ++-
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 8bc9372..2775d98 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++
It's not guaranteed to have the same width as the instruction
generating the spilled variable.
---
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp
We have a number of optimization passes that repeat the same pattern
before inserting new instructions into the program based on some
previous instruction: They point the default builder at the original
instruction, then call exec_all() and group() to select the same
execution controls the
Not a typo. Replace the default builder with one of bogus width to
catch cases in which optimization passes assume that the default
dispatch width is good enough. The execution controls of instructions
emitted during optimization should in general match the original code
that is being
opt_sampler_eot() was relying on the default builder to have the same
width as the sampler and FB write opcodes it was eliminating, the
channel selects didn't matter because the builder was only being used
to allocate registers, no new instructions were being emitted with it.
A future commit will
This wasn't taking into account the execution controls of the original
instruction, but it was most likely not a bug because control flow
instructions are typically full width.
---
src/mesa/drivers/dri/i965/brw_fs_peephole_predicated_break.cpp | 8 +---
1 file changed, 5 insertions(+), 3
---
src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
index e33fe6a..a123ff2 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp
+++
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp
b/src/mesa/drivers/dri/i965/brw_fs.cpp
index 2775d98..57e4dd7 100644
--- a/src/mesa/drivers/dri/i965/brw_fs.cpp
+++
demote_pull_constants() was ignoring the execution size and channel
selects of the instruction that wanted the constant, which doesn't
matter for uniform pull constant loads because all channels get the
same scalar value, but it might for varying pull constant loads. Fix
it by using the new
This could have led to somewhat increased bandwidth usage for lowered
texturing instructions on Gen4 (which is the only case in which
lower_width may be greater than inst-exec_size). After the previous
patches the invariant mentioned in the comment should no longer be
assumed by any of the other
The register coalesce pass wasn't rewriting the destination and
sources of instructions that accessed the second half of a coalesced
register previously copied with a 16-wide MOV instruction. E.g.:
| ADD (16) vgrf0:f, vgrf0:f, 1.0:f
| MOV (16) vgrf1:f, vgrf0:f
| MOV (8) vgrf2:f, vgrf0+1:f {
register_coalesce() was considering the exec_size of the MOV
instruction alone to decide whether the register at offset+1 of the
source VGRF was being copied to inst-dst.reg_offset+1 of the
destination VGRF, which is only a valid assumption if the move has a
32-bit execution type. Use regs_read()
For some reason the loop that rewrites all occurrences of the
coalesced register was iterating over all possible offsets until it
would find one that compares equal to the offset of a source or
destination of any instruction in the program. Since the mapping
between old and new offsets is already
Patches 1,3,4
Reviewed-by: Tapani Pälli tapani.pa...@intel.com
On 07/27/2015 04:22 PM, Marta Lofstedt wrote:
From: Marta Lofstedt marta.lofst...@intel.com
Signed-off-by: Marta Lofstedt marta.lofst...@intel.com
---
src/mesa/main/get.c | 6 ++
-Original Message-
From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On
Behalf Of Samuel Iglesias Gonsálvez
Sent: Tuesday, July 28, 2015 7:24 AM
To: Marta Lofstedt; mesa-dev@lists.freedesktop.org
Subject: Re: [Mesa-dev] [PATCH v6 1/4] mesa/es3.1: enable
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/Makefile.sources | 1 +
src/gallium/drivers/radeonsi/si_cp_dma.c | 265 ++
src/gallium/drivers/radeonsi/si_descriptors.c | 233 --
src/gallium/drivers/radeonsi/si_pipe.c
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeonsi/si_shader.c | 2 +-
3 files changed, 3 insertions(+), 1 deletion(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=13978
Tapani Pälli lem...@gmail.com changed:
What|Removed |Added
Status|REOPENED|RESOLVED
On Tue, 2015-07-28 at 13:37 +0300, Tapani Pälli wrote:
Change function to get all gl_constants for inspection, this is used
by follow-up patch.
v2: rebase, update function documentation
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/linker.cpp | 23
From: Nanley Chery nanley.g.ch...@intel.com
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column 3D
From: Nanley Chery nanley.g.ch...@intel.com
According to the spec, Tex*Storage* commands are supported if the GL
implementation has support for immutable textures.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texformat.c | 56
On Tue, 2015-07-28 at 16:34 -0700, Kenneth Graunke wrote:
A simple shader such as
vec4 color;
color.xy.x = 1.0;
would cause ir_assignment::set_lhs() to generate bogus IR:
(swiz xy (swiz x (constant float (1.0
We were setting the number of components of each new RHS
From: Dave Airlie airl...@redhat.com
One of the oglconform tests was crashing here, and it was
due to not cloning the actual parameters before creating the
new call. This makes a call clone function that does the right
things to make sure we clone all the needed info, and points
the callee at it.
From: Dave Airlie airl...@redhat.com
This enables GL4.1 for radeonsi, and updates the
docs in the correct places.
v2: enable only for llvm 3.7 which has fixes in place.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
docs/GL3.txt
From: Dave Airlie airl...@redhat.com
This adds to the common radeon streamout code, support
for multiple streams.
It updates radeonsi/r600 to set the enabled mask up.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
From: Dave Airlie airl...@redhat.com
This is the final piece for ARB_gpu_shader5,
The code is based on the r600 code from Glenn Kennard,
and myself.
While developing this, I'm not 100% sure of all the calculations
made in the GS registers, this is why the max_stream is worked
out there and used
From: Dave Airlie airl...@redhat.com
This will be used here later.
v2: update atom sizes
add check for old vs new enabled mask
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeon/r600_pipe_common.h | 3 +++
src/gallium/drivers/radeon/r600_streamout.c | 21
From: Nanley Chery nanley.g.ch...@intel.com
The following patches add missing functionality to my prior ASTC patch series
needed to advertise support for the extension. The missing first patch was an
oversight, while the second patch is due to the release of a newer spec
revision.
The series
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/common/meta_blit.c | 6 +++---
src/mesa/drivers/dri/i915/i915_texstate.c | 2 +-
src/mesa/drivers/dri/i965/brw_fs_vector_splitting.cpp | 2 +-
src/mesa/drivers/dri/i965/brw_reg.h
On 28 July 2015 at 20:05, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git
On 28 July 2015 at 20:05, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/r600/r600_llvm.c| 1 -
src/gallium/drivers/r600/r600_shader.c | 1 -
On 07/28/2015 10:05 AM, Emil Velikov wrote:
On 28/07/15 17:54, Bish, Jim wrote:
On 07/28/2015 06:11 AM, Emil Velikov wrote:
Hello Jim,
On 28 July 2015 at 02:57, Bish, Jim jim.b...@intel.com wrote:
From: Jim Bish jim.b...@intel.com
Would you mind splitting this into separate patches ?
The last 4 had some review fixes that I rebased badly, and failed to test.
This set actually work.
Dave.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
From: Dave Airlie airl...@redhat.com
This will be used here later.
v2: update atom sizes
add check for old vs new enabled mask
Signed-off-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeon/r600_pipe_common.h | 3 +++
src/gallium/drivers/radeon/r600_streamout.c | 21
From: Dave Airlie airl...@redhat.com
This adds to the common radeon streamout code, support
for multiple streams.
It updates radeonsi/r600 to set the enabled mask up.
v2: update for changes in previous patch.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Dave Airlie
On 28/07/15 23:49, Jason Ekstrand wrote:
On Mon, Jul 27, 2015 at 3:37 PM, Alejandro Piñeiro apinhe...@igalia.com
wrote:
Uses the nir structure to get all the info needed (sources,
dest reg, etc), and then it uses the common
vec4_visitor::emit_texture to emit the final code.
---
v3:
On 28 July 2015 at 20:05, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
Looks good,
Reviewed-by: Dave Airlie airl...@redhat.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
On 28 July 2015 at 20:05, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Dave Airlie airl...@redhat.com
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 66
++
1 file changed, 66 insertions(+)
diff --git
From: Dave Airlie airl...@redhat.com
This is the final piece for ARB_gpu_shader5,
The code is based on the r600 code from Glenn Kennard,
and myself.
While developing this, I'm not 100% sure of all the calculations
made in the GS registers, this is why the max_stream is worked
out there and used
From: Dave Airlie airl...@redhat.com
This enables GL4.1 for radeonsi, and updates the
docs in the correct places.
v2: enable only for llvm 3.7 which has fixes in place.
Reviewed-by: Marek Olšák marek.ol...@amd.com
Signed-off-by: Dave Airlie airl...@redhat.com
---
docs/GL3.txt
brw_cs.cpp:386:27: warning: comparison between signed and unsigned
integer expressions [-Wsign-compare]
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_cs.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 28 July 2015 at 20:05, Marek Olšák mar...@gmail.com wrote:
From: Marek Olšák marek.ol...@amd.com
For 2 3,
Reviewed-by: Dave Airlie airl...@redhat.com
duplicated now
---
src/gallium/drivers/r600/r600_llvm.c | 34 +--
src/gallium/drivers/radeon/radeon_llvm.h
On 07/28/2015 02:38 PM, Chad Versace wrote:
On Tue 28 Jul 2015, Emil Velikov wrote:
Hello Jim,
On 28 July 2015 at 02:57, Bish, Jim jim.b...@intel.com wrote:
From: Jim Bish jim.b...@intel.com
Would you mind splitting this into separate patches ? Adding a few
words in the commit log(s)
Other stages can be miserably slow too!
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/brw_shader.cpp | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp
b/src/mesa/drivers/dri/i965/brw_shader.cpp
Same check is made for glBindFragDataLocationIndexed but it was missing
when using layout qualifiers.
Fixes following Piglit test:
arb_blend_func_extended-output-location
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/linker.cpp | 19 +++
1 file changed,
https://bugs.freedesktop.org/show_bug.cgi?id=91474
--- Comment #2 from Emil Velikov emil.l.veli...@gmail.com ---
Using the device extensions one will be able to enumerate and select the device
they want without the need of X or the DRI_PRIME variable.
Jonny Lamb posted a series that implements
Hello Boyan,
On 21 July 2015 at 16:43, Boyan Ding boyan.j.d...@gmail.com wrote:
This is the second version of my effort to bring dri3 to EGL on X. This
time I took Emil's advice and moved common logic of GLX and EGL into
loader/loader_dri3_helper.[ch]. With this, the dri3 code in libEGL is
https://bugs.freedesktop.org/show_bug.cgi?id=91468
--- Comment #4 from Serge Martin edb+freedesk...@sigluy.net ---
Please note that autotools buils have the svn part in the libname.
I don't knows if it will be deprecated in 3.8 and remove later or if it will be
removed in 3.8.
--
You are
Jason Ekstrand ja...@jlekstrand.net writes:
On Jul 28, 2015 2:43 AM, Francisco Jerez curroje...@riseup.net wrote:
register_coalesce() was considering the exec_size of the MOV
instruction alone to decide whether the register at offset+1 of the
source VGRF was being copied to
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
b/src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c
index
From: Marek Olšák marek.ol...@amd.com
duplicated now
---
src/gallium/drivers/r600/r600_llvm.c | 34 +--
src/gallium/drivers/radeon/radeon_llvm.h | 8 ---
.../drivers/radeon/radeon_setup_tgsi_llvm.c| 68 +-
From: Marek Olšák marek.ol...@amd.com
The patch has a better explanation. Just a summary here:
- The CPU always uploads a whole descriptor array to previously-unused memory.
- CP DMA isn't used.
- No caches need to be flushed.
- All descriptors are always up-to-date in memory even after a hang,
From: Marek Olšák marek.ol...@amd.com
st/nine uses GENERIC slots greater than 60.
---
src/gallium/drivers/radeonsi/si_shader.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader.c
b/src/gallium/drivers/radeonsi/si_shader.c
index
From: Marek Olšák marek.ol...@amd.com
This is for shader-db and should reduce size of shader dumps.
---
src/gallium/drivers/r600/r600_llvm.c | 2 +-
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 23 ---
From: Marek Olšák marek.ol...@amd.com
There are 2 reasons for this:
- LLVM optimization passes can work with floor
- there are patterns to select v_fract from floor anyway
There is no change in the generated code.
---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 20
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_blit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/r600/r600_blit.c
b/src/gallium/drivers/r600/r600_blit.c
index 8e553a8..1c59230 100644
--- a/src/gallium/drivers/r600/r600_blit.c
+++
From: Marek Olšák marek.ol...@amd.com
Broken since:
46b2b3b - radeonsi: don't change pipe_resource in resource_copy_region
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=91444
---
src/gallium/drivers/radeonsi/si_state.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_llvm.c | 152 -
.../drivers/radeon/radeon_setup_tgsi_llvm.c| 150
2 files changed, 150 insertions(+), 152 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
This will help remove some duplicated code from radeon.
---
src/gallium/auxiliary/gallivm/lp_bld_arit.c | 6 +++---
src/gallium/auxiliary/gallivm/lp_bld_intr.c | 12
src/gallium/auxiliary/gallivm/lp_bld_intr.h | 3 ++-
From: Marek Olšák marek.ol...@amd.com
This reverts commit 4db985a5fa9ea985616a726b1770727309502d81.
The grass no longer disappears, which was the reason the commit was reverted.
This might affect tessellation. We'll see.
Totals from affected shaders:
SGPRS: 151672 - 150232 (-0.95 %)
VGPRS:
From: Marek Olšák marek.ol...@amd.com
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 66 ++
1 file changed, 66 insertions(+)
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp
index 4c6e48a..6f00727 100644
---
From: Marek Olšák marek.ol...@amd.com
It only checks fragment textures and ignores other shaders, which makes it
incomplete, and texture are already finalized in update_single_texture.
There are no piglit regressions.
---
src/mesa/state_tracker/st_atom.c | 1 -
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/auxiliary/util/u_debug.c | 8
src/gallium/auxiliary/util/u_debug.h | 6 +++---
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/src/gallium/auxiliary/util/u_debug.c
b/src/gallium/auxiliary/util/u_debug.c
index
From: Marek Olšák marek.ol...@amd.com
This will be used by the new ddebug pipe. I'm including it now to avoid
conflicts with other patches.
---
src/gallium/drivers/r600/evergreen_compute.c | 2 +-
src/gallium/drivers/radeon/r600_pipe_common.h | 5 ++---
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/r600/r600_llvm.c| 1 -
src/gallium/drivers/r600/r600_shader.c | 1 -
src/gallium/drivers/radeon/radeon_llvm.h| 19 ---
src/gallium/drivers/radeon/radeon_setup_tgsi_llvm.c | 14
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeon/r600_pipe_common.c | 1 +
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeonsi/si_shader.c | 20 +++-
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/si_blit.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/drivers/radeonsi/si_blit.c
b/src/gallium/drivers/radeonsi/si_blit.c
index c3591a7..c892623 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++
https://bugs.freedesktop.org/show_bug.cgi?id=91130
--- Comment #2 from Serge Martin edb+freedesk...@sigluy.net ---
Hello
this should be mitigated with the clover: allow the creation of Piglit tests
for the missing CL 1.2 fonction serie available on mesa-dev list.
However, even if the program
Hello Jim,
On 28 July 2015 at 02:57, Bish, Jim jim.b...@intel.com wrote:
From: Jim Bish jim.b...@intel.com
Would you mind splitting this into separate patches ? Adding a few
words in the commit log(s) would be highly preferable.
---
Android.common.mk | 10
https://bugs.freedesktop.org/show_bug.cgi?id=91130
--- Comment #3 from Serge Martin edb+freedesk...@sigluy.net ---
Sorry I mean OpenCL 1.1 MESA 10.7.0-devel. 1.2 is only clain on my local tree
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for
On 07/28/2015 07:33 AM, Emil Velikov wrote:
On 20 July 2015 at 17:12, Brian Paul bri...@vmware.com wrote:
On 07/17/2015 02:14 PM, Emil Velikov wrote:
On 17 July 2015 at 20:22, Brian Paul bri...@vmware.com wrote:
Can you elaborate in the commit message why this is being done or why the
On 17/07/15 21:57, Emil Velikov wrote:
Would anyone be interested is skimming over this trivial series ?
Thomas kindly looked over patches 1,2 and 5. Would anyone care to throw
a quick ack/nack for the rest ?
I'm inclined to push the series unless there are any objections in the
next few days.
On 20 July 2015 at 17:12, Brian Paul bri...@vmware.com wrote:
On 07/17/2015 02:14 PM, Emil Velikov wrote:
On 17 July 2015 at 20:22, Brian Paul bri...@vmware.com wrote:
Can you elaborate in the commit message why this is being done or why the
HAVE_SYS_TYPES_H definition is not needed? That
https://bugs.freedesktop.org/show_bug.cgi?id=91468
--- Comment #3 from Emil Velikov emil.l.veli...@gmail.com ---
Please send the patch to mesa-dev (ideally using git send-email). It'll get
wider exposure there.
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are
On Jul 28, 2015 2:43 AM, Francisco Jerez curroje...@riseup.net wrote:
register_coalesce() was considering the exec_size of the MOV
instruction alone to decide whether the register at offset+1 of the
source VGRF was being copied to inst-dst.reg_offset+1 of the
destination VGRF, which is only a
On 07/28/2015 04:05 AM, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
It only checks fragment textures and ignores other shaders, which makes it
incomplete, and texture are already finalized in update_single_texture.
There are no piglit regressions.
---
Hi Marek,
Yea I don't let git send emails via any mailer.. It would be better if I
could just do pull requests rather than mailing lists if at all
possible? I really seriously hate mailing lists.
In any case, attached is a revised patch with all the feedback included.
Kind Regards,
Edward.
--
This is easily accomplished by moving simd16 3src to GEN9_FEATURES.
Signed-off-by: Ben Widawsky b...@bwidawsk.net
---
src/mesa/drivers/dri/i965/brw_device_info.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_device_info.c
This also helps making my egl/dri3 code easier, so
Acked-by: Boyan Ding boyan.j.d...@gmail.com
2015-07-11 1:49 GMT+08:00 Emil Velikov emil.l.veli...@gmail.com:
Cc: Axel Davy axel.d...@ens.fr
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
configure.ac|
On Tue, Jul 28, 2015 at 12:05:42PM +0200, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
This reverts commit 4db985a5fa9ea985616a726b1770727309502d81.
The grass no longer disappears, which was the reason the commit was reverted.
This might affect tessellation. We'll see.
Hi
https://bugs.freedesktop.org/show_bug.cgi?id=91468
--- Comment #5 from Krzysztof A. Sobiecki sob...@gmail.com ---
(In reply to Serge Martin from comment #4)
Please note that autotools buils have the svn part in the libname.
I don't knows if it will be deprecated in 3.8 and remove later or if it
Iago Toral Quiroga ito...@igalia.com writes:
Link to v1:
http://lists.freedesktop.org/archives/mesa-dev/2015-July/089766.html
Changes after review (Curro)
- Drop the patch that asserted that the reg size should always be 1
- Expand this so that we do not unspill a register if we have
On Tue, Jul 28, 2015 at 12:05:40PM +0200, Marek Olšák wrote:
From: Marek Olšák marek.ol...@amd.com
Reviewed-by: Tom Stellard thomas.stell...@amd.com
---
src/gallium/drivers/r600/r600_llvm.c | 152
-
.../drivers/radeon/radeon_setup_tgsi_llvm.c|
https://bugs.freedesktop.org/show_bug.cgi?id=91468
--- Comment #7 from Emil Velikov emil.l.veli...@gmail.com ---
(In reply to Krzysztof A. Sobiecki from comment #6)
(In reply to Emil Velikov from comment #3)
Please send the patch to mesa-dev (ideally using git send-email). It'll get
wider
https://bugs.freedesktop.org/show_bug.cgi?id=91130
--- Comment #4 from Dennis Schridde devuran...@gmx.net ---
Just to make sure I understand. You say that:
1) Mesa should provide a shared library that actually implements all functions
advertised in the header (which will be fixed in Mesa
https://bugs.freedesktop.org/show_bug.cgi?id=91468
--- Comment #6 from Krzysztof A. Sobiecki sob...@gmail.com ---
(In reply to Emil Velikov from comment #3)
Please send the patch to mesa-dev (ideally using git send-email). It'll get
wider exposure there.
I don't see how It would be appropriate
Change function to get all gl_constants for inspection, this is used
by follow-up patch.
v2: rebase, update function documentation
Signed-off-by: Tapani Pälli tapani.pa...@intel.com
---
src/glsl/linker.cpp | 23 +++
1 file changed, 15 insertions(+), 8 deletions(-)
diff
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