Re: [Mesa-dev] [PATCH] anv: fix building on i686 with -mcpu=generic

Reviewed-by: Jason Ekstrand On Apr 16, 2016 12:50 PM, "Laurent Carlier" wrote: > mcpu=generic doesn't enable sse2, and anvil definitly needs it > --- > src/intel/vulkan/Makefile.am | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff

[Mesa-dev] [PATCH v2 1/2] gallium/dri2: Factor out DRI2 to PIPE_FORMAT conversion

From: Nicolas Dufresne This code is already duplicated twice and will be useful again. This will also help when adding formats. Signed-off-by: Nicolas Dufresne --- src/gallium/state_trackers/dri/dri2.c | 61

[Mesa-dev] [PATCH v2 2/2] gallium/dri2: Fix RGB565 EGLImage creation

From: Nicolas Dufresne When creating egl images we do a bytes to pixel conversion by deviding by 4 regardless of the pixel format. This does not work for RGB565. In this patch, we avoid useless conversion and use proper API when the conversion cannot be avoided.

[Mesa-dev] [PATCH v2 0/2] Fix Gallium RGB565 image support

From: Nicolas Dufresne Sorry for the long delay breaking down this patch. I have now rebased on top recent mesa tree. First patch creates a new function to convert DRI2 format into PIPE format (to avoid more copy paste). The second fixes the wrong pitch to stride

Re: [Mesa-dev] [PATCH v2] xlib: do not cache return value of glXChooseVisual/glXGetVisualFromFBConfig

On 15 April 2016 at 07:19, Alejandro Piñeiro wrote: > On 14/04/16 19:23, Emil Velikov wrote: >> On 14 April 2016 at 08:09, Alejandro Piñeiro wrote: >>> For next time, on the cases were minor changes are suggested, but a RB >>> is granted in any case,

Re: [Mesa-dev] [PATCH 1/7] util: add MAYBE_UNUSED for config dependent variables

On 16 April 2016 at 02:00, Grazvydas Ignotas wrote: > This is mostly for variables that are only used in asserts and cause > unused-but-set-variable warnings in release builds. Could just use > UNUSED directly, but MAYBE_UNUSED should be less confusing and is > similar to what

Re: [Mesa-dev] [PATCH 00/13] i965/compiler: Use ISL for image_load_store format

On Sat, Apr 16, 2016 at 4:40 PM, Emil Velikov wrote: > On 16 April 2016 at 20:45, Jason Ekstrand wrote: > > This little series switches our back-end compiler to use libisl for the > > surface format introspection it needs for doing

[Mesa-dev] [PATCH v2 07/12] radeonsi: Add CE synchronization.

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_pipe.h | 1 + src/gallium/drivers/radeonsi/si_state_draw.c | 24 2 files changed, 25 insertions(+) diff --git

[Mesa-dev] [PATCH v2 02/12] winsys/amdgpu: split IB data into a new structure in preparation for CE

From: Marek Olšák Reviewed-by: Bas Nieuwenhuizen --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.c | 5 --- src/gallium/winsys/amdgpu/drm/amdgpu_bo.h | 6 +++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 68 +++

[Mesa-dev] [PATCH v2 10/12] radeonsi: Replace list_dirty with a mask.

We can then upload only the dirty ones with the constant engine. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 37 --- src/gallium/drivers/radeonsi/si_state.h | 9 +-- 2 files changed, 29

[Mesa-dev] [PATCH v2 04/12] winsys/amdgpu: Enlarge const IB size.

Necessary to prevent performance regressions due to extra flushing. Probably should enlarge it even further when also updating uniforms through the CE, but this seems large enough for now. v2: Add preamble IB. Signed-off-by: Bas Nieuwenhuizen ---

[Mesa-dev] [PATCH v2 08/12] radeonsi: Allocate chunks of CE ram.

v2: Use 32 byte alignment. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 30 +++ src/gallium/drivers/radeonsi/si_state.h | 3 +++ 2 files changed, 24 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH v2 03/12] winsys/amdgpu: Add support for const IB.

From: Marek Olšák v2: Use the correct IB to update request (Bas Nieuwenhuizen) v3: Add preamble IB. (Bas Nieuwenhuizen) --- src/gallium/drivers/radeon/radeon_winsys.h | 30 ++ src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 88 --

[Mesa-dev] [PATCH v2 09/12] radeonsi: Add CE uploader.

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_descriptors.c | 23 +++ src/gallium/drivers/radeonsi/si_pipe.c| 11 +++ src/gallium/drivers/radeonsi/si_pipe.h

[Mesa-dev] [PATCH v2 06/12] radeonsi: Add CE packet definitions.

Signed-off-by: Bas Nieuwenhuizen Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/sid.h | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/sid.h b/src/gallium/drivers/radeonsi/sid.h index

[Mesa-dev] [PATCH v2 01/12] gallium/radeon: move ring_type into winsyses

From: Marek Olšák Not used by drivers. Reviewed-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeon/radeon_winsys.h| 1 - src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 8 src/gallium/winsys/amdgpu/drm/amdgpu_cs.h | 1 +

[Mesa-dev] [PATCH v2 05/12] radeonsi: Create CE IB.

Based on work by Marek Olšák. v2: Add preamble IB. Leaves the load packet in the space calculation as the radeon winsys might not be able to support a premable. The added space calculation may look expensive, but is converted to a constant with (at least) -O2 and -O3. Signed-off-by: Bas

[Mesa-dev] [PATCH v2 12/12] radeonsi: Use CE for all descriptors.

v2: Load previous list for new CS instead of re-emitting all descriptors. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/drivers/radeonsi/si_descriptors.c | 70 +++ 1 file changed, 60 insertions(+), 10 deletions(-) diff --git

[Mesa-dev] [PATCH v2 11/12] gallium/util: Add u_bit_scan_consecutive_range64.

For use by radeonsi. v2: Make sure that it works for all 64 bits set. Signed-off-by: Bas Nieuwenhuizen --- src/gallium/auxiliary/util/u_math.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/auxiliary/util/u_math.h

[Mesa-dev] [PATCH v2 00/12] Use the constant engine in radeonsi

For this v2 I did the following changes: - Use Nicolai's proposed dirty mask structure. - Use load packets to reinitialize CE ram. - Use a preamble IB for reinitializing CE ram. I've made the preamble IB optional in radeonsi, as the radeon kernel driver does not support it as far as I

Re: [Mesa-dev] [PATCH 00/13] i965/compiler: Use ISL for image_load_store format

On 16 April 2016 at 20:45, Jason Ekstrand wrote: > This little series switches our back-end compiler to use libisl for the > surface format introspection it needs for doing image_load_store shader > work-arounds. Format introspection is the one place where thet back-end >

Re: [Mesa-dev] [PATCH 3/6] gallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_*

On 16 April 2016 at 23:15, Roland Scheidegger wrote: > Am 16.04.2016 um 14:50 schrieb Marek Olšák: >> From: Marek Olšák >> >> Use PIPE_SWIZZLE_* everywhere. >> Use X/Y/Z/W/0/1 instead of RED, GREEN, BLUE, ALPHA, ZERO, ONE. >> The new enum is called

Re: [Mesa-dev] [PATCH 1/6] gallium: use enums in p_defines.h

On 16 April 2016 at 22:04, Marek Olšák wrote: > On Sat, Apr 16, 2016 at 9:40 PM, Rob Clark wrote: >> On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote: >>> From: Marek Olšák >>> >>> and remove number assignments

Re: [Mesa-dev] [PATCH 4/6] gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*

Am 16.04.2016 um 14:50 schrieb Marek Olšák: > From: Marek Olšák > > we should use MESA_SHADER_* everywhere, but we're not ready for that yet > --- I think the idea initially was that tgsi is essentially self-contained: you can parse the token stream without any "external"

Re: [Mesa-dev] [PATCH 3/6] gallium: merge PIPE_SWIZZLE_* and UTIL_FORMAT_SWIZZLE_*

Am 16.04.2016 um 14:50 schrieb Marek Olšák: > From: Marek Olšák > > Use PIPE_SWIZZLE_* everywhere. > Use X/Y/Z/W/0/1 instead of RED, GREEN, BLUE, ALPHA, ZERO, ONE. > The new enum is called pipe_swizzle. Using PIPE_SWIZZLE insteads sounds reasonable. Not sure though how I

Re: [Mesa-dev] [PATCH 2/6] gallium: use enums in p_shader_tokens.h

Reviewed-by: Roland Scheidegger Am 16.04.2016 um 14:50 schrieb Marek Olšák: > From: Marek Olšák > > --- > src/gallium/include/pipe/p_shader_tokens.h | 303 > - > 1 file changed, 164 insertions(+), 139 deletions(-) > > diff

Re: [Mesa-dev] [PATCH 1/6] gallium: use enums in p_defines.h

Makes me wonder why we didn't use enums in the first place. But I can't think of any disadvantages. Reviewed-by: Roland Scheidegger Am 16.04.2016 um 14:50 schrieb Marek Olšák: > From: Marek Olšák > > and remove number assignments which are consecutive

[Mesa-dev] [Bug 92850] Segfault loading War Thunder

https://bugs.freedesktop.org/show_bug.cgi?id=92850 higu...@gmx.net changed: What|Removed |Added CC||higu...@gmx.net -- You are receiving

Re: [Mesa-dev] [PATCH 1/6] gallium: use enums in p_defines.h

On Sat, Apr 16, 2016 at 5:49 PM, Rob Clark wrote: > On Sat, Apr 16, 2016 at 5:04 PM, Marek Olšák wrote: >> On Sat, Apr 16, 2016 at 9:40 PM, Rob Clark wrote: >>> On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote:

Re: [Mesa-dev] [PATCH 1/6] gallium: use enums in p_defines.h

On Sat, Apr 16, 2016 at 5:04 PM, Marek Olšák wrote: > On Sat, Apr 16, 2016 at 9:40 PM, Rob Clark wrote: >> On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote: >>> From: Marek Olšák >>> >>> and remove number

[Mesa-dev] [PATCH] gallivm: don't use vector selects with llvm 3.7

From: Roland Scheidegger llvm 3.7 sometimes simply miscompiles vector selects. See https://bugs.freedesktop.org/show_bug.cgi?id=94972 --- src/gallium/auxiliary/gallivm/lp_bld_logic.c | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [Bug 94972] blend failures on llvmpipe with llvm 3.7 due to vector selects

https://bugs.freedesktop.org/show_bug.cgi?id=94972 Bug ID: 94972 Summary: blend failures on llvmpipe with llvm 3.7 due to vector selects Product: Mesa Version: git Hardware: All OS: All Status:

Re: [Mesa-dev] [PATCH 4/6] gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*

On Sat, Apr 16, 2016 at 6:54 PM, Ilia Mirkin wrote: > On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote: >> From: Marek Olšák >> >> we should use MESA_SHADER_* everywhere, but we're not ready for that yet > > H not sure if

Re: [Mesa-dev] [PATCH 1/6] gallium: use enums in p_defines.h

On Sat, Apr 16, 2016 at 9:40 PM, Rob Clark wrote: > On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote: >> From: Marek Olšák >> >> and remove number assignments which are consecutive >> --- >> src/gallium/include/pipe/p_defines.h |

Re: [Mesa-dev] [PATCH 2/2] radeonsi: Implement ddx/ddy on VI using ds_bpermute

On Sat, Apr 16, 2016 at 8:17 PM, Nicolai Hähnle wrote: > On 16.04.2016 05:20, Marek Olšák wrote: >> >> On Sat, Apr 16, 2016 at 8:04 AM, Michel Dänzer wrote: >>> >>> On 16.04.2016 14:51, Michel Dänzer wrote: On 16.04.2016 11:39, Tom Stellard

[Mesa-dev] [PATCH] anv: fix build without Wayland platform

--- src/intel/vulkan/Makefile.am | 9 + src/intel/vulkan/anv_private.h | 3 --- 2 files changed, 5 insertions(+), 7 deletions(-) diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am index cba6671..a201bed 100644 --- a/src/intel/vulkan/Makefile.am +++

[Mesa-dev] [PATCH 14/13] i965/surface_state: Use libisl functions for image format lowering

This lets us delete some redundant code and keep all of the image_load_store format lowering logic in one place: libisl. --- src/mesa/drivers/dri/i965/brw_context.h | 2 - src/mesa/drivers/dri/i965/brw_surface_formats.c | 109 ---

[Mesa-dev] [PATCH] anv: fix building on i686 with -mcpu=generic

mcpu=generic doesn't enable sse2, and anvil definitly needs it --- src/intel/vulkan/Makefile.am | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/Makefile.am b/src/intel/vulkan/Makefile.am index cba6671..a84be72 100644 --- a/src/intel/vulkan/Makefile.am +++

[Mesa-dev] [PATCH 09/13] isl/format: Add a get_num_channels helper

--- src/intel/isl/isl.h| 2 ++ src/intel/isl/isl_format.c | 15 +++ 2 files changed, 17 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index c84e685..bef2592 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -863,6 +863,8 @@

[Mesa-dev] [PATCH 05/13] isl: Add a helper for determining when a typed load/store can be used

--- src/intel/isl/isl.h | 7 +++ src/intel/isl/isl_storage_image.c | 10 ++ 2 files changed, 17 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index 2982bad..c6fe318 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -912,6 +912,13 @@

[Mesa-dev] [PATCH 11/13] i965/fs_surface_builder: Explicitly handle FORMAT_NONE in num_image_coordinates

Previously, we were relying on has_matching_typed_format returning true for MESA_FORMAT_NONE which, in turn, relied on _mesa_get_format_bytes returning 1 for MESA_FORMAT_NONE. When we switch to ISL, this behaviour will no longer be something we can rely on. ---

[Mesa-dev] [PATCH 10/13] i965/fs_surface_builder: Take a GL format enum instead of mesa_format

--- src/mesa/drivers/dri/i965/brw_fs_nir.cpp | 8 +++- src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp | 7 +-- src/mesa/drivers/dri/i965/brw_fs_surface_builder.h | 4 ++-- 3 files changed, 10 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH 02/13] isl: Add an ISL_RESTRICT #define for use in isl.h

C++ doesn't define the "restrict" keyword so g++ barfs when it sees isl.h. Having our own define lets us define it to be a no-op for C++. --- src/intel/isl/isl.h | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index

[Mesa-dev] [PATCH 06/13] anv/image: Use the has_matching_typed_storage_image_format helper from isl

--- src/intel/vulkan/anv_image.c | 15 +++ 1 file changed, 3 insertions(+), 12 deletions(-) diff --git a/src/intel/vulkan/anv_image.c b/src/intel/vulkan/anv_image.c index 7236b81..03a8cb8 100644 --- a/src/intel/vulkan/anv_image.c +++ b/src/intel/vulkan/anv_image.c @@ -424,16 +424,6

[Mesa-dev] [PATCH 07/13] isl/format: Break the guts of has_[us]int_channel into a helper

--- src/intel/isl/isl_format.c | 34 -- 1 file changed, 16 insertions(+), 18 deletions(-) diff --git a/src/intel/isl/isl_format.c b/src/intel/isl/isl_format.c index 32bd701..b0450d9 100644 --- a/src/intel/isl/isl_format.c +++ b/src/intel/isl/isl_format.c @@ -25,32

[Mesa-dev] [PATCH 12/13] i965/fs_surface_builder: Add a helper for converting GL to ISL formats

--- .../drivers/dri/i965/brw_fs_surface_builder.cpp| 55 ++ 1 file changed, 55 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp index 0932336..23ad511 100644 ---

[Mesa-dev] [PATCH 13/13] i965/fs_surface_builder: Use isl instead of mesa for format info

--- .../drivers/dri/i965/brw_fs_surface_builder.cpp| 118 + 1 file changed, 52 insertions(+), 66 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp b/src/mesa/drivers/dri/i965/brw_fs_surface_builder.cpp index 23ad511..fc1fc13 100644 ---

[Mesa-dev] [PATCH 08/13] isl/format: Add more isl_format_has_type_channel functions

--- src/intel/isl/isl.h| 23 +++ src/intel/isl/isl_format.c | 24 2 files changed, 43 insertions(+), 4 deletions(-) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index c6fe318..c84e685 100644 --- a/src/intel/isl/isl.h +++

[Mesa-dev] [PATCH 04/13] isl: Take a devinfo in lower_storage_image_format instead of an isl_device

We want to call this function from the shader compiler and having a full isl_device available at that point isn't practical. --- src/intel/isl/isl.h | 2 +- src/intel/isl/isl_storage_image.c | 30 +++--- src/intel/isl/isl_surface_state.c | 3 ++-

[Mesa-dev] [PATCH 01/13] i965: Add a dependency on libisl

--- configure.ac | 3 ++- src/Makefile.am | 9 +++-- src/intel/Makefile.am | 4 src/mesa/drivers/dri/i965/Makefile.am | 7 ++- 4 files changed, 15 insertions(+), 8 deletions(-) diff --git a/configure.ac b/configure.ac

[Mesa-dev] [PATCH 03/13] isl: Don't use designated initializers in the header

C++ doesn't support designated initializers and g++ in particular doesn't handle them when the struct gets complicated, i.e. has a union. --- src/intel/isl/isl.h | 32 1 file changed, 20 insertions(+), 12 deletions(-) diff --git a/src/intel/isl/isl.h

[Mesa-dev] [PATCH 00/13] i965/compiler: Use ISL for image_load_store format

This little series switches our back-end compiler to use libisl for the surface format introspection it needs for doing image_load_store shader work-arounds. Format introspection is the one place where thet back-end compilers still have a dependency on libmesa. Once this dependency is removed,

Re: [Mesa-dev] [PATCH 1/6] gallium: use enums in p_defines.h

On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote: > From: Marek Olšák > > and remove number assignments which are consecutive > --- > src/gallium/include/pipe/p_defines.h | 378 > +++ > 1 file changed, 205 insertions(+),

[Mesa-dev] [PATCH 2/2] meta: initialize values to avoid random behaviour on error path

if brw_meta_stencil_blit() errored at wrong place 'target' would be uninitialized and cause random behaviour on leaving the funtion. Signed-off-by: Juha-Pekka Heikkila --- src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 2 +- 1 file changed, 1 insertion(+), 1

[Mesa-dev] [PATCH 1/2] meta: Avoid random memory access on error

Initialize drawFb to NULL in _mesa_meta_CopyImageSubData_uncompressed() if getting readFb fails uninitialized drawFb will cause randomness on cleanup. Signed-off-by: Juha-Pekka Heikkila --- src/mesa/drivers/common/meta_copy_image.c | 2 +- 1 file changed, 1

[Mesa-dev] [PATCH 0/2] two super simple patches

These are just fixes for error paths. Juha-Pekka Heikkila (2): meta: Avoid random memory access on error meta: initialize values to avoid random behaviour on error path src/mesa/drivers/common/meta_copy_image.c | 2 +- src/mesa/drivers/dri/i965/brw_meta_stencil_blit.c | 2 +- 2

[Mesa-dev] i965: The future of blorp

All, With Topi's gen8/9 blorp patches on the list, I wanted to start a brief discussion about the future of blorp in the hopes of us all being on the same page and not stepping on each other's toes. I think everyone is now agreed that blorp is the future and GL meta should die. As we continue to

Re: [Mesa-dev] [PATCH 2/2] radeonsi: Implement ddx/ddy on VI using ds_bpermute

On 16.04.2016 05:20, Marek Olšák wrote: On Sat, Apr 16, 2016 at 8:04 AM, Michel Dänzer wrote: On 16.04.2016 14:51, Michel Dänzer wrote: On 16.04.2016 11:39, Tom Stellard wrote: The ds_bpermute instruction allows threads to transfer data directly to or from the vgprs of

[Mesa-dev] [PATCH] radeonsi: implement TGSI_SEMANTIC_HELPER_INVOCATION

From: Nicolai Hähnle --- We will soon claim GLES 3.1 support, which requires gl_HelperInvocation, so now is the time to do this. This depends on LLVM support: http://reviews.llvm.org/D19191 docs/GL3.txt | 2 +-

Re: [Mesa-dev] [PATCH 4/6] gallium: use PIPE_SHADER_* everywhere, remove TGSI_PROCESSOR_*

On Sat, Apr 16, 2016 at 8:50 AM, Marek Olšák wrote: > From: Marek Olšák > > we should use MESA_SHADER_* everywhere, but we're not ready for that yet H not sure if this is right. I thought the idea is that TGSI should be its own self-contained

Re: [Mesa-dev] [PATCH 2/2] radeonsi: Implement ddx/ddy on VI using ds_bpermute

On Sat, Apr 16, 2016 at 10:36 AM, Marek Olšák wrote: > On Sat, Apr 16, 2016 at 3:28 PM, Roland Scheidegger > wrote: >> Am 16.04.2016 um 15:19 schrieb eocallag...@alterapraxis.com: >>> On 2016-04-16 20:20, Marek Olšák wrote: On Sat, Apr 16, 2016 at 8:04

Re: [Mesa-dev] [PATCH 2/2] radeonsi: Implement ddx/ddy on VI using ds_bpermute

On Sat, Apr 16, 2016 at 3:28 PM, Roland Scheidegger wrote: > Am 16.04.2016 um 15:19 schrieb eocallag...@alterapraxis.com: >> On 2016-04-16 20:20, Marek Olšák wrote: >>> On Sat, Apr 16, 2016 at 8:04 AM, Michel Dänzer >>> wrote: On 16.04.2016 14:51,

Re: [Mesa-dev] [PATCH 2/2] radeonsi: Implement ddx/ddy on VI using ds_bpermute

Am 16.04.2016 um 15:19 schrieb eocallag...@alterapraxis.com: > On 2016-04-16 20:20, Marek Olšák wrote: >> On Sat, Apr 16, 2016 at 8:04 AM, Michel Dänzer >> wrote: >>> On 16.04.2016 14:51, Michel Dänzer wrote: On 16.04.2016 11:39, Tom Stellard wrote: > The ds_bpermute

[Mesa-dev] [PATCH 15/40] i965/blorp: Add support for sampling 3D textures

This patch adds additional MOV instruction for all blorp programs that use SHADER_OPCODE_TXF. Alternative is to augment blorp program key to tell if z-coordinate is needed, add condition to the blorp blit compiler and to produce a variant with and without the MOV. This seems a little overkill.

[Mesa-dev] [PATCH 32/40] i965/blorp/gen7: Prepare blorp being the very first renderer

I noticed using one synthetic benchmark a sequence where hiz depth operations are run first followed by a color buffer clear. In such case there is a difference between blorp and meta clear where meta configures L3 but blorp doesn't. I didn't see any problems in practise without the configure but

[Mesa-dev] [PATCH 23/40] i965: Declare input to mcs alignment calculation constant

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 29/40] i965/meta: Move check for srgb into is_color_fast_clear_compatible()

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 34 + src/mesa/drivers/dri/i965/brw_meta_util.h | 2 +- 2 files changed, 19 insertions(+), 17 deletions(-) diff --git

[Mesa-dev] [PATCH 12/40] i965: Allow texture surface state setup to be used by blorp

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 ++- src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 +-- src/mesa/drivers/dri/i965/gen8_surface_state.c| 7

[Mesa-dev] [PATCH 33/40] i965/blorp: Prepare to switch from compute pipeline

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 618949c..5f0083c 100644 ---

[Mesa-dev] [PATCH 35/40] i965/blorp: Do not tricker urb re-configuration unnecessarily

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 4 +++- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 ++ 2 files changed, 5 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp

[Mesa-dev] [PATCH 34/40] i965/blorp: Skip re-emitting urb config whenever possible

Otherwise clearing with blorp will regress performance in some synthetic test cases. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 14 ++ 1 file changed, 14 insertions(+) diff --git

[Mesa-dev] [PATCH 37/40] i965/blorp: Leave new batch signaling to batch buffer logic

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp b/src/mesa/drivers/dri/i965/brw_blorp.cpp index 1d3b3e2..04a2a74 100644 ---

[Mesa-dev] [PATCH 38/40] i965/blorp: Use more fine grained state trashing than new context

which results into, for example, urb configuration to be re-emitted even though it is not needed. There are a few emitters that rely solely on BRW_NEW_CONTEXT in driver state. These can be addressed using GL-state instead (similarly to gen8_hiz_exec()): gen6_sf_state: _NEW_PROGRAM

[Mesa-dev] [PATCH 22/40] i965/blorp: Switch the order of render and texture targets

On gen8 color resolving won't work anymore if the target isn't the first entry in the binding table. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h | 2 +- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 4 2 files changed,

[Mesa-dev] [PATCH 30/40] i965/blorp: Re-introduce clear programs

This partially reverts 2f28a0dc23165123cf1e8b5942acad37878edd8a Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/Makefile.sources| 1 + src/mesa/drivers/dri/i965/brw_blorp.h | 8 + src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 +-

[Mesa-dev] [PATCH 16/40] i965/blorp: Add check for supported sample numbers

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 10 ++ src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 +++-- 2 files changed, 17 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 13/40] i965/blorp: Pipeline upload support for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/Makefile.sources | 1 + src/mesa/drivers/dri/i965/brw_blorp.h | 3 + src/mesa/drivers/dri/i965/gen8_blorp.cpp | 694 + 3 files changed, 698 insertions(+) create mode

[Mesa-dev] [PATCH 18/40] i965/blorp: Enable blits on gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 6 +- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 8 +--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 3 +-- 3 files changed, 11 insertions(+), 6 deletions(-) diff

[Mesa-dev] [PATCH 26/40] i965/meta: Expose non-fast clear rectangle calculation

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 26 +++-- src/mesa/drivers/dri/i965/brw_meta_util.h | 5 + 2 files changed, 21 insertions(+), 10 deletions(-) diff --git

[Mesa-dev] [PATCH 21/40] i965/blorp: Reduce scope for generator and its inputs

Generator is only needed for getting the assembly. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp| 23 ++- src/mesa/drivers/dri/i965/brw_blorp_blit_eu.cpp | 22 --

[Mesa-dev] [PATCH 01/40] i965/gen9: Use correct size for DS_STATE

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_ds_state.c | 22 ++ 1 file changed, 18 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen8_ds_state.c b/src/mesa/drivers/dri/i965/gen8_ds_state.c index

[Mesa-dev] [PATCH 25/40] i965/meta: Expose resolve clear rectangle calculation

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 16 +--- src/mesa/drivers/dri/i965/brw_meta_util.h | 6 ++ 2 files changed, 15 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH 20/40] i965/blorp: Add support for disabling color blending

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 4 src/mesa/drivers/dri/i965/brw_blorp.h| 1 + src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 + src/mesa/drivers/dri/i965/gen8_blorp.cpp | 9 + 4 files changed, 19

[Mesa-dev] [PATCH 19/40] i965/blorp: Add support for setting fast clear operation

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 1 + src/mesa/drivers/dri/i965/brw_blorp.h| 1 + src/mesa/drivers/dri/i965/gen7_blorp.cpp | 2 ++ src/mesa/drivers/dri/i965/gen8_blorp.cpp | 1 + 4 files changed, 5 insertions(+) diff

[Mesa-dev] [PATCH 28/40] i965/meta: Expose check for fast clear compatibility

Also add the additional render format check to the same utility. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 40 - src/mesa/drivers/dri/i965/brw_meta_util.h | 5 2 files changed, 25

[Mesa-dev] [PATCH 31/40] i965/blorp: Skip uploading state/options not needed for clears

In case there is no source it means the program does a simple clear or a resolve. In such case there is no need to program sampling state or enable pixel kill in fragment shader. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 13

[Mesa-dev] [PATCH 17/40] i965/blorp: Prepare stencil sampling for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++- src/mesa/drivers/dri/i965/brw_blorp_blit.cpp | 4 ++-- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.cpp

[Mesa-dev] [PATCH 39/40] i965/blorp: Enable for normal color clears

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_clear.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_clear.c b/src/mesa/drivers/dri/i965/brw_clear.c index 841ba5d..d57b677 100644 ---

[Mesa-dev] [PATCH 24/40] i965/meta: Expose fast clear rectangle calculation

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 44 ++--- src/mesa/drivers/dri/i965/brw_meta_util.h | 8 + 2 files changed, 33 insertions(+), 19 deletions(-) diff --git

[Mesa-dev] [PATCH 08/40] i965/blorp/gen7: Expose state setup applicable to gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.h| 39 src/mesa/drivers/dri/i965/gen7_blorp.cpp | 22 +- 2 files changed, 50 insertions(+), 11 deletions(-) diff --git

[Mesa-dev] [PATCH 36/40] i965/blorp: Reconfigure base state address only if needed

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.cpp | 3 ++- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 5 + src/mesa/drivers/dri/i965/gen8_blorp.cpp | 4 +++- 3 files changed, 10 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 27/40] i965/meta: Expose fast clear value setup

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_meta_fast_clear.c | 10 +- src/mesa/drivers/dri/i965/brw_meta_util.h | 5 + 2 files changed, 10 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 40/40] i965/blorp: Enable for buffer resolves

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94181 Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 06/40] i965/blorp/gen7: Prepare re-using for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_blorp.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen7_blorp.cpp b/src/mesa/drivers/dri/i965/gen7_blorp.cpp index eae1e30..4debeb3 100644

[Mesa-dev] [PATCH 05/40] i965/blorp: Let compiler calculate the vertex buffer size

Currently the size is sizeof(float) times too large. One reserves GEN6_BLORP_VBO_SIZE many floats whereas GEN6_BLORP_VBO_SIZE stands for the size of vertex buffer in bytes. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 31

[Mesa-dev] [PATCH 07/40] i965/blorp: Use 8k chunk size for urb allocation

Otherwise switch from blorp to compute failes. Note that this now follows the normal i965 upload logic found in gen7_upload_urb(). Effectively vs_size changes from 2 to 1 and vs_start from 2 to 4. Signed-off-by: Topi Pohjolainen ---

[Mesa-dev] [PATCH 02/40] i965/gen8: Document inst buffer size modify enabling bit

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen8_misc_state.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/gen8_misc_state.c b/src/mesa/drivers/dri/i965/gen8_misc_state.c index a46b252..c0014e5

[Mesa-dev] [PATCH 09/40] i965/blorp/gen6: Prepare vertex buffer setup logic for gen8

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.cpp | 30 ++ 1 file changed, 22 insertions(+), 8 deletions(-) diff --git a/src/mesa/drivers/dri/i965/gen6_blorp.cpp b/src/mesa/drivers/dri/i965/gen6_blorp.cpp index

[Mesa-dev] [PATCH 03/40] i965/gen8: Expose surface state helpers

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_state.h | 15 src/mesa/drivers/dri/i965/gen8_surface_state.c | 51 +- 2 files changed, 41 insertions(+), 25 deletions(-) diff --git

[Mesa-dev] i965: Support for gen8/9 blorp

This series adds blorp pipeline upload support for gen8 and gen9, switches over to blorp blits (except for 2X and 16X msaa which don't have support in blorp yet) and finally re-introduces blorp clears for gen6-9. This makes it possible to close bug 94181 preventing single sample compression

  1   2   >