[Mesa-dev] [PATCH] glShaderSource must not change compile status.

OpenGL 4.5 Core Profile section 7.1, in the documentation for CompileShader, says: "Changing the source code of a shader object with ShaderSource does not change its compile status or the compiled shader code." (I haven't checked older versions of the spec.) According to Karol Herbst, the game

[Mesa-dev] [PATCH] Test that glShaderSource does not change compile status.

OpenGL 4.5 Core Profile section 7.1, in the documentation for CompileShader, says: "Changing the source code of a shader object with ShaderSource does not change its compile status or the compiled shader code." (I haven't checked older versions of the spec.) This test creates a shader, compiles

Re: [Mesa-dev] [PATCH 5/6] nir: Add a helper for figuring out what channels of an SSA def are read

On Sat, Apr 23, 2016 at 04:39:28PM -0700, Kenneth Graunke wrote: > From: Jason Ekstrand > > Reviewed-by: Kenneth Graunke Reviewed-by: Topi Pohjolainen ___ mesa-dev mailing

[Mesa-dev] [PATCH 6/7] tgsi/exec: misc fixes for compute shaders.

From: Dave Airlie We want to use the SysSemanticToIndex to tell if we've seen the semantics at all. Also add semantic swizzle support. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 5 - 1 file changed, 4 insertions(+), 1

Re: [Mesa-dev] [PATCH 3/6] i965/fs: Properly report regs_written from SAMPLEINFO

On Sat, Apr 23, 2016 at 04:39:26PM -0700, Kenneth Graunke wrote: > From: Jason Ekstrand > > Reviewed-by: Kenneth Graunke Reviewed-by: Topi Pohjolainen ___ mesa-dev mailing

[Mesa-dev] [PATCH 3/7] tgsi/exec: implement load/store/atomic on MEMORY.

From: Dave Airlie This implements basic load/store/atomic ops on MEMORY types for compute shaders. TODO: finish off atomic ops. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 109 -

[Mesa-dev] [PATCH 4/7] tgsi/exec: make inputs/outputs optional for compute shaders.

From: Dave Airlie compute shaders don't need input/outputs so don't bother allocating memory for these. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 43 +++--- 1 file changed, 24 insertions(+), 19

[Mesa-dev] [PATCH 5/7] tgsi/exec: implement restartable machine.

From: Dave Airlie This lets us restart the machine at a PC value, and exits the machine when we hit a barrier. Compute shaders will then execute all the threads up to the barrier, then restart the machines after the barrier once all are done. Signed-off-by: Dave Airlie

[Mesa-dev] [rfc] softpipe compute shader support

This isn't complete yet, but it passes all the piglit tests, the main missing bit is completing the atomic operations. This is based on some tgsi fixes I've sent out previously, The full branch is also here: https://cgit.freedesktop.org/~airlied/mesa/log/?h=softpipe-compute I just wanted to

[Mesa-dev] [PATCH 1/7] tgsi: accept a starting PC value for exec machine.

From: Dave Airlie This will be used later to restart barriered execution threads in compute, for now we just want to change the API. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/draw/draw_gs.c | 2 +-

[Mesa-dev] [PATCH 7/7] softpipe: add support for compute shaders.

From: Dave Airlie This enables ARB_compute_shader on softpipe. I've only tested this with piglit so far, and I hopefully plan on integrating it with my vulkan work. I'll get to testing it with deqp more later. The basic premise is to create up to 1024 restartable TGSI

[Mesa-dev] [PATCH 2/7] tgsi/exec: split out setting up masks to separate function

From: Dave Airlie This is just a cleanup that will make later changes easier to make. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/tgsi/tgsi_exec.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH 5/6] nir/opt_algebraic: Fix some expressions with ambiguous bit sizes

--- src/compiler/nir/nir_opt_algebraic.py | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index fc439f0..2ad1c70 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++

[Mesa-dev] [PATCH 6/6] nir/algebraic: Add a bit-size validator

This commit adds a validator that ensures that all expressions passed through nir_algebraic are 100% non-ambiguous as far as bit-sizes are concerned. This way it's a compile-time error rather than a hard-to-trace C exception some time later. --- src/compiler/nir/nir_algebraic.py | 270

[Mesa-dev] [PATCH 1/6] nir/algebraic: Do better error reporting of bad expressions

Previously, if an exception was encountered anywhere, nir_algebraic would just die in a fire with no indication whatsoever as to where the actual bug is. This commit makes it print out the particular search-and-replace expression that is causing problems along with the exception. Also, it will

[Mesa-dev] [PATCH 4/6] nir/search: Respect the bit_size parameter on nir_search_value

--- src/compiler/nir/nir_opt_algebraic.py | 5 - src/compiler/nir/nir_search.c | 14 ++ 2 files changed, 18 insertions(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index fa7d7c7..fc439f0 100644 ---

[Mesa-dev] [PATCH 2/6] nir/algebraic: Use "uint" instead of "unsigned" for uint types

This is consistent with the rename done for the rest of NIR. Currently, "bool" is the only type specifier used in nir_opt_algebraic.py so this is really a no-op. --- src/compiler/nir/nir_algebraic.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 3/6] nir/algebraic: Add a mechanism for specifying the bit size of a value

--- src/compiler/nir/nir_algebraic.py | 29 + src/compiler/nir/nir_opt_algebraic.py | 4 src/compiler/nir/nir_search.h | 2 ++ 3 files changed, 31 insertions(+), 4 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py

[Mesa-dev] [PATCH 0/6] nir/algebraic: bit size improvements

This little series makes some bit size improvements to nir_algebraic. In particular, it adds a mechanism that allows you to specify a specific bit size for any part of a search or replace expression to get rid of ambiguity. The last patch is probably the most important and also the trickiest.

Re: [Mesa-dev] [PATCH 4/6] i965/fs: Use inst->regs_written for rlen for texture instructions

On Sat, Apr 23, 2016 at 04:39:27PM -0700, Kenneth Graunke wrote: > From: Jason Ekstrand > > Reviewed-by: Kenneth Graunke Reviewed-by: Topi Pohjolainen ___ mesa-dev mailing

[Mesa-dev] [PATCH] tgsi/exec: fix system value handling.

From: Dave Airlie a) SysSemanticToIndex needs to be indexed with the semantic name not the decl->Declaration.Semantic. b) doing this in run is too late, as the mappings are all setup prior to run in the execs. This fixes point-vertex-id gl_vertex_id gl_instanceid

Re: [Mesa-dev] [PATCH] glsl: fix lowering outputs for early/nested returns

Hi Timothy, Thanks for your comments, you're absolutely right about not wanting to visit other functions. I will modify the visitor appropriately and submit a couple of piglit tests. Regards, Lars Hamre On Mon, Apr 25, 2016 at 8:20 PM, Timothy Arceri wrote: > Hi

[Mesa-dev] [Bug 95110] Some Ogre 2.1 demos doesn't render properly

https://bugs.freedesktop.org/show_bug.cgi?id=95110 MWATTT changed: What|Removed |Added Attachment #123263|text/plain |image/png mime

[Mesa-dev] [Bug 95110] Some Ogre 2.1 demos doesn't render properly

https://bugs.freedesktop.org/show_bug.cgi?id=95110 --- Comment #3 from MWATTT --- Created attachment 123263 --> https://bugs.freedesktop.org/attachment.cgi?id=123263=edit The demo on r600g (bad) -- You are receiving this mail because: You are the assignee for the bug. You

[Mesa-dev] [PATCH 7/7] llvmpipe: s/Elements/ARRAY_SIZE/

--- src/gallium/drivers/llvmpipe/lp_context.c | 10 +++ src/gallium/drivers/llvmpipe/lp_jit.c | 10 +++ src/gallium/drivers/llvmpipe/lp_rast_debug.c| 2 +- src/gallium/drivers/llvmpipe/lp_setup.c | 20 ++---

[Mesa-dev] [PATCH 6/7] tgsi: s/Elements/ARRAY_SIZE/

--- src/gallium/auxiliary/tgsi/tgsi_exec.c| 12 ++-- src/gallium/auxiliary/tgsi/tgsi_info.c| 2 +- src/gallium/auxiliary/tgsi/tgsi_scan.c| 8 src/gallium/auxiliary/tgsi/tgsi_strings.c | 16 src/gallium/auxiliary/tgsi/tgsi_text.c| 8

[Mesa-dev] [PATCH 3/7] gallivm: s/Elements/ARRAY_SIZE/

--- src/gallium/auxiliary/gallivm/lp_bld_arit.c | 4 ++-- src/gallium/auxiliary/gallivm/lp_bld_assert.c| 4 ++-- src/gallium/auxiliary/gallivm/lp_bld_format_aos.c| 8 src/gallium/auxiliary/gallivm/lp_bld_format_cached.c | 12 ++--

[Mesa-dev] [PATCH 5/7] os: s/Elements/ARRAY_SIZE/

--- src/gallium/auxiliary/os/os_process.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/os/os_process.c b/src/gallium/auxiliary/os/os_process.c index d2dcd0d..332e195 100644 --- a/src/gallium/auxiliary/os/os_process.c +++

[Mesa-dev] [PATCH 1/7] softpipe: s/Elements/ARRAY_SIZE/

Try to standardize on the later, which is defined in the common util/ directory. --- src/gallium/drivers/softpipe/sp_context.c| 16 src/gallium/drivers/softpipe/sp_flush.c | 4 ++-- src/gallium/drivers/softpipe/sp_state_derived.c | 2 +-

[Mesa-dev] [PATCH 4/7] hud: s/Elements/ARRAY_SIZE/

--- src/gallium/auxiliary/hud/font.c | 2 +- src/gallium/auxiliary/hud/hud_context.c | 10 +- src/gallium/auxiliary/hud/hud_driver_query.c | 2 +- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/gallium/auxiliary/hud/font.c

[Mesa-dev] [PATCH 2/7] draw: s/Elements/ARRAY_SIZE/

--- src/gallium/auxiliary/draw/draw_context.c | 2 +- src/gallium/auxiliary/draw/draw_llvm.c | 24 +++--- src/gallium/auxiliary/draw/draw_llvm_sample.c | 4 ++-- .../draw/draw_pt_fetch_shade_pipeline_llvm.c | 4 ++--

[Mesa-dev] [Bug 95110] Some Ogre 2.1 demos doesn't render properly

https://bugs.freedesktop.org/show_bug.cgi?id=95110 --- Comment #2 from MWATTT --- Created attachment 123262 --> https://bugs.freedesktop.org/attachment.cgi?id=123262=edit The demo on Catalyst (good) -- You are receiving this mail because: You are the assignee for the bug.

Re: [Mesa-dev] [PATCH v2 22/24] nvc0: inform users that 3D images are not fully supported

On Mon, Apr 25, 2016 at 4:15 PM, Samuel Pitoiset wrote: > 3D images are a bit more complicated to implement and will probably > requires a bunch of headaches and we don't care for now because they > do not seem to be really used by apps. > > v2: add a pipe_debug_message

Re: [Mesa-dev] [PATCH v2 20/24] nvc0/ir: check that the image format doesn't mismatch

Reviewed-by: Ilia Mirkin On Mon, Apr 25, 2016 at 4:15 PM, Samuel Pitoiset wrote: > This re-uses NVE4_SU_INFO_CALL which is not used anymore because we > don't use our lib for format conversions. While we are at it, add a > todo for image buffers

Re: [Mesa-dev] [PATCH] tgsi: pass a shader type to the machine create and clean up.

On 04/25/2016 06:48 PM, Dave Airlie wrote: From: Dave Airlie There was definitely bugs here mixing up the PIPE_ and TGSI_ defines, hopefully they didn't cause any problems, since mostly it was special cases for GEOMETRY. This clarifies at shader machine create what type of

Re: [Mesa-dev] [PATCH v2 19/24] nvc0/ir: prevent out of bounds when no images are bound

On Mon, Apr 25, 2016 at 4:15 PM, Samuel Pitoiset wrote: > Checking if the image address is not 0 should be enough to prevent > read faults. To improve robustness, make sure that the destination > value of atomic operations is correctly initialized in case the >

Re: [Mesa-dev] [PATCH v2 18/24] nvc0/ir: add indirect support for images on Kepler

On Mon, Apr 25, 2016 at 4:15 PM, Samuel Pitoiset wrote: > This fixes arb_shader_image_load_store-indexing and > arb_shader_image_load_store-max-images. > > Signed-off-by: Samuel Pitoiset > Reviewed-by: Ilia Mirkin > ---

Re: [Mesa-dev] [PATCH v2 17/24] nvc0/ir: fix 1D arrays images for Kepler

Reviewed-by: Ilia Mirkin On Mon, Apr 25, 2016 at 4:15 PM, Samuel Pitoiset wrote: > For 1D arrays, the array index is stored in the Z component. > > v2: simplify logic > > Signed-off-by: Samuel Pitoiset > --- >

Re: [Mesa-dev] [PATCH v2 14/24] nv50/ir: make use of OP_SUQ for surfaces query

On Mon, Apr 25, 2016 at 4:15 PM, Samuel Pitoiset wrote: > This implements RESQ for surfaces which comes from imageSize() GLSL > bultin. As the dimensions are sticked into the driver constant buffer, > this only has to be lowered with loads. > > v2: - load a 1 into .w

Re: [Mesa-dev] [PATCH v2 10/24] nv50/ir: re-introduce TGSI lowering pass for images

On Mon, Apr 25, 2016 at 4:14 PM, Samuel Pitoiset wrote: > This is loosely based on the previous lowering pass wrote by calim > four years ago. I did clean the code and fixed some issues. > > v2: drop .raw code which is unused for now > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v2 04/24] nvc0: bind images on 3D shaders for Kepler

Reviewed-by: Ilia Mirkin On Mon, Apr 25, 2016 at 4:14 PM, Samuel Pitoiset wrote: > Similar to surfaces validation for compute shaders. > > v2: - only stick images when images_dirty[s] != 0 > > Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v2 03/24] nvc0: bind images on compute shaders for Kepler

On Mon, Apr 25, 2016 at 4:14 PM, Samuel Pitoiset wrote: > Old surfaces validation code will be removed once images are completely > done for Fermi/Kepler, that explains why I only disable it for now. > > This also introduces nvc0_get_surface_dims() which computes

[Mesa-dev] [PATCH] vbo: Return INVALID_OPERATION during draw with a mapped buffer

Fixes the OpenGLES 3.1 CTS: * ESEXT-CTS.draw_elements_base_vertex_tests.invalid_mapped_bos Because this is triggering the error message after the normal API validation phase, we don't have the API function name available, and therefore we generate an error message that is a little confusing:

Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

Rob Herring writes: > On Fri, Apr 22, 2016 at 9:08 PM, Rob Herring wrote: >> On Fri, Apr 22, 2016 at 6:32 PM, Emil Velikov >> wrote: >>> Hi Rob, >>> >>> On 22 April 2016 at 16:50, Rob Herring wrote: This adds

[Mesa-dev] [PATCH] tgsi: pass a shader type to the machine create and clean up.

From: Dave Airlie There was definitely bugs here mixing up the PIPE_ and TGSI_ defines, hopefully they didn't cause any problems, since mostly it was special cases for GEOMETRY. This clarifies at shader machine create what type of shader this machine will execute. This is

Re: [Mesa-dev] [PATCH] glsl: fix lowering outputs for early/nested returns

Hi Lars, Thankd for working on this, comments below. On Sun, 2016-04-17 at 13:18 -0400, Lars Hamre wrote: > Return statements in conditional blocks were not having their > output varyings lowered correctly. > > This patch fixes the following piglit tests: >

[Mesa-dev] [PATCH] tgsi: move to using vector for system values.

From: Dave Airlie For compute support some of the system values are .xyz types, so move to using a vector instead of a single channel. Signed-off-by: Dave Airlie --- src/gallium/auxiliary/draw/draw_gs.c | 2 +-

Re: [Mesa-dev] [PATCH] gallium/tgsi: move tgsi_exec.h header out of draw_context.h

On 04/25/2016 05:44 PM, Dave Airlie wrote: From: Dave Airlie It gets annoying that changing the tgsi exec rebuilds the state tracker unnecessarily. Putting this include into draw_gs.h which uses it causes a lot less rebuilds. Signed-off-by: Dave Airlie

[Mesa-dev] [PATCH] gallium/tgsi: move tgsi_exec.h header out of draw_context.h

From: Dave Airlie It gets annoying that changing the tgsi exec rebuilds the state tracker unnecessarily. Putting this include into draw_gs.h which uses it causes a lot less rebuilds. Signed-off-by: Dave Airlie ---

Re: [Mesa-dev] [PATCH] glsl: Use correct mode for split components.

On Wednesday, April 20, 2016 3:42:01 PM PDT Bas Nieuwenhuizen wrote: > The mode should stay the same as the original struct. In > particular, shared should not be changed to temporary. > > Signed-off-by: Bas Nieuwenhuizen > --- >

Re: [Mesa-dev] [PATCH v4 4/4] r600g: use do_endian_swap in texture swapping function

For the series: Reviewed-by: Marek Olšák Marek On Sat, Apr 23, 2016 at 11:36 AM, Oded Gabbay wrote: > For some texture formats we need to take "do_endian_swap" into account > when configuring their swizzling. > > Signed-off-by: Oded Gabbay

Re: [Mesa-dev] [PATCH] nvc0: bump the amount of shared memory per MP on Maxwell

Reviewed-by: Ilia Mirkin On Mon, Apr 25, 2016 at 6:17 PM, Samuel Pitoiset wrote: > According to the CUDA compute capability version, GM10x can expose > 64KB of shared memory while GM20x can use 96KB. > > Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH] nvc0: bump the amount of shared memory per MP on Maxwell

According to the CUDA compute capability version, GM10x can expose 64KB of shared memory while GM20x can use 96KB. Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 12 +++- 1 file changed, 11 insertions(+), 1 deletion(-)

[Mesa-dev] [PATCH 5/6] swr: [rasterizer core] implement legacy depth bias enable

--- src/gallium/drivers/swr/rasterizer/core/api.cpp| 4 +-- .../drivers/swr/rasterizer/core/rasterizer.cpp | 8 +- src/gallium/drivers/swr/rasterizer/core/state.h| 32 ++ src/gallium/drivers/swr/swr_state.cpp | 2 +- 4 files changed, 25

[Mesa-dev] [PATCH 4/6] swr: [rasterizer jitter] support for dumping x86 asm

--- .../drivers/swr/rasterizer/jitter/JitManager.cpp | 49 ++ .../drivers/swr/rasterizer/jitter/JitManager.h | 1 + 2 files changed, 50 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/JitManager.cpp

[Mesa-dev] [PATCH 6/6] swr: [rasterizer] warning cleanup

--- .../drivers/swr/rasterizer/common/swr_assert.h | 17 - .../drivers/swr/rasterizer/core/backend.cpp| 24 .../drivers/swr/rasterizer/core/format_types.h | 1 - .../drivers/swr/rasterizer/core/frontend.cpp | 6 +--

[Mesa-dev] [PATCH 1/6] swr: [rasterizer core] backend refactor

Lump all template args into a bundle of traits, and add some functionality to the MSAA traits. --- src/gallium/drivers/swr/rasterizer/core/api.cpp| 4 - .../drivers/swr/rasterizer/core/backend.cpp| 334 ++- src/gallium/drivers/swr/rasterizer/core/backend.h | 50 ++-

[Mesa-dev] [PATCH 2/6] swr: [rasterizer jitter] add mSimdInt1Ty

--- src/gallium/drivers/swr/rasterizer/jitter/builder.cpp | 1 + src/gallium/drivers/swr/rasterizer/jitter/builder.h | 1 + 2 files changed, 2 insertions(+) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp b/src/gallium/drivers/swr/rasterizer/jitter/builder.cpp index

[Mesa-dev] [PATCH 0/6] update swr rasterizer

Couple of large backend refactorizations, some miscellaneous changes, and warning cleanup. Tim Rowley (6): swr: [rasterizer core] backend refactor swr: [rasterizer jitter] add mSimdInt1Ty swr: [rasterizer core] more backend refactoring swr: [rasterizer jitter] support for dumping x86 asm

[Mesa-dev] [PATCH] nvc0: stick compute kernel arguments into uniform_bo

Having one buffer object for input kernel arguments coming from clover and an other one for OpenGL user uniforms is unnecessary. Using the uniform_bo object for both GL/CL uniforms avoids to declare a new BO. This only affects compute programs but it should not hurt anything because the states

Re: [Mesa-dev] [Mesa-stable] [PATCH] egl/x11: authenticate before doing chipset id ioctls

On Tue, Apr 19, 2016 at 10:48 AM, Emil Velikov wrote: > On 19 April 2016 at 03:29, Jonathan Gray wrote: >> For systems without udev or sysfs that use drm ioctls in the loader >> drm authentication must take place earlier or the loader will fail >>

Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

On Fri, Apr 22, 2016 at 9:08 PM, Rob Herring wrote: > On Fri, Apr 22, 2016 at 6:32 PM, Emil Velikov > wrote: >> Hi Rob, >> >> On 22 April 2016 at 16:50, Rob Herring wrote: >>> This adds map and unmap functions to GBM utilizing the

Re: [Mesa-dev] [PATCH] mesa/st: log some additional invalid-fbo cases

On 04/25/2016 02:15 PM, Rob Clark wrote: From: Rob Clark Signed-off-by: Rob Clark --- src/mesa/state_tracker/st_cb_fbo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/state_tracker/st_cb_fbo.c

Re: [Mesa-dev] [PATCH 2/2] gm107/ir: s/invalid load/invalid store/

Reviewed-by: Ilia Mirkin On Mon, Apr 25, 2016 at 4:47 PM, Samuel Pitoiset wrote: > Signed-off-by: Samuel Pitoiset > --- > src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +- > 1 file changed, 1

[Mesa-dev] [PATCH 2/2] gm107/ir: s/invalid load/invalid store/

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gm107.cpp

[Mesa-dev] [PATCH 1/2] gk110/ir: remove an unused parameter in isLIMM()

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/gallium/drivers/nouveau/codegen/nv50_ir_emit_gk110.cpp

[Mesa-dev] [PATCH v2 24/24] nvc0: expose GLSL version 420 on GK104

Other chipsets will be added later. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_screen.c

[Mesa-dev] [PATCH v2 18/24] nvc0/ir: add indirect support for images on Kepler

This fixes arb_shader_image_load_store-indexing and arb_shader_image_load_store-max-images. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- .../nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 40 +++--- 1 file

[Mesa-dev] [PATCH v2 19/24] nvc0/ir: prevent out of bounds when no images are bound

Checking if the image address is not 0 should be enough to prevent read faults. To improve robustness, make sure that the destination value of atomic operations is correctly initialized in case the instruction is not performed. v2: make use of bld.getSSA() Signed-off-by: Samuel Pitoiset

[Mesa-dev] [PATCH v2 20/24] nvc0/ir: check that the image format doesn't mismatch

This re-uses NVE4_SU_INFO_CALL which is not used anymore because we don't use our lib for format conversions. While we are at it, add a todo for image buffers because there are some robustness-related issues to fix. Signed-off-by: Samuel Pitoiset ---

[Mesa-dev] [PATCH v2 00/24] nvc0: ARB_shader_image_load_store/size on GK104

Hi, This series adds support for ARB_shader_image_load_store (GL 4.2) and ARB_shader_image_size (GL 4.3) on GK104 and will expose OpenGL 4.2 on this chipset. The list of dEQP/piglit fails is available below. Please review, Thanks! Ilia Mirkin (1): nv50/ir: add support for SULDP -> SULDB

[Mesa-dev] [PATCH v2 02/24] nvc0: reserve an area for surfaces info in the driver constbuf

To process surfaces coordinates from the codegen part, and because some information like the format is not always available (eg. when writeonly is used), we have to stick some surfaces data in the driver constbuf. This is especially true for OpenCL because we don't know the format at shader

[Mesa-dev] [PATCH v2 14/24] nv50/ir: make use of OP_SUQ for surfaces query

This implements RESQ for surfaces which comes from imageSize() GLSL bultin. As the dimensions are sticked into the driver constant buffer, this only has to be lowered with loads. v2: - load a 1 into .w for the number of samples - divide z-dim for cube/cube arrays by 6 Signed-off-by: Samuel

[Mesa-dev] [PATCH v2 09/24] nv50/ir: add support for TGSI image declarations

Old and dead resource code will be removed once images are completely done. Based on original patch by Ilia Mirkin. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 23

[Mesa-dev] [PATCH v2 03/24] nvc0: bind images on compute shaders for Kepler

Old surfaces validation code will be removed once images are completely done for Fermi/Kepler, that explains why I only disable it for now. This also introduces nvc0_get_surface_dims() which computes correct dimensions regarding the given target. v2: - squash nvc0_get_surface_dims() into this

[Mesa-dev] [PATCH v2 08/24] nvc0: add missing glMemoryBarrier bits

This fixes a bunch of subtests of arb_shader_image_load_store-host-mem-barrier. v2: use (flags & (PIPE_A | PIPE_B)) to use a single operation Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin (v1) ---

[Mesa-dev] [PATCH v2 16/24] nvc0/ir: fix cube images for Kepler

Like 2d array images, the z-dimension needs to be clamped. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-)

[Mesa-dev] [PATCH v2 01/24] nvc0: add preliminary support for images

This implements set_shader_images() and resource invalidation for images. As OpenGL requires at least 8 images, we are going to expose this minimum value even if this might be raised for Kepler, but this limit is mainly for Fermi because the hardware only accepts 8 images. Based on original patch

[Mesa-dev] [PATCH v2 07/24] nvc0: enable RGB10_A2UI format on GK104

No clue why this was not enabled by default before, maybe because the SULDP conversion was wrong. Anyway, this helps in fixing all rgb10_a2ui piglit tests. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin ---

[Mesa-dev] [PATCH v2 04/24] nvc0: bind images on 3D shaders for Kepler

Similar to surfaces validation for compute shaders. v2: - only stick images when images_dirty[s] != 0 Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nvc0/nvc0_program.c | 4 +++- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 29

[Mesa-dev] [PATCH v2 06/24] nvc0: shift address with blocksize for image buffers

This fixes a bunch of dEQP image buffers related tests. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 4 1 file changed, 4 insertions(+) diff --git

[Mesa-dev] [PATCH v2 13/24] nv50/ir: add OP_BUFQ for buffers query

TGSI RESQ allows both images and buffers but we have to make a distinction between these two type of resources in our lowering pass. Introducing OP_BUFQ which is a fake operand will allow to implement OP_SUQ for surfaces. Signed-off-by: Samuel Pitoiset Reviewed-by:

[Mesa-dev] [PATCH v2 23/24] nvc0: enable ARB_shader_image_load_store on GK104

This exposes 8 images for all shader types. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_screen.c | 2 ++ 1 file changed, 2 insertions(+) diff --git

[Mesa-dev] [PATCH v2 10/24] nv50/ir: re-introduce TGSI lowering pass for images

This is loosely based on the previous lowering pass wrote by calim four years ago. I did clean the code and fixed some issues. v2: drop .raw code which is unused for now Signed-off-by: Samuel Pitoiset --- .../drivers/nouveau/codegen/nv50_ir_from_tgsi.cpp | 97

[Mesa-dev] [PATCH v2 11/24] nvc0/ir: fix constraints for OP_SUSTx on Kepler

Destination type is actually always 32-bits, so typeSizeof() returns 4 and no sources are condensed. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/codegen/nv50_ir_ra.cpp | 4 +++- 1 file changed, 3

[Mesa-dev] [PATCH v2 21/24] nvc0: reduce GL_MAX_3D_TEXTURE_SIZE to 2048 on Kepler+

The blob sets it to 2048 and using 4096 reports an INVALID_DATA error with RT_ARRAY_MODE when z is 4096. Suggested by Ilia Mirkin. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin Cc: "11.1 11.2" ---

[Mesa-dev] [PATCH v2 17/24] nvc0/ir: fix 1D arrays images for Kepler

For 1D arrays, the array index is stored in the Z component. v2: simplify logic Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/codegen/nv50_ir_lowering_nvc0.cpp | 11 +-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 05/24] nvc0: fix address offset when images have multiple levels

This fixes arb_shader_image_load_store-level. Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin --- src/gallium/drivers/nouveau/nvc0/nvc0_tex.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/nouveau/nvc0/nvc0_tex.c

[Mesa-dev] [PATCH v2 22/24] nvc0: inform users that 3D images are not fully supported

3D images are a bit more complicated to implement and will probably requires a bunch of headaches and we don't care for now because they do not seem to be really used by apps. v2: add a pipe_debug_message Signed-off-by: Samuel Pitoiset Reviewed-by: Ilia Mirkin

[Mesa-dev] [PATCH v2 12/24] nv50/ir: enable early fragment test with explicit user control

This feature can be enabled in two ways: as an optimization and by explicit user control (with OpenGL 4.2 or ARB_shader_image_load_store). This makes use of the recent TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL to force early fragment tests when needed. This fixes a bunch of

[Mesa-dev] [PATCH] mesa/st: log some additional invalid-fbo cases

From: Rob Clark Signed-off-by: Rob Clark --- src/mesa/state_tracker/st_cb_fbo.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/state_tracker/st_cb_fbo.c b/src/mesa/state_tracker/st_cb_fbo.c index 456ad83..a53b95a 100644 ---

[Mesa-dev] [PATCH] r600: include u_memory.h to get Elements() macro

Fixes "undefined Elements()" regression caused by commit 63df017fda. --- src/gallium/drivers/r600/r600_pipe.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/gallium/drivers/r600/r600_pipe.h b/src/gallium/drivers/r600/r600_pipe.h index 7793859..6692d4a 100644 ---

Re: [Mesa-dev] [PATCH] docs: update link to Intel's graphics website

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] docs: update the instructions for getting a git account

Thanks for doing this. Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa/gles: Allow format GL_RED to be used with MESA_FORMAT_R_UNORM

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=94396 ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 3/5] i965: Move TCS output indirect_offset.file check out a level.

On Mon, Apr 25, 2016 at 12:33:26PM -0700, Kenneth Graunke wrote: > On Monday, April 25, 2016 10:46:37 AM PDT Pohjolainen, Topi wrote: > > On Thu, Apr 21, 2016 at 10:32:07PM -0700, Kenneth Graunke wrote: > > > I want to add another condition. Moving the indirect_offset.file > > > check out a level

Re: [Mesa-dev] [PATCH 3/5] i965: Move TCS output indirect_offset.file check out a level.

On Monday, April 25, 2016 10:46:37 AM PDT Pohjolainen, Topi wrote: > On Thu, Apr 21, 2016 at 10:32:07PM -0700, Kenneth Graunke wrote: > > I want to add another condition. Moving the indirect_offset.file > > check out a level should make this a little easier. > > > > Signed-off-by: Kenneth

[Mesa-dev] [PATCH] docs: update link to Intel's graphics website

--- docs/systems.html | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/docs/systems.html b/docs/systems.html index f847928..1286387 100644 --- a/docs/systems.html +++ b/docs/systems.html @@ -34,8 +34,7 @@ Hardware drivers include: Intel i965, i945, i915. -See

Re: [Mesa-dev] [PATCH 2/5] i965: Mark URB reads as volatile.

On Monday, April 25, 2016 8:22:59 AM PDT Eduardo Lima Mitev wrote: > Patches 1 and 2 are: > > Reviewed-by: Eduardo Lima Mitev Thanks! Pushed these two. signature.asc Description: This is a digitally signed message part. ___

Re: [Mesa-dev] [PATCH 4/4] gbm: Add map/unmap functions

On Mon, Apr 25, 2016 at 9:25 AM, Emil Velikov wrote: > Hi all, > > On 25 April 2016 at 13:46, Daniel Stone wrote: >> Hi, >> >> On 23 April 2016 at 03:08, Rob Herring wrote: >>> On Fri, Apr 22, 2016 at 6:32 PM, Emil Velikov

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