Re: [Mesa-dev] [PATCH 2/7] i965: Pass devinfo pointer to is_3src() helpers.

On Thu, 2016-04-28 at 15:38 +0200, Iago Toral wrote: > On Thu, 2016-04-28 at 00:19 -0700, Francisco Jerez wrote: > > This is not strictly required for the following changes because none > > of the three-source opcodes we support at the moment in the compiler > > back-end has been removed or

Re: [Mesa-dev] [PATCH 2/7] i965: Pass devinfo pointer to is_3src() helpers.

On Thu, 2016-04-28 at 00:19 -0700, Francisco Jerez wrote: > This is not strictly required for the following changes because none > of the three-source opcodes we support at the moment in the compiler > back-end has been removed or redefined, but that's likely to change in > the future. In any

Re: [Mesa-dev] [PATCH 1/4] gbm: Add Android build support

On Fri, Apr 22, 2016 at 5:57 PM, Emil Velikov wrote: > Hi Rob, > > On 22 April 2016 at 16:50, Rob Herring wrote: > >> --- /dev/null >> +++ b/src/gbm/Android.mk > >> +LOCAL_EXPORT_C_INCLUDE_DIRS := \ >> + $(LOCAL_PATH)/main >> + > You don't need

Re: [Mesa-dev] [PATCH 11/15] i965: abort linking if we exhaust the registers

On 04/28/2016 01:40 PM, Antia Puentes wrote: > From: "Juan A. Suarez Romero" > > Even when the number of vertex attributes is under the limit, for > shaders that use a high number of them, we can quickly exhaust the > number of hardware registers. Were you able to construct

Re: [Mesa-dev] [PATCH 05/15] i965/fs: shuffle 32bits into 64bits for doubles

On 04/28/2016 01:40 PM, Antia Puentes wrote: > From: "Juan A. Suarez Romero" > > VS Thread Payload handles attributes in URB as vec4, no matter if they > are actually single or double precision. > > So with double-precision types, value ends up in the registers split in >

Re: [Mesa-dev] [PATCH 15/15] i965: Expose OpenGL 4.1 for gen8+

On jue, 2016-04-28 at 15:11 +0200, Ian Romanick wrote: > I think we should bump all the way to 4.2 because all of the features > specific to 4.2 have been done for quite some time. True. > On 04/28/2016 01:40 PM, Antia Puentes wrote: > > From: Alejandro Piñeiro > > > >

Re: [Mesa-dev] [PATCH 04/15] i965/fs: half exec_size when dealing with 64 bits attributes

On 04/28/2016 01:40 PM, Antia Puentes wrote: > From: Alejandro Piñeiro > > The HW has a restriction that only vertical stride may cross register > boundaries. Until now this was only handled on VGRFs at > rw_reg_from_fs_reg, but it is also needed for attributes. > > This

[Mesa-dev] [Bug 92850] Segfault loading War Thunder

https://bugs.freedesktop.org/show_bug.cgi?id=92850 --- Comment #68 from Felix Schwarz --- (In reply to higuita from comment #67) > May i suggest to include this patch in any maintenance/bugfix release for > mesa 11.x? in linked patch (see patchwork link above)

[Mesa-dev] [RFC PATCH] winsys/radeon: drop support for kernels lacking tile mode array queries

From: Marek Olšák This will allow us to simplify a lot of code around tiling. Kernel 3.10 is required for SI. Kernel 3.13 is required for CIK. --- src/gallium/winsys/radeon/drm/radeon_drm_winsys.c | 20 ++-- 1 file changed, 14 insertions(+), 6 deletions(-)

Re: [Mesa-dev] [PATCH 02/15] i965: Configure how to store *64*PASSTHRU vertex components

On 04/28/2016 01:40 PM, Antia Puentes wrote: > From the Broadwell specification, structure VERTEX_ELEMENT_STATE > description: > >"When SourceElementFormat is set to one of the *64*_PASSTHRU > formats, 64-bit components are stored in the URB without any > conversion. In this case,

[Mesa-dev] [Bug 92850] Segfault loading War Thunder

https://bugs.freedesktop.org/show_bug.cgi?id=92850 --- Comment #67 from higu...@gmx.net --- May i suggest to include this patch in any maintenance/bugfix release for mesa 11.x? this would help pushing this to distros updates and to normal linux users and not have to wait 6+ months for the

Re: [Mesa-dev] [PATCH 15/15] i965: Expose OpenGL 4.1 for gen8+

I think we should bump all the way to 4.2 because all of the features specific to 4.2 have been done for quite some time. On 04/28/2016 01:40 PM, Antia Puentes wrote: > From: Alejandro Piñeiro > > ARB_vertex_attrib_64bit was the only feature missing. > --- >

[Mesa-dev] [PATCH] gallium/radeon: drop support for LINEAR_GENERAL layout

From: Marek Olšák Unused. All texture imports use LINEAR_ALIGNED regardless of what the DDX does. --- src/gallium/drivers/r600/evergreen_state.c | 33 +- src/gallium/drivers/r600/r600_state.c | 33 ++

[Mesa-dev] [PATCH] radeonsi: rework clear_buffer flags

From: Marek Olšák Changes: - don't flush DB for fast color clears - don't flush any caches for initial clears - remove the flag from si_copy_buffer, always assume shader coherency --- src/gallium/drivers/r600/r600_blit.c | 2 +-

Re: [Mesa-dev] [RFC 1/3] tgsi: Add WORK_DIM System Value

Hi, On 28-04-16 10:13, Pierre Moreau wrote: On 05:43 PM - Apr 27 2016, Samuel Pitoiset wrote: On 04/27/2016 05:24 PM, Ilia Mirkin wrote: On Wed, Apr 27, 2016 at 11:19 AM, Hans de Goede wrote: Hi, On 27-04-16 16:49, Ilia Mirkin wrote: Please add this semantic to

[Mesa-dev] [PATCH 07/15] i965: take care of doubles when remapping VS attributes

From: "Juan A. Suarez Romero" Double-precision types require 1 slot in VUE for double and dvec2, and 2 slots for anything else. --- src/mesa/drivers/dri/i965/brw_nir.c | 26 +++--- 1 file changed, 11 insertions(+), 15 deletions(-) diff --git

[Mesa-dev] [PATCH 02/15] i965: Configure how to store *64*PASSTHRU vertex components

From the Broadwell specification, structure VERTEX_ELEMENT_STATE description: "When SourceElementFormat is set to one of the *64*_PASSTHRU formats, 64-bit components are stored in the URB without any conversion. In this case, vertex elements must be written as 128 or 256 bits,

[Mesa-dev] [PATCH 15/15] i965: Expose OpenGL 4.1 for gen8+

From: Alejandro Piñeiro ARB_vertex_attrib_64bit was the only feature missing. --- src/mesa/drivers/dri/i965/intel_extensions.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 00/15] Add ARB_vertex_attrib_64bit for i965 scalar (gen8+)

Hello, the following series adds the implementation for the ARB_vertex_attrib_64bit extension on the i965 scalar backend (gen8+). It is the result of working on https://bugs.freedesktop.org/show_bug.cgi?id=94442. As this work depends on the ARB_gpu_shader_fp64 i965 functionality [1], which is

[Mesa-dev] [PATCH 12/15] i965: abort linking if URB read length greater than 15

From: "Juan A. Suarez Romero" In scalar mode, URB read length limit is 15. Abort if we go beyond it. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp

[Mesa-dev] [PATCH 14/15] docs: Mark ARB_vertex_attrib_64bit as done for i965

From: Alejandro Piñeiro --- docs/GL3.txt | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/docs/GL3.txt b/docs/GL3.txt index 95ee508..3f1f7a3 100644 --- a/docs/GL3.txt +++ b/docs/GL3.txt @@ -142,7 +142,7 @@ GL 4.1, GLSL 4.10 --- all DONE: nvc0, r600,

[Mesa-dev] [PATCH 04/15] i965/fs: half exec_size when dealing with 64 bits attributes

From: Alejandro Piñeiro The HW has a restriction that only vertical stride may cross register boundaries. Until now this was only handled on VGRFs at rw_reg_from_fs_reg, but it is also needed for attributes. This can be seen as the equivalent of commit 552cfa9 but for

[Mesa-dev] [PATCH 10/15] i965: take care of doubles when lowering VS inputs

From: "Juan A. Suarez Romero" Input attributes can require 2 vec4 or 1 vec4 depending on whether they are double-precision or not. --- src/mesa/drivers/dri/i965/brw_fs.cpp | 13 + src/mesa/drivers/dri/i965/brw_nir.c| 3 ++-

[Mesa-dev] [PATCH 01/15] i965: get the proper vertex surface type for doubles on gen8+

From: Alejandro Piñeiro This commit adds support for PASSTHRU format when pushing double-precision attributes. Check glarray->Doubles in order to know if we should choose a format that does a conversion to float, or just passthru the 64-bit double. ---

[Mesa-dev] [PATCH 11/15] i965: abort linking if we exhaust the registers

From: "Juan A. Suarez Romero" Even when the number of vertex attributes is under the limit, for shaders that use a high number of them, we can quickly exhaust the number of hardware registers. In this case, just abort the linking. --- src/mesa/drivers/dri/i965/brw_fs.cpp |

[Mesa-dev] [PATCH 08/15] i965/vec4: use attribute slots to calculate URB read length

From: "Juan A. Suarez Romero" Do not use total attributes because a dvec3/dvec4 attribute requires two slots. So rather use total attribute slots. --- src/mesa/drivers/dri/i965/brw_vec4.cpp | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff

[Mesa-dev] [PATCH 13/15] i965: Enable ARB_vertex_attrib_64bit for gen8+

From: Alejandro Piñeiro --- src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c b/src/mesa/drivers/dri/i965/intel_extensions.c index 412dea0..d3905d0 100644 ---

[Mesa-dev] [PATCH 03/15] i965: passthru formats cannot be used width edge flag enabled

From: Alejandro Piñeiro Add an assertion to detect this case. --- src/mesa/drivers/dri/i965/gen8_draw_upload.c | 20 1 file changed, 20 insertions(+) diff --git a/src/mesa/drivers/dri/i965/gen8_draw_upload.c

[Mesa-dev] [PATCH 09/15] i965/fs: calculate first non-payload GRF using attrib slots

From: "Juan A. Suarez Romero" When computing where the first non-payload GRF starts, we can't rely on the number of attributes, as each attribute can be using 1 or 2 slots depending on whether they are a dvec3/4 or other. Instead, we need to use the number of slots used by

[Mesa-dev] [PATCH 06/15] nir: add double input bitmap

From: "Juan A. Suarez Romero" This bitmap tracks which input attributes are double-precision. --- src/compiler/nir/glsl_to_nir.cpp | 1 + src/compiler/nir/nir.h | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/compiler/nir/glsl_to_nir.cpp

[Mesa-dev] [PATCH 05/15] i965/fs: shuffle 32bits into 64bits for doubles

From: "Juan A. Suarez Romero" VS Thread Payload handles attributes in URB as vec4, no matter if they are actually single or double precision. So with double-precision types, value ends up in the registers split in 32bits chunks, in different positions. We need to shuffle

[Mesa-dev] [Bug 95180] rasterizer/memory/Convert.h:170:9: error: ‘__builtin_isnan’ is not a member of ‘std’

https://bugs.freedesktop.org/show_bug.cgi?id=95180 --- Comment #2 from Jose Fonseca --- I wonder if there's a #include missing somewhere. Also, per https://cgit.freedesktop.org/mesa/mesa/commit/?id=649704f1f7c9e1d0990d34a76154b2eb656bee42 , it sounds that GLIBC prior

[Mesa-dev] [PATCH 2/4] nir: Remove spurious ; after namespace.

Makes -pedantic happy. --- src/compiler/nir/glsl_to_nir.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/glsl_to_nir.cpp b/src/compiler/nir/glsl_to_nir.cpp index fafa8bb..e3fa623 100644 --- a/src/compiler/nir/glsl_to_nir.cpp +++

[Mesa-dev] [PATCH 3/4] nir: Remove spurious ; after nir_builder functions.

--- src/compiler/nir/nir_builder_opcodes_h.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/compiler/nir/nir_builder_opcodes_h.py b/src/compiler/nir/nir_builder_opcodes_h.py index e27206e..038e2b4 100644 --- a/src/compiler/nir/nir_builder_opcodes_h.py +++

[Mesa-dev] [PATCH 4/4] nir: Try to warn when C99 extensions are used in nir headers.

Ideally we'd have nir.h being included with -Wpedantic too. src/compiler/nir/nir.h:754:20: warning: ISO C++ forbids zero-size array ‘src’ [-Wpedantic] nir_alu_src src[]; ^ In file included from src/compiler/nir/glsl_to_nir.cpp:42:0: src/compiler/nir/nir.h:919:16: warning:

[Mesa-dev] [PATCH 1/4] nir: Avoid C99 field initializers.

As they are not standard C++ and are not supported by MSVC C++ compiler. Just have nir_imm_double match nir_imm_float above. --- src/compiler/nir/nir_builder.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir_builder.h

Re: [Mesa-dev] [AppVeyor] mesa master #1090 failed

On 28/04/16 11:44, Jose Fonseca wrote: On 28/04/16 11:07, AppVeyor wrote: Build mesa 1090 failed Commit db07b46f2c by Samuel Iglesias Gonsálvez on 4/26/2016 7:35 AM: nir: Add lrp lowering for

[Mesa-dev] [PATCH 2/3] mesa: rename lower_fmod to lower_fmod32

A later patch will add lower_fmod64 option to NIR. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 2 +- src/compiler/nir/nir_opt_algebraic.py| 4 ++-- src/mesa/drivers/dri/i965/brw_compiler.c | 2 +- 3 files changed, 4

[Mesa-dev] [PATCH 3/3] nir/opt_algebraic: lower mod() with doubles operands if lower_fmod64 is enabled

Make this distintion as the drivers might need to lower it inside NIR. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h| 2 ++ src/compiler/nir/nir_opt_algebraic.py | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 1/3] nir/lower_double_ops: lower mod()

There are rounding errors with the division in i965 that affect the mod(x,y) result when x = N * y. Instead of returning '0' it was returning 'y'. This lowering pass fixes those cases. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h |

[Mesa-dev] [PATCH 3/3] i965/blorp: Use hardware for layered clears

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp_clear.cpp | 43 +++ 1 file changed, 11 insertions(+), 32 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp

[Mesa-dev] [PATCH 2/3] i965/blorp: Add means to use normal render surface setup

This will be initially used for clears (allowing correct setup for layered clears), and later on for blits that get launched against the current gl-state. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_blorp.c | 1 +

[Mesa-dev] [PATCH 1/3] i965/blorp: Instruct vertex fetcher to provide prim instance id

This will indicate target layer (Render Target Array Index) needed for layered clears. Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen6_blorp.c | 10 ++ 1 file changed, 6 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [Bug 95180] rasterizer/memory/Convert.h:170:9: error: ‘__builtin_isnan’ is not a member of ‘std’

https://bugs.freedesktop.org/show_bug.cgi?id=95180 --- Comment #1 from Tim Rowley --- That's odd - "std:isnan" is C++11, and I don't see any macros in the mesa tree that would be messing it up. What compiler/platform are you building on? -- You are receiving this

Re: [Mesa-dev] [PATCH 3/3] radeonsi: don't flush DB for fast color clears

On Thu, Apr 28, 2016 at 1:45 AM, Nicolai Hähnle wrote: > r600_screen_clear_buffer is always called with last parameter true, also for > the initial HTILE clear, so that doesn't seem quite right to me. I'll send a new patch. Marek

Re: [Mesa-dev] [AppVeyor] mesa master #1090 failed

On 28/04/16 11:07, AppVeyor wrote: Build mesa 1090 failed Commit db07b46f2c by Samuel Iglesias Gonsálvez on 4/26/2016 7:35 AM: nir: Add lrp lowering for doubles in opt_algebraic\n\nSome hardware

[Mesa-dev] [PATCH 2/2] mesa: dri: Add shared glapi to LIBADD on Android

/system/vendor/lib/dri/*_dri.so actually depend on libglapi: without this, loading the so file fails with: cannot locate symbol "__emutls_v._glapi_tls_Context" On non-Android (non-bionic) platform, EGL uses the following workflow, which works fine: dlopen("libglapi.so", RTLD_LAZY |

[Mesa-dev] [PATCH 1/2] configure.ac: Add support for Android builds

Add support for EGL android platform. Also, detect when --host finishes with -android. In that case, we do not set _GNU_SOURCE, and define autoconf symbol HAVE_ANDROID, so that Android-specific workarounds can be applied. Signed-off-by: Nicolas Boichat --- configure.ac

[Mesa-dev] [AppVeyor] mesa master #1090 failed

Build mesa 1090 failed Commit db07b46f2c by Samuel Iglesias Gonsálvez on 4/26/2016 7:35 AM: nir: Add lrp lowering for doubles in opt_algebraic\n\nSome hardware (i965 on Broadwell generation, for example) does not support\nnatively the execution of lrp

Re: [Mesa-dev] [PATCH] mesa: improve comment on _mesa_check_disallowed_mapping(), return bool

Reviewed-by: Marek Olšák Marek On Wed, Apr 27, 2016 at 6:44 PM, Brian Paul wrote: > The old comment was a bit terse. Also, change the function return > type to bool. > --- > src/mesa/main/bufferobj.h | 10 -- > 1 file changed, 8 insertions(+),

Re: [Mesa-dev] [RFC 1/3] tgsi: Add WORK_DIM System Value

On 05:43 PM - Apr 27 2016, Samuel Pitoiset wrote: > > > On 04/27/2016 05:24 PM, Ilia Mirkin wrote: > >On Wed, Apr 27, 2016 at 11:19 AM, Hans de Goede wrote: > >>Hi, > >> > >>On 27-04-16 16:49, Ilia Mirkin wrote: > >>> > >>>Please add this semantic to src/gallium/docs and

[Mesa-dev] [RFC 4/7] android: print debug info to logcat

From: WuZhen Redirect logs printed to stderr to logcat. NO_REF_TASK tested: local run Change-Id: I58e3966a608af361b86c54b4c95a92561b711968 Signed-off-by: Chih-Wei Huang --- src/gallium/auxiliary/os/os_misc.c | 12 ++--

[Mesa-dev] [RFC 3/7] gallium/swrast: fix dri_sw_dt->data free func not matching alloc func

From: WuZhen The old code causes crashes when using software rendering. NO_REF_TASK tested: local run Change-Id: Ib1d7f36b9f25ccc13afdd28d1e34f76162d3 Signed-off-by: Chih-Wei Huang --- src/gallium/winsys/sw/dri/dri_sw_winsys.c | 2 +- 1 file

[Mesa-dev] [RFC 6/7] android: enable x86 asm and sse4 for x86 and x86_64

From: WuZhen Support multilib compilation use runtime feature selection. NO_REF_TASK tested: local run Change-Id: Iee7961effdecde09cfbdaf09455bfb0912699ae3 Signed-off-by: Chih-Wei Huang --- Android.common.mk| 21

[Mesa-dev] [RFC 2/7] tgsi: fix stack allocated struct may not be initialized

From: WuZhen NO_REF_TASK tested: local run Change-Id: Ied449126c2059d2654afebdf68972cb00862a4ce Signed-off-by: Chih-Wei Huang --- src/gallium/auxiliary/tgsi/tgsi_dump.c | 7 +++ 1 file changed, 7 insertions(+) diff --git

[Mesa-dev] [RFC 1/7] st/dri: fix double free of dri_drawable

From: WuZhen In the callchain destroy_surface->destroyDrawable->dri_put_drawable-> dri_put_drawable->DestroyBuffer By the semantic of it, dri_destroy_buffer should not free drawable struct, all vendor specific and legacy swrast version of the function do not. wonder why no

[Mesa-dev] [RFC 5/7] android: enable dlopen

From: WuZhen NO_REF_TASK tested: local run Change-Id: I7c3c03f844ba6fc7ee3d6817d9ee1e806b92aed7 Signed-off-by: Chih-Wei Huang --- Android.common.mk | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Android.common.mk

[Mesa-dev] [RFC 7/7] android: support swrast

From: WuZhen System boots up with gles_mesa/softpipe/llvmpipe. NO_REF_TASK tested: local run Change-Id: I629ed0ca9fad12e32270eb8e8bfa9f7681b68474 Signed-off-by: Chih-Wei Huang --- Android.mk | 2 +-

[Mesa-dev] [RFC 0/7] android: enable llvmpipe for software rendering

This is a series of patches developed by Jide Technolody to enable the llvmpipe for software rendering of Android. It makes a device without a Mesa supported GPU could run most modern Android apps. These patches are mainly developed and tested on the 11.0 and 11.2 branches. They might not work

[Mesa-dev] [PATCH 6/7] i965: Move opcode_desc tables into brw_eu.c.

The opcode_desc tables are useful for several purposes other than disassembling the program: Finding out whether an instruction is three-source in the optimizer and instruction compaction code, printing out instructions at the IR level and validating assembled programs -- It seems like brw_eu.c

[Mesa-dev] [PATCH 7/7] i965: Remove inst_info table from brw_eu_validate.

At this point this doesn't contain any information not already in the opcode_desc tables, the validation code can just call brw_opcode_desc() in order to find out whether an instruction is supported by the device. --- src/mesa/drivers/dri/i965/brw_eu_validate.c | 246 +---

[Mesa-dev] [PATCH 5/7] i965/disasm: Mark instructions that no longer exist in the opcode_desc tables.

With this small addition we can now easily determine on which generations a given instruction is supported from the opcode_desc tables alone. --- src/mesa/drivers/dri/i965/brw_disasm.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 4/7] i965/disasm: Split opcode tables by the generation they were introduced in.

--- src/mesa/drivers/dri/i965/brw_disasm.c | 90 ++ 1 file changed, 69 insertions(+), 21 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_disasm.c b/src/mesa/drivers/dri/i965/brw_disasm.c index 15d9383..0125434 100644 ---

[Mesa-dev] [PATCH 2/7] i965: Pass devinfo pointer to is_3src() helpers.

This is not strictly required for the following changes because none of the three-source opcodes we support at the moment in the compiler back-end has been removed or redefined, but that's likely to change in the future. In any case having hardware instructions specified as a pair of hardware

[Mesa-dev] [PATCH 3/7] i965/disasm: Wrap opcode_desc look-up in a function.

The function takes a device info struct as argument in addition to the opcode number in order to disambiguate between multiple opcode_desc entries for different instructions with the same opcode number. --- src/mesa/drivers/dri/i965/brw_context.h | 1 - src/mesa/drivers/dri/i965/brw_disasm.c

[Mesa-dev] [PATCH 1/7] i965: Pass devinfo pointer to brw_instruction_name().

A future series will implement support for an instruction that happens to have the same opcode number as another instruction we support already on a disjoint set of hardware generations. In order to disambiguate which instruction it is brw_instruction_name() will need some way to find out which

Re: [Mesa-dev] [PATCH 2/6] nir: Switch the arguments to nir_foreach_phi_src

On 04/27/2016 07:39 PM, Jason Ekstrand wrote: > On Wed, Apr 27, 2016 at 12:54 AM, Ian Romanick > wrote: > > On 04/27/2016 05:41 AM, Jason Ekstrand wrote: > > This matches the "foreach x in container" pattern found in many other > >

Re: [Mesa-dev] [PATCH] mesa: improve comment on _mesa_check_disallowed_mapping(), return bool

Reviewed-by: Ian Romanick On 04/27/2016 06:44 PM, Brian Paul wrote: > The old comment was a bit terse. Also, change the function return > type to bool. > --- > src/mesa/main/bufferobj.h | 10 -- > 1 file changed, 8 insertions(+), 2 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH v2 1/2] nir: rename lower_flrp to lower_flrp32

Both are Reviewed-by: Jason Ekstrand On Apr 27, 2016 11:20 PM, "Samuel Iglesias Gonsálvez" wrote: > A later patch will add lower_flrp64 option to NIR. > > Signed-off-by: Samuel Iglesias Gonsálvez > --- > src/compiler/nir/nir.h

[Mesa-dev] [PATCH v2 2/2] nir: Add lrp lowering for doubles in opt_algebraic

Some hardware (i965 on Broadwell generation, for example) does not support natively the execution of lrp instruction with double arguments. Add 'lower_flrp64' flag to lower this instruction in that case. v2: - Rename lower_flrp_double to lower_flrp64 (Jason) - Fix typo (Jason) - Adapt

[Mesa-dev] [PATCH v2 1/2] nir: rename lower_flrp to lower_flrp32

A later patch will add lower_flrp64 option to NIR. Signed-off-by: Samuel Iglesias Gonsálvez --- src/compiler/nir/nir.h | 2 +- src/compiler/nir/nir_opt_algebraic.py | 12 ++-- src/gallium/drivers/freedreno/ir3/ir3_nir.c | 2 +-

Re: [Mesa-dev] [PATCH 3/3] nir/algebraic: Support lowering for bot 64 and 32-bit ldexp

-BEGIN PGP SIGNED MESSAGE- Hash: SHA256 s/bot/both Patches 1-3 are: Reviewed-by: Samuel Iglesias Gonsálvez On 27/04/16 20:25, Jason Ekstrand wrote: > --- src/compiler/nir/nir_opt_algebraic.py | 31 > ++- 1 file changed, 22

[Mesa-dev] [PATCH v2 8/9] i965: Implement ARB_query_buffer_object for HSW+

v2: * Declare loop index variable at loop site (idr) * Make arrays of MI_MATH instructions 'static const' (idr) * Remove commented debug code (idr) * Updated comment in set_query_availability (Ken) * Replace switch with if/else in hsw_result_to_gpr0 (Ken) * Only divide

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