On Wednesday, May 10, 2017 10:19:46 AM PDT Emil Velikov wrote:
> On 10 May 2017 at 16:38, Jason Ekstrand wrote:
> > On Wed, May 10, 2017 at 8:26 AM, Emil Velikov
> > wrote:
> >>
> >> Hi Jason,
> >>
> >> Humble unrelated question.
> >>
> >> On 9 May
On Tuesday, May 9, 2017 6:57:53 PM PDT Timothy Arceri wrote:
> This was added in b527dd65c830a as a work around because fixed function
> fragment shaders were tracked in ctx->FragmentProgram._Current as
> a gl_program rather than gl_shader_program.
>
> However after my refactoring of the program
For the series:
Tested-by: Dieter Nützel
on radeonsi / RX580, 8 GB
Unigine_Heaven-4.0
Unigine_Valley-1.0
Unigine_Superposition-1.0
running wine-2.7_gallium_nine+staging
Steam: PES2015 + TS2017
LS2015 + LS2017 (!!! ;-)
Except: currently _only_ Linux 4.11
(have to
For the series:
Tested-by: Dieter Nützel
on radeonsi / RX580, 8 GB
Unigine_Heaven-4.0
Unigine_Valley-1.0
Unigine_Superposition-1.0
Nine (as Nicolai requested):
running wine-2.7_gallium_nine+staging
Steam: PES2015 + TS2017
LS2015 + LS2017 (!!!)
Dieter
Am 10.05.2017
On 10/05/17 11:31 PM, Kai Wasserbäch wrote:
> Michel Dänzer wrote on 10.05.2017 10:27:
>> From: Michel Dänzer
>>
>> deregisterEHFrames doesn't take any parameters anymore.
>>
>> Signed-off-by: Michel Dänzer
>
> LGTM,
Thanks, but the convention
Hi Nicolai and Marek,
Gallium nine associates to every d3d usage/index a generic unique index.
That should fit on a 16bits integer, but not for 32 values.
We could fit in 32 indexes by recompiling vertex and pixel shaders to match,
but one advantage of gallium nine is we don't need much
On 10/05/2017 09:17, Nicolai Hähnle wrote:
On 10.05.2017 08:58, Axel Davy wrote:
Hi Nicolai and Marek,
Gallium nine associates to every d3d usage/index a generic unique index.
That should fit on a 16bits integer, but not for 32 values.
Hold on, you're saying the semantic index could be as
Build mesa 4332 failed
Commit fe6c407a33 by Dave Airlie on 5/11/2017 12:05 AM:
radv: handle fragment shader srgb resolve pass better\n\nBas pointed out the fs key doesn't take srgb into account,\nsince there is just one srgb variant, just create a
On 11/05/17 08:45, Marek Olšák wrote:
Hi,
This series adds an optional module into gallium/util that wraps
around pipe_context and moves execution of all pipe_context calls into
a separate thread.
It puts a lot of new requirements on the driver, especially on thread-
safetiness of pipe_context
From: Dave Airlie
Bas pointed out the fs key doesn't take srgb into account,
since there is just one srgb variant, just create a separate
pipeline for it. This also uses dest format to be more consistent
on when srgb matters.
Signed-off-by: Dave Airlie
On Wed, May 03, 2017 at 03:39:51PM -0700, Jason Ekstrand wrote:
> On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> wrote:
>
> > There's no image layout to represent a full-RT-cleared color attachment.
> > That's one reason we can end up with redundant resolves. Testing has
We processed fs key 3 multiple times, resulting in overwriting the
pointer in the meta struct and hence only freeing one of them.
Fixes: 69136f4e633 "radv/meta: add resolve pass using fragment/vertex shaders"
Signed-off-by: Bas Nieuwenhuizen
---
Build mesa 4331 completed
Commit 0d053014ac by Andres Gomez on 5/10/2017 9:06 PM:
cherry-ignore: rejected commits\n\nstable: rejected commits.\n\nSigned-off-by: Andres Gomez
Configure your notification preferences
Hello list,
The candidate for the Mesa 17.0.6 is now available. Currently we have:
- 57 queued
- 0 nominated (outstanding)
- and 4 rejected patch(es)
The current queue contains fixes in several places.
In Mesa Core we include a fix for validating that SSA references use
the same number of
---
src/intel/vulkan/anv_batch_chain.c | 23 +++
1 file changed, 11 insertions(+), 12 deletions(-)
diff --git a/src/intel/vulkan/anv_batch_chain.c
b/src/intel/vulkan/anv_batch_chain.c
index 13303b1..cc4f92e 100644
--- a/src/intel/vulkan/anv_batch_chain.c
+++
We use the look-up table mechanism for relocations so this isn't the
value we want. The correct value is filled out at execbuf2 time by
anv_cmd_buffer_process_relocs.
---
src/intel/vulkan/anv_batch_chain.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
One of the key invariants of the relocation system is the
presumed_offset field. The assumption is made that the value currently
in the address to be relocated agrees with the presumed_offset field.
If presumed_offset is equal to the offset of the BO, the kernel will
skip the relocation assuming
Note that for requests for Prime FDs or flink names, we return handles to
the etanviv BO, not the scanout BO. This is at least better than previous
behavior of returning GEM handles for a request for an FD or flink name.
And add an assert that renderonly_get_handle is only used for getting the
This patch series lets X start running with no patches and no
xorg.conf on the BCM Cygnus (pl111/vc4) platform, along with kmscube,
glmark2, etc.
Eric Anholt (2):
etnaviv: Only use renderonly_get_handle for GEM handles.
gallium: Add renderonly-based support for pl111+vc4.
.travis.yml
This follows the model of imx (display) and etnaviv (render): pl111 is a
display-only device, so when asked to do GL for it, we see if we have a
vc4 renderer, make the vc4 screen, and have vc4 call back to pl111 to do
scanout allocations.
The difference from etnaviv is that we share the same BO
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index 4132858..5d984ea 100644
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_query.c | 14 ++
src/gallium/drivers/radeon/r600_query.h | 5 ++---
2 files changed, 12 insertions(+), 7 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_query.c
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 23 +
src/gallium/drivers/radeon/r600_pipe_common.h | 11 +++-
src/gallium/drivers/radeonsi/si_descriptors.c | 34 -
3 files changed, 55 insertions(+), 13
From: Marek Olšák
---
src/gallium/drivers/radeonsi/si_pipe.c | 37 +++---
1 file changed, 34 insertions(+), 3 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c
b/src/gallium/drivers/radeonsi/si_pipe.c
index 53738a5..c7ca928
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_pipe_common.c | 6 --
src/gallium/drivers/radeon/r600_texture.c | 6 --
src/gallium/drivers/radeonsi/si_pipe.c| 2 +-
3 files changed, 9 insertions(+), 5 deletions(-)
diff --git
From: Marek Olšák
---
src/gallium/auxiliary/util/u_upload_mgr.c | 7 +++
src/gallium/auxiliary/util/u_upload_mgr.h | 7 +++
2 files changed, 14 insertions(+)
diff --git a/src/gallium/auxiliary/util/u_upload_mgr.c
b/src/gallium/auxiliary/util/u_upload_mgr.c
index
From: Marek Olšák
---
src/gallium/auxiliary/Makefile.sources |3 +
src/gallium/auxiliary/util/u_threaded_context.c| 2300
src/gallium/auxiliary/util/u_threaded_context.h| 349 +++
.../auxiliary/util/u_threaded_context_calls.h
Hi,
This series adds an optional module into gallium/util that wraps
around pipe_context and moves execution of all pipe_context calls into
a separate thread.
It puts a lot of new requirements on the driver, especially on thread-
safetiness of pipe_context functions, and even expects different
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 22 ++---
src/gallium/drivers/radeon/r600_pipe_common.h | 2 +-
src/gallium/drivers/radeon/r600_texture.c | 26 -
3 files changed, 25 insertions(+), 25
From: Marek Olšák
"tc" will be initialized by the next commit.
---
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
src/gallium/drivers/radeon/r600_query.c | 21 +
src/gallium/drivers/radeon/r600_query.h | 3 +++
3 files changed, 25
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 12 +++-
src/gallium/drivers/radeon/r600_pipe_common.c | 2 ++
src/gallium/drivers/radeon/r600_pipe_common.h | 1 +
3 files changed, 14 insertions(+), 1 deletion(-)
diff --git
From: Marek Olšák
State trackers can set this to tell the driver when u_threaded_context is
desirable.
---
src/gallium/include/pipe/p_defines.h | 8
src/mesa/state_tracker/st_manager.c | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git
From: Marek Olšák
---
src/gallium/drivers/radeon/r600_buffer_common.c | 16 ++--
src/gallium/drivers/radeon/r600_pipe_common.h | 4 ++--
src/gallium/drivers/radeon/r600_texture.c | 20 ++--
3 files changed, 22 insertions(+), 18
From: Marek Olšák
spotted randomly.
---
src/gallium/drivers/radeon/r600_buffer_common.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/r600_buffer_common.c
b/src/gallium/drivers/radeon/r600_buffer_common.c
index
On Tue, May 02, 2017 at 05:04:05PM -0700, Jason Ekstrand wrote:
> On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> wrote:
>
> > This will be used in conjunction with the buffer of clear values.
> >
> > Signed-off-by: Nanley Chery
> > ---
> >
On Wed, May 10, 2017 at 02:00:19PM -0700, Jason Ekstrand wrote:
> On Wed, May 10, 2017 at 1:35 PM, Nanley Chery wrote:
>
> > On Wed, May 10, 2017 at 12:38:50PM -0700, Jason Ekstrand wrote:
> > > On Wed, May 10, 2017 at 11:30 AM, Nanley Chery
> > >
---
src/intel/isl/isl_gen6.c | 30 --
1 file changed, 12 insertions(+), 18 deletions(-)
diff --git a/src/intel/isl/isl_gen6.c b/src/intel/isl/isl_gen6.c
index b746903..0de9620 100644
--- a/src/intel/isl/isl_gen6.c
+++ b/src/intel/isl/isl_gen6.c
@@ -88,6 +88,8 @@
The Ivy Bridge PRM provides a nice table that handles most of the
alignment cases in one place. For standard color buffers we have a
little freedom of choice but for most depth, stencil and compressed it's
hard-coded. Chad's original functions split halign and valign apart and
implemented them
---
src/intel/isl/isl_gen8.c | 193 +--
1 file changed, 53 insertions(+), 140 deletions(-)
diff --git a/src/intel/isl/isl_gen8.c b/src/intel/isl/isl_gen8.c
index 01500b8..cd7c703 100644
--- a/src/intel/isl/isl_gen8.c
+++ b/src/intel/isl/isl_gen8.c
@@
From: "Pohjolainen, Topi"
The reasoning Chad gave in the comment for choosing a valign of 4 is
entirely bunk. The fact that you have to multiply pitch by 2 is
completely unrelated to the halign/valign parameters used for texture
layout. (Not completely unrelated.
On Wed, May 10, 2017 at 09:14:06PM +0300, Pohjolainen, Topi wrote:
> On Tue, May 09, 2017 at 10:00:34AM -0700, Jason Ekstrand wrote:
> > The Ivy Bridge PRM provides a nice table that handles most of the
> > alignment cases in one place. For standard color buffers we have a
> > little freedom of
On Wed, May 10, 2017 at 1:35 PM, Nanley Chery wrote:
> On Wed, May 10, 2017 at 12:38:50PM -0700, Jason Ekstrand wrote:
> > On Wed, May 10, 2017 at 11:30 AM, Nanley Chery
> > wrote:
> >
> > > On Wed, May 03, 2017 at 02:24:19PM -0700, Jason Ekstrand
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/Makefile.sources | 1 +
src/gallium/drivers/radeon/radeon_vcn_dec.c | 672
src/gallium/drivers/radeon/radeon_vcn_dec.h | 3 +
3 files
On Wed, May 10, 2017 at 12:38:50PM -0700, Jason Ekstrand wrote:
> On Wed, May 10, 2017 at 11:30 AM, Nanley Chery
> wrote:
>
> > On Wed, May 03, 2017 at 02:24:19PM -0700, Jason Ekstrand wrote:
> > > On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> >
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_cs.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_cs.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 66 +
1 file changed, 66 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeonsi/si_uvd.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/si_uvd.c
b/src/gallium/drivers/radeonsi/si_uvd.c
index
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_winsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 72 +
1 file changed, 72 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/r600/r600_pipe.c | 2 +-
src/gallium/drivers/radeon/r600_pipe_common.c | 4 ++--
src/gallium/drivers/radeon/radeon_winsys.h| 2 +-
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/Makefile.sources | 1 +
src/gallium/drivers/radeon/radeon_vcn_dec.h | 501
2 files changed, 502 insertions(+)
create mode 100644
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 225
1 file changed, 225 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 22 +-
1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_winsys.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/gallium/drivers/radeon/radeon_winsys.h
b/src/gallium/drivers/radeon/radeon_winsys.h
index
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/gallium/winsys/amdgpu/drm/amdgpu_winsys.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 51 +
1 file changed, 51 insertions(+)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
Signed-off-by: Leo Liu
Reviewed-by: Christian König
---
src/gallium/drivers/radeon/radeon_vcn_dec.c | 197 +++-
1 file changed, 193 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c
You can always use a NULL BO but this is fine too.
Reviewed-by: Jason Ekstrand
On Wed, May 10, 2017 at 12:41 PM, Kenneth Graunke
wrote:
> We use Instruction State Base Address on Ironlake, so we want KSP to be
> an offset not an actual pointer.
On Wed, May 10, 2017 at 9:36 PM, Nils Wallménius
wrote:
> Hi Marek,
>
> A comment below
>
> Den 10 maj 2017 20:29 skrev "Marek Olšák" :
>
> From: Marek Olšák
>
> Cc: 17.1
> Reviewed-by: Alex
Hi Lucas,
2017-05-10 18:01 GMT+02:00 Lucas Stach :
> Use the proper pipe_resource_reference function instead of
> rolling our own.
Would it make sense to convert all gallium drivers using this pattern?
greets
--
Christian Gmeiner, MSc
It's actually not that much code.
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml| 2 +-
src/intel/genxml/gen5.xml | 2 +-
src/mesa/drivers/dri/i965/Makefile.sources| 1 -
This whole code is surrounded in #if GEN_GEN >= 6, and this code only
applies on Sandybridge. So, use GEN_GEN == 6 to reduce the delta in
the next patch, when we add Gen4-5 support.
---
src/mesa/drivers/dri/i965/genX_state_upload.c | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
We use Instruction State Base Address on Ironlake, so we want KSP to be
an offset not an actual pointer. Gen4/G45 use pointers.
---
src/intel/genxml/gen5.xml | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml
On Wed, May 10, 2017 at 11:30 AM, Nanley Chery
wrote:
> On Wed, May 03, 2017 at 02:24:19PM -0700, Jason Ekstrand wrote:
> > On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> > wrote:
> >
> > > Signed-off-by: Nanley Chery
>
Hi Marek,
A comment below
Den 10 maj 2017 20:29 skrev "Marek Olšák" :
From: Marek Olšák
Cc: 17.1
Reviewed-by: Alex Deucher
Reviewed-by: Nicolai Hähnle
---
https://bugs.freedesktop.org/show_bug.cgi?id=100201
Anonymous Helper changed:
What|Removed |Added
Resolution|--- |FIXED
Reviewed-by: Kristian H. Kristensen
On Wed, May 10, 2017 at 12:01 PM, Kenneth Graunke wrote:
> This was used by the meta fast clear code. Now that we've switched
> back to BLORP, it's always true.
>
> We might want it back when we add a RECTLIST
This was used by the meta fast clear code. Now that we've switched
back to BLORP, it's always true.
We might want it back when we add a RECTLIST extension to GL, but
that's someday in the future...
---
src/mesa/drivers/dri/i965/brw_context.c | 1 -
src/mesa/drivers/dri/i965/brw_context.h
Build mesa 4329 failed
Commit 0f34b674ed by Kenneth Graunke on 5/8/2017 5:50 AM:
i965: Switch BRW_NEW_CURBE_OFFSETS to BRW_NEW_PUSH_CONSTANT_ALLOCATION.\n\nThe BRW_NEW_CURBE_OFFSETS dirty bit is signalled when changing the\npartitioning of the Constant Buffer
Apparently, Nanhai made the Gen4-5 point size calculations round to the
nearest integer in commit 8d5231a3582e4f2769ac0685cf0174e09750700e,
"according to spec". When Eric first ported the driver to Sandybridge,
he did not implement this rounding.
In the GL 2.1 and 3.0 specs "Basic Point
This updates the Gen4-5 code to use a line end cap width of 0.5
for non-smooth lines, and 1.0 for smooth lines - which is what we
do on Gen6+.
---
src/mesa/drivers/dri/i965/brw_sf_state.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git
It's a U3.1. It became a U3.7 on Sandybridge.
---
src/intel/genxml/gen4.xml | 2 +-
src/intel/genxml/gen45.xml | 2 +-
src/intel/genxml/gen5.xml | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/src/intel/genxml/gen4.xml b/src/intel/genxml/gen4.xml
index
This effectively reverts Robert Ellison's 2009 commit
cc8afbd3862fedfe42e51c3774960d1c7078ec53.
I'm not seeing any GL spec text indicating that UPPER won't work.
On Gen6+, this bit moved to 3DSTATE_WM as a single bit, controlling
UPPER_LEFT vs. UPPER_RIGHT. There is no way to request
This unifies the Gen4-5 and Gen6+ line width calculations.
I believe it also fixes a bug - we weren't rounding the line width
to the nearest integer. The GL 4.5 (and GL 2.1) specs "Wide Lines"
section says:
"The actual width of non-antialiased lines is determined by rounding
the supplied width
Modern GL specifications say that the point size should be 1.0 when
gl_PointSize is unwritten and the last enabled stage is a geometry
or tessellation shader. If it's a vertex shader, though, both the
GL specs and ES 3.0 spec say that it's undefined - so since Gen4-5
only support vertex shaders,
On Wed, May 03, 2017 at 02:24:19PM -0700, Jason Ekstrand wrote:
> On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> wrote:
>
> > Signed-off-by: Nanley Chery
> > ---
> > src/intel/vulkan/genX_cmd_buffer.c | 93 ++
> >
From: Marek Olšák
Cc: 17.1
Reviewed-by: Alex Deucher
Reviewed-by: Nicolai Hähnle
---
src/amd/addrlib/gfx9/gfx9addrlib.cpp | 57
From: Marek Olšák
Cc: 17.1
Reviewed-by: Alex Deucher
Reviewed-by: Nicolai Hähnle
---
include/pci_ids/radeonsi_pci_ids.h| 2 ++
src/amd/common/amd_family.h
Seems more straightforward, but I don't know the rationale
why it was done the way it was.
Reviewed-By: Wladimir J. van der Laan
On Wed, May 10, 2017 at 06:01:08PM +0200, Lucas Stach wrote:
> From: Philipp Zabel
>
> Just increment the resource seqno
On Tue, May 02, 2017 at 05:15:46PM -0700, Jason Ekstrand wrote:
> On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> wrote:
>
> > Make the function take in an image instead of an image view. This
> > enables us to record relocations for surfaces states created outside of
> >
On Tue, May 09, 2017 at 10:00:34AM -0700, Jason Ekstrand wrote:
> The Ivy Bridge PRM provides a nice table that handles most of the
> alignment cases in one place. For standard color buffers we have a
> little freedom of choice but for most depth, stencil and compressed it's
> hard-coded. Chad's
Yes, good idea to do this in one place.
Reviewed-By: Wladimir J. van der Laan
On Wed, May 10, 2017 at 06:01:06PM +0200, Lucas Stach wrote:
> This way we can just test the feature bits and don't need to spread
> the debug overrides to all locations touching a feature.
>
>
On Tue, May 02, 2017 at 05:01:23PM -0700, Jason Ekstrand wrote:
> On Thu, Apr 27, 2017 at 11:32 AM, Nanley Chery
> wrote:
>
> > Signed-off-by: Nanley Chery
> > ---
> > src/intel/blorp/blorp.h | 9 ++
> > src/intel/blorp/blorp_clear.c
Reviewed-by: Marek Olšák
Marek
On Wed, May 10, 2017 at 10:27 AM, Michel Dänzer wrote:
> From: Michel Dänzer
>
> deregisterEHFrames doesn't take any parameters anymore.
>
> Signed-off-by: Michel Dänzer
>
Good catch!
Reviewed-By: Wladimir J. van der Laan
On Wed, May 10, 2017 at 06:01:04PM +0200, Lucas Stach wrote:
> PIPE_BUFFER is a target enum, not a binding. This caused the driver to
> up-align the height of buffer resources, leading to largely oversizing
> those resources.
From: Marek Olšák
for some reason, only scons can build these.
---
src/gallium/tests/graw/fs-fragcoord.c| 2 +-
src/gallium/tests/graw/fs-frontface.c| 2 +-
src/gallium/tests/graw/fs-test.c | 2 +-
src/gallium/tests/graw/fs-write-z.c | 2 +-
From: Varad Gautam
Signed-off-by: Varad Gautam
---
src/egl/drivers/dri2/egl_dri2.c | 6 ++
src/egl/main/eglapi.c | 1 +
2 files changed, 7 insertions(+)
diff --git a/src/egl/drivers/dri2/egl_dri2.c
From: Varad Gautam
query and return supported dmabuf format modifiers for
EGL_EXT_image_dma_buf_import_modifiers.
v2: rebase to master.
v3: move format check to the driver instead of making format queries
from here and then checking.
Signed-off-by: Varad Gautam
From: Varad Gautam
format modifiers tokens are driver specific, and hence, need to come
in from the driver. this allows drivers to be queried for supported
format modifiers for EGL_EXT_image_dma_buf_import_modifiers.
v2: rebase to master.
v3: drivers must return
From: Varad Gautam
ask the driver for supported modifiers for a given format.
bump __DRIimageExtension to 16.
v2: move to __DRIimageExtension v16.
v3: fail if the supplied format is not supported by driver.
v4: purge PIPE_CAP_QUERY_DMABUF_ATTRIBS.
Signed-off-by:
From: Varad Gautam
these allow querying the driver for supported dmabuf formats and
modifiers.
v2: move to __DRIimageExtension version 16.
v3: return GLBoolean for error reporting, document params better.
Signed-off-by: Varad Gautam
---
From: Varad Gautam
ask the driver for supported dmabuf formats
v2: rebase to master.
v3: return false on failure.
v4: use pscreen->is_format_supported instead of adding a new query.
(Lucas Stach)
Signed-off-by: Varad Gautam
---
From: Varad Gautam
allow egl clients to query the dmabuf formats supported on this platform.
v2: rebase to master.
v3: return EGL_FALSE upon failure.
Signed-off-by: Louis-Francis Ratté-Boulianne
Signed-off-by: Varad Gautam
From: Varad Gautam
allow creating EGLImages with dmabuf format modifiers when target is
EGL_LINUX_DMA_BUF_EXT for EGL_EXT_image_dma_buf_import_modifiers.
v2:
- clear modifier assembling and error label name (Eric Engestrom)
v3:
- remove goto jumps within
From: Varad Gautam
introduce modifier field in DRIimage and set it to
DRM_FORMAT_MOD_INVALID for now. support DRIimage modifier
queries.
Suggested-by: Daniel Stone
Signed-off-by: Varad Gautam
---
From: Varad Gautam
support importing dmabufs into DRIimage while taking format modifiers
in account, as per DRIimage extension version 15.
bump __DRIimageExtension to 15.
v2: initialize winsys modifier to DRM_FORMAT_MOD_INVALID (Daniel Stone)
Signed-off-by: Varad
One more time, from the top!
Hi all,
The v3 diverges somewhat form v2 while building upon the suggestions
received on earlier patchsets, and hence warrants a resend. Here's a
breakdown of patches in this series, and the changes since v2.
01 slightly reworks the multi-plane YUV import path in
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