On Thu, Jun 1, 2017 at 4:53 PM, Emil Velikov wrote:
> Should be handled now. See the documentation for future stable nominations
> [1].
Actually, I don't see the patch in 17.1.2, was it expected?
___
mesa-dev mailing list
Patches which need Rb's are 4-5, 56-57, 58.
Thanks.
On 06/09/2017 03:34 PM, Samuel Pitoiset wrote:
Hi,
Updated version of this patchset, hopefully it will be the last revision.
Major changes sinve v2:
- fix a refcount issue in mesa core for handles
- replace u_vector by util_dynarray
-
On 06/13/2017 04:23 PM, James Legg wrote:
On Fri, 2017-06-09 at 15:35 +0200, Samuel Pitoiset wrote:
v2: - rename st_bound_handle to st_bound_handles
Signed-off-by: Samuel Pitoiset
Reviewed-by: Nicolai Hähnle (v1)
Reviewed-by: Marek Olšák
v4: - use hash_table_u64 wrapper
v3: - do not use lookup_*_handle() in delete_*_handle()
- allocate _key on the stack for hash_table_search() wrapper
- add assertions in make_{texture,image}_handle_resident()
- remove useless casts in get_{texture,image}_handle
- fix refcounting
On 06/13/2017 06:07 PM, Nicolai Hähnle wrote:
On 13.06.2017 14:01, Grazvydas Ignotas wrote:
On Tue, Jun 13, 2017 at 10:58 AM, Samuel Pitoiset
wrote:
Needed for bindless handles which are represented using
64-bit unsigned integers. All hash table implementations
Hi,
On 13.06.2017 18:35, Ernst Sjöstrand wrote:
does GfxBench v4 work on RadeonSI at all?
GfxBench Manhattan, CarChase and tessellation tests require GL 4.x, its
other tests (like Driver2) work with GL 3.x. Public GUI version is
build with Qt.
Why it wouldn't work?
- Eero
https://bugs.freedesktop.org/show_bug.cgi?id=101378
--- Comment #3 from freedesk...@ca.sh13.net ---
Thanks a lot, couldn't have wished for another person to look into this :)
--
You are receiving this mail because:
You are the assignee for the bug.___
On 13.06.2017 14:01, Grazvydas Ignotas wrote:
On Tue, Jun 13, 2017 at 10:58 AM, Samuel Pitoiset
wrote:
Needed for bindless handles which are represented using
64-bit unsigned integers. All hash table implementations should
be uniformized later on.
Signed-off-by:
Hi,
does GfxBench v4 work on RadeonSI at all?
Regards
//Ernst
2017-06-13 16:50 GMT+02:00 Eero Tamminen :
> Hi,
>
> On 13.06.2017 16:23, Marek Olšák wrote:
>>
>> On Tue, Jun 13, 2017 at 3:24 PM, Eero Tamminen
>> wrote:
>>>
>>> On 13.06.2017
Reviewed-by: Marek Olšák
Marek
On Sun, Jun 11, 2017 at 3:52 PM, Boyan Ding wrote:
> Signed-off-by: Boyan Ding
> ---
> src/gallium/auxiliary/hud/hud_driver_query.c | 22 +++---
> 1 file changed, 19
On Tue, Jun 13, 2017 at 2:00 AM, Bas Nieuwenhuizen
wrote:
> With the unrelated line removed,
Same here.
Reviewed-by: Marek Olšák
Marek
>
> Reviewed-by: Bas Nieuwenhuizen
>
> On Tue, Jun 13, 2017 at 1:54 AM, Dave
On Tue, Jun 13, 2017 at 2:33 AM, Roland Scheidegger wrote:
> Am 13.06.2017 um 02:05 schrieb Ilia Mirkin:
>> On Mon, Jun 12, 2017 at 7:57 PM, Roland Scheidegger
>> wrote:
>>> FWIW surely on nv50 you could keep a single mad instruction for umad
>>> (sad
On Tue, Jun 13, 2017 at 4:12 PM, Roland Scheidegger wrote:
> Am 13.06.2017 um 15:11 schrieb Karol Herbst:
>> On Tue, Jun 13, 2017 at 2:18 PM, Roland Scheidegger
>> wrote:
>>> Am 13.06.2017 um 08:57 schrieb Karol Herbst:
On Tue, Jun 13, 2017 at 2:17
because buffers get unconditionally initialised by cpu writing.
Reviewed-by: Jason Ekstrand
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff
Reviewed-by: Jason Ekstrand
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.c| 4 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 3 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 47
Reviewed-by: Jason Ekstrand
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.c| 2 +
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 8 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 103
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.c | 24 ++--
1 file changed, 10 insertions(+), 14 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index
This is also earlier work in the list. Major difference is that
gen6 hiz is now based on the new "side-by-side" layout.
Topi Pohjolainen (8):
i965/miptree: Refactor isl aux usage resolver
i965/gen6: Use isl for hiz
i965/miptree: Refactor aux surface allocation
i965/miptree: Use isl for
Reviewed-by: Jason Ekstrand (v1)
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 64 +--
1 file changed, 41 insertions(+), 23 deletions(-)
diff --git
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.c| 4 +-
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 +-
src/mesa/drivers/dri/i965/gen6_depth_state.c | 6 +-
src/mesa/drivers/dri/i965/gen7_misc_state.c | 5
Now the last user of intel_miptree_get_aux_isl_surf() is gone.
Reviewed-by: Jason Ekstrand
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 5 +-
src/mesa/drivers/dri/i965/intel_mipmap_tree.c| 77
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++--
src/mesa/drivers/dri/i965/gen6_depth_state.c | 12 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 50 ++-
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 76 +++
1 file changed, 76 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 16
1 file changed, 16 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 32 +++
1 file changed, 28 insertions(+), 4 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index
This is part of earlier work in the list. Major difference is that
everything is now rebased on the new "side-by-side" stencil layout.
Topi Pohjolainen (15):
i965/miptree: Refactor mapping table alloc
i965: Add helper for converting isl tiling to bufmgr tiling
i965/miptree: Add isl surface
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 ++-
1 file changed, 38 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/gen6_depth_state.c | 31 +++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 ++
2 files changed, 19 insertions(+), 19 deletions(-)
diff --git
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 355f936f06..fee7c43d2c 100644
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 28 +--
1 file changed, 22 insertions(+), 6 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 19 ---
1 file changed, 16 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 +--
1 file changed, 27 insertions(+), 2 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_fbo.c | 33 ++---
1 file changed, 30 insertions(+), 3 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c
b/src/mesa/drivers/dri/i965/intel_fbo.c
index
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_blit.h | 13 +
1 file changed, 13 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_blit.h
b/src/mesa/drivers/dri/i965/intel_blit.h
index 2604417e2d..5e4d1f5eb4 100644
---
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index
Signed-off-by: Topi Pohjolainen
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 7acfcb87a4..8479b285cb 100644
Hi,
On 13.06.2017 16:23, Marek Olšák wrote:
On Tue, Jun 13, 2017 at 3:24 PM, Eero Tamminen
wrote:
On 13.06.2017 12:56, Marek Olšák wrote:
Everything is here:
git://people.freedesktop.org/~mareko/mesa state-optz
Didn't see any changes in benchmark suites that
On Fri, 2017-06-09 at 15:35 +0200, Samuel Pitoiset wrote:
> v2: - rename st_bound_handle to st_bound_handles
>
> Signed-off-by: Samuel Pitoiset
> Reviewed-by: Nicolai Hähnle (v1)
> Reviewed-by: Marek Olšák (v2)
> ---
>
Am 13.06.2017 um 15:11 schrieb Karol Herbst:
> On Tue, Jun 13, 2017 at 2:18 PM, Roland Scheidegger
> wrote:
>> Am 13.06.2017 um 08:57 schrieb Karol Herbst:
>>> On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger
>>> wrote:
I am actually also
On 06/12/2017 05:33 PM, Roland Scheidegger wrote:
Am 12.06.2017 um 21:19 schrieb Brian Paul:
On 06/12/2017 11:50 AM, Nicolai Hähnle wrote:
On 12.06.2017 19:37, Brian Paul wrote:
For the SAMPLE_POS and SAMPLE_INFO opcodes, clarify resource vs. render
target queries, range of postion values,
On 06/12/2017 10:55 AM, Marek Olšák wrote:
From: Marek Olšák
This bypasses _mesa_update_state_locked.
Before:
DrawElements ( 1 VBOs, 4 UBOs, 8 Tex) w/ stencil enable change:3.99
million
DrawArrays ( 1 VBOs, 4 UBOs, 8 Tex) w/ stencil enable change:4.56
On Tue, Jun 13, 2017 at 1:40 PM, Jose Fonseca wrote:
> On 12/06/17 22:56, Marek Olšák wrote:
>>
>> On Mon, Jun 12, 2017 at 10:43 PM, Jose Fonseca
>> wrote:
>>>
>>> On 12/06/17 21:25, Marek Olšák wrote:
On Mon, Jun 12, 2017 at 9:51 PM, Jose
On Tue, Jun 13, 2017 at 1:43 AM, Henri Verbeet wrote:
> On 11 June 2017 at 21:56, Marek Olšák wrote:
>> On Sun, Jun 11, 2017 at 8:25 PM, Henri Verbeet wrote:
>>> As someone downstream of this, I have to say I find the "family" names
>>>
On Tue, Jun 13, 2017 at 3:24 PM, Eero Tamminen
wrote:
> Hi,
>
> On 13.06.2017 12:56, Marek Olšák wrote:
>>
>> Everything is here:
>>
>> git://people.freedesktop.org/~mareko/mesa state-optz
>
>
> Didn't see any changes in benchmark suites that had tests which are
>
Hi,
On 13.06.2017 12:56, Marek Olšák wrote:
Everything is here:
git://people.freedesktop.org/~mareko/mesa state-optz
Didn't see any changes in benchmark suites that had tests which are
partially CPU bound. Everything was within variation on BYT, BSW, BDW,
BXT & SKL.
- Eero
On Tue, Jun 13, 2017 at 2:18 PM, Roland Scheidegger wrote:
> Am 13.06.2017 um 08:57 schrieb Karol Herbst:
>> On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger
>> wrote:
>>> I am actually also thinking this should be different.
>>>
>>> e.g. imho MAD
On Tue, Jun 13, 2017 at 8:47 AM, Martin Peres wrote:
>
>
> On 13/06/17 15:43, Ilia Mirkin wrote:
>>
>> On Tue, Jun 13, 2017 at 8:18 AM, Roland Scheidegger
>> wrote:
>>>
>>> Am 13.06.2017 um 08:57 schrieb Karol Herbst:
On Tue, Jun 13, 2017 at
On 13/06/17 15:43, Ilia Mirkin wrote:
On Tue, Jun 13, 2017 at 8:18 AM, Roland Scheidegger wrote:
Am 13.06.2017 um 08:57 schrieb Karol Herbst:
On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger wrote:
I am actually also thinking this should be
On Tue, Jun 13, 2017 at 8:18 AM, Roland Scheidegger wrote:
> Am 13.06.2017 um 08:57 schrieb Karol Herbst:
>> On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger
>> wrote:
>>> I am actually also thinking this should be different.
>>>
>>> e.g. imho MAD
Am 13.06.2017 um 08:57 schrieb Karol Herbst:
> On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger
> wrote:
>> I am actually also thinking this should be different.
>>
>> e.g. imho MAD means the operation can be either fused or unfused.
>> This is the "traditional" definition
On Tue, Jun 13, 2017 at 10:58 AM, Samuel Pitoiset
wrote:
> Needed for bindless handles which are represented using
> 64-bit unsigned integers. All hash table implementations should
> be uniformized later on.
>
> Signed-off-by: Samuel Pitoiset
Quoting Kenneth Graunke (2017-06-13 01:33:32)
> We can promote INVALIDATE_RANGE_BIT to INVALIDATE_BUFFER_BIT if the
> range contains the only valid data in the buffer. This allows us to
> orphan the storage, instead of doing stall avoidance blits.
> ---
>
Quoting Kenneth Graunke (2017-06-13 01:33:31)
> When writing a region of a buffer via glBufferSubData(), we can write
> the data asynchronously if the destination doesn't contain any data.
> Even if it's busy, the data was undefined, so the new data is fine too.
>
> Decreases the number of stall
Quoting Kenneth Graunke (2017-06-13 01:33:30)
Every alloc_buffer_object() is followed by marking the valid range. I
could not find a missed path, so
Reviewed-by: Chris Wilson
At some point, mesa with have to get an rbtree and then it will be
interesting to see if
Quoting Kenneth Graunke (2017-06-13 01:33:29)
> This doesn't do anything yet, but soon we'll want to know whether an
> access to a buffer section may write that data, or simply reads it.
This series doesn't got further than boolean, but would it be worth
feeding through map flags? The immediate
On 12/06/17 22:56, Marek Olšák wrote:
On Mon, Jun 12, 2017 at 10:43 PM, Jose Fonseca wrote:
On 12/06/17 21:25, Marek Olšák wrote:
On Mon, Jun 12, 2017 at 9:51 PM, Jose Fonseca wrote:
How does this help exactly?
Are applications actually rendering
2017-06-13 12:07 GMT+02:00 Michel Dänzer :
> On 13/06/17 06:51 PM, Timothy Arceri wrote:
>> On 13/06/17 19:22, Michel Dänzer wrote:
>>> From: Michel Dänzer
>>>
>>> It calling itself recursively prevented it from being inlined, resulting
>>> in a copy
On Thu 08 Jun 2017, Daniel Stone wrote:
> Hi,
> With full support for modifiers in DRIimage, this patch series adds
> support for fully plumbing them through X11. A patchset proposing
> an extension to DRI3 to support multiple planes and modifiers can
> be found here:
>
https://bugs.freedesktop.org/show_bug.cgi?id=101378
--- Comment #2 from Nicolai Hähnle ---
Thanks for the report. It does indeed look like this should be valid GLSL. I'm
looking into it.
--
You are receiving this mail because:
You are the assignee for the
On 13/06/17 06:51 PM, Timothy Arceri wrote:
> On 13/06/17 19:22, Michel Dänzer wrote:
>> From: Michel Dänzer
>>
>> It calling itself recursively prevented it from being inlined, resulting
>> in a copy being generated in every compilation unit referencing it. This
>>
Everything is here:
git://people.freedesktop.org/~mareko/mesa state-optz
Marek
On Tue, Jun 13, 2017 at 9:58 AM, Eero Tamminen
wrote:
> Hi,
>
> Do you have a branch I could check with our automation?
>
> On 13.06.2017 02:34, Marek Olšák wrote:
>>
>> Edmondo on IRC
Looks good to me. For the series
Reviewed-by: Nicolai Hähnle
On 12.06.2017 21:55, Brian Paul wrote:
I've since discovered the fragment shader sample mask system value (which
corresponds to gl_SampleMaskIn).
v2: It's a system value, not a shader input.
---
From: Michel Dänzer
It calling itself recursively prevented it from being inlined, resulting
in a copy being generated in every compilation unit referencing it. This
bloated the text segment of the Gallium mega-driver *_dri.so by ~5%,
and might also have impacted
On 13/06/17 19:22, Michel Dänzer wrote:
From: Michel Dänzer
It calling itself recursively prevented it from being inlined, resulting
in a copy being generated in every compilation unit referencing it. This
bloated the text segment of the Gallium mega-driver *_dri.so by
How about adding a comment which explains why we need that? This might
prevent someone to remove pipe_resource_next_reference() in the future
because these two functions are *quite* similar. :)
Other than, looks good to me.
On 06/13/2017 11:22 AM, Michel Dänzer wrote:
From: Michel Dänzer
From: Michel Dänzer
It calling itself recursively prevented it from being inlined, resulting
in a copy being generated in every compilation unit referencing it. This
bloated the text segment of the Gallium mega-driver *_dri.so by ~5%,
and might also have impacted
According to GLSL.std.450 spec, SmoothStep expects input to be a
floating-point type, but it does not restrict the bitsize.
Current implementation relies on inputs to be 32-bit.
This commit extends the support to 64-bit size inputs.
Reviewed by: Elie Tournier
---
v2: NIR fmax/fmin already handles NaN (Connor).
---
src/compiler/spirv/vtn_glsl450.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c
index 96e3407dee..1d7e2b8d95 100644
--- a/src/compiler/spirv/vtn_glsl450.c
+++
According to GLSL.std.450 spec, the operand for step() function must be
a floating-point. It does not restrict the value to 32-bit floats.
Reviewed by: Elie Tournier
---
src/compiler/nir/nir_opcodes.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
This short series of 3 patches extend a couple of functions SPIR-V functions to
support 64-bit, as well as it adds new functions defined in GLSL.450.std.
The first 2 commits add support for 64-bit float-point types in Step() and
SmoothStep().
The latest commit implement GLSL.std.450 NMin(),
On 06/13/2017 11:01 AM, Michel Dänzer wrote:
On 13/06/17 05:03 PM, Samuel Pitoiset wrote:
Fixes: 8ec4975cd83 ("st_glsl_to_tgsi: don't try and pass 32-bit values to
get_deref_offsets")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101401
Signed-off-by: Samuel Pitoiset
On Mon, 2017-06-12 at 10:27 -0700, Connor Abbott wrote:
> The nir fmax opcode already has the semantics you want wrt NaN's, or
> at least it should, no need to do all this csel stuff.
>
Thanks for the feedback. Didn't realize that indeed fmax (and fmin too)
already handle NaN.
I'll use them to
On 13.06.2017 10:01, Gert Wollny wrote:
Am Montag, den 12.06.2017, 21:00 +0200 schrieb Nicolai Hähnle:
Thanks for you comments, although I do not agree with most of them.
Okay. I think you should seriously re-think your algorithm in a way
that makes it a more natural evolution from the
On 13/06/17 05:03 PM, Samuel Pitoiset wrote:
> Fixes: 8ec4975cd83 ("st_glsl_to_tgsi: don't try and pass 32-bit values to
> get_deref_offsets")
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101401
> Signed-off-by: Samuel Pitoiset
The patch didn't apply
Fixes: 8ec4975cd83 ("st_glsl_to_tgsi: don't try and pass 32-bit values to
get_deref_offsets")
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101401
Signed-off-by: Samuel Pitoiset
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 ++--
1 file changed, 2
Am Montag, den 12.06.2017, 21:00 +0200 schrieb Nicolai Hähnle:
Thanks for you comments, although I do not agree with most of them.
>
> > Okay. I think you should seriously re-think your algorithm in a way
> > that makes it a more natural evolution from the algorithm that's
> > already there.
Needed for bindless handles which are represented using
64-bit unsigned integers. All hash table implementations should
be uniformized later on.
Signed-off-by: Samuel Pitoiset
---
src/util/hash_table.c | 149 ++
Hi,
Do you have a branch I could check with our automation?
On 13.06.2017 02:34, Marek Olšák wrote:
Edmondo on IRC reported that this series improves Civilization 5
performance and the improvement is not just tiny.
A potentially interesting synthetic test-case for this could be
"Driver2"
Reviewed-by: Samuel Iglesias Gonsálvez
On Thu, 2017-06-08 at 10:45 -0700, Jason Ekstrand wrote:
> ---
> src/intel/blorp/blorp_clear.c | 10 ++
> 1 file changed, 10 insertions(+)
>
> diff --git a/src/intel/blorp/blorp_clear.c
> b/src/intel/blorp/blorp_clear.c
>
On Mon, 2017-06-12 at 13:52 +0200, Samuel Iglesias Gonsálvez wrote:
> On Tue, 2017-06-06 at 21:59 -0700, Jason Ekstrand wrote:
> > This little series switches the GL driver to use BLORP for depth
> > and
> > stencil clears. BLORP has had depth/stencil clear support ever
> > since
> > we
> >
On Tue, Jun 13, 2017 at 2:17 AM, Roland Scheidegger wrote:
> I am actually also thinking this should be different.
>
> e.g. imho MAD means the operation can be either fused or unfused.
> This is the "traditional" definition of MAD - opencl for instance will
> follow this too,
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git
Should we add some asserts here to catch invalid values passed to these
functions?
Either way:
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 79
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
AMD SI-VI use this. GFX9 doesn't. We can stop doing this for SI-VI since
border color swizzling is broken there anyway. The only other user of this
code is nouveau.
Maybe move this comment into the code as a TODO?
On 06/12/2017 04:30 PM, Eric Engestrom wrote:
On Monday, 2017-06-12 09:39:15 +0300, Tapani Pälli wrote:
Hi Eric;
EGL_KHR_swap_buffers_with_damage is implemented by Android's EGL wrapper
library so these tests are passing already, no implementation required in
Mesa side.
Right, I keep
Reviewed-by: Timothy Arceri
On 13/06/17 04:18, Marek Olšák wrote:
From: Marek Olšák
---
src/mesa/state_tracker/st_atom_sampler.c | 24
1 file changed, 8 insertions(+), 16 deletions(-)
diff --git
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