[Mesa-dev] [Bug 100629] No mans sky renders white screen under wine in linux

https://bugs.freedesktop.org/show_bug.cgi?id=100629 --- Comment #4 from Giovanni ongaro --- i have noticed this on mesa git 4.5 Mesa 17.2.0-devel (git-d5a9608) it states compatibility profile 4.5 Still no mans sky doest work under wine staging -- You are receiving

Re: [Mesa-dev] [PATCH 0/6] i965: Add RGBX, RGBA configs, even on gen9

On Fri 16 Jun 2017, Chad Versace wrote: > On Thu 15 Jun 2017, Rob Herring wrote: > > While not i965, I tested the similar code and change in gallium. With > > the RGBA/RGBX formats at the end of the list I get: > > > > EGL-MAIN: Native format mismatch: 0x1 != 0x5 > > > > That's coming from

[Mesa-dev] [PATCH 1/5] egl/android: Declare loop vars inside their loops

That is, consistently do this: for (int i = 0; ...) No behavioral change. --- src/egl/drivers/dri2/platform_android.c | 32 ++-- 1 file changed, 14 insertions(+), 18 deletions(-) diff --git a/src/egl/drivers/dri2/platform_android.c

[Mesa-dev] [PATCH 4/5] egl/android: Pull invariant var outside of loop

This makes the nested loops in droid_add_configs_for_visuals() easier to read. No behavioral change. --- src/egl/drivers/dri2/platform_android.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/egl/drivers/dri2/platform_android.c

[Mesa-dev] [PATCH 5/5] egl/android: Change order of EGLConfig generation

Many Android apps (such as Google's official NDK GLES2 example app), and even portions the core framework code (such as SystemServiceManager in Nougat), incorrectly choose their EGLConfig. They neglect to match the EGLConfig's EGL_NATIVE_VISUAL_ID against the window's native format, and instead

[Mesa-dev] [PATCH 3/5] egl/android: Rename var in droid_add_configs_for_visuals()

Rename 'config' to 'config_count'. I didn't understand what the variable did until I untangled the for-loops. Now the next person won't have that problem. --- src/egl/drivers/dri2/platform_android.c | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 2/5] egl/android: Declare 'const' the EGLConfig attribs template array

No behavioral change. Just a cleanup. Post-patch, we no longer modify the same array on each iteration of the inner loop of droid_add_configs_for_visuals(). Instead, we just declare the array as const inside the inner loop. --- src/egl/drivers/dri2/platform_android.c | 16 +++- 1

[Mesa-dev] [PATCH 0/5] egl/android: Change order of EGLConfig generation

Patches 1-4 are little cleanups. The real change is in patch 5. I wrote this series while debugging issues that Rob Herring found [1] while testing my i965 RGBX patch series [2]. *This* patch series fixes those errors, and is also independent of my RGBX series. [1]:

[Mesa-dev] [Bug 101475] Max Core Profile for OpenGL showing 0.0

https://bugs.freedesktop.org/show_bug.cgi?id=101475 vinf...@gmail.com changed: What|Removed |Added Status|NEEDINFO|NEW --- Comment #4 from

[Mesa-dev] [Bug 101475] Max Core Profile for OpenGL showing 0.0

https://bugs.freedesktop.org/show_bug.cgi?id=101475 --- Comment #3 from vinf...@gmail.com --- glxinfo | grep renderer returns: GLX_MESA_multithread_makecurrent, GLX_MESA_query_renderer, GLX_MESA_multithread_makecurrent, GLX_MESA_query_renderer, Extended renderer info

[Mesa-dev] [Bug 101475] Max Core Profile for OpenGL showing 0.0

https://bugs.freedesktop.org/show_bug.cgi?id=101475 --- Comment #2 from Dylan Baker --- Also, are you sure you're running 17.0.0-rc1? That is a very old release candidate, if you are running that you should update to 17.1.2. -- You are receiving this mail because: You

[Mesa-dev] [Bug 101475] Max Core Profile for OpenGL showing 0.0

https://bugs.freedesktop.org/show_bug.cgi?id=101475 Dylan Baker changed: What|Removed |Added Status|NEW |NEEDINFO ---

[Mesa-dev] [Bug 101475] Max Core Profile for OpenGL showing 0.0

https://bugs.freedesktop.org/show_bug.cgi?id=101475 Bug ID: 101475 Summary: Max Core Profile for OpenGL showing 0.0 Product: Mesa Version: 17.1 Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW

[Mesa-dev] [PATCH 09/18] i965: Make a helper function for depth/stencil related state.

From: Kenneth Graunke Gen4-5 basically glue DEPTH_STENCIL_STATE, COLOR_CALC_STATE, and BLEND_STATE together into a single COLOR_CALC_STATE structure. By making a helper function, we'll be able to reuse it when filling out Gen4-5 COLOR_CALC_STATE without replicating any

[Mesa-dev] [PATCH 13/18] i965: Convert BLEND_CONSTANT_COLOR state to genxml.

It's a very simple conversion, and it allows us to delete brw_cc.c. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/Makefile.sources| 1 - src/mesa/drivers/dri/i965/brw_cc.c| 62 ---

[Mesa-dev] [PATCH 18/18] i965: Convert WM_STATE to genxml on gen4-5.

The code doesn't get exactly a lot simpler but at least it is in a single place, and we delete more than we add. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/Makefile.sources| 1 - src/mesa/drivers/dri/i965/brw_state.h | 1 -

[Mesa-dev] [PATCH 11/18] i965: Check for alpha channel just like in gen6+.

gen6+ uses _mesa_base_format_has_channel() to check for the alpha channel, while gen4-5 use ctx->DrawBuffer->Visual.alphaBits. By using _mesa_base_format_has_channel() here we keep the same behavior accross all gen. While initially both ways of checking the alpha channel seemed correct to me,

[Mesa-dev] [PATCH 16/18] i965: Convert GS_STATE to genxml.

Merge the code with gen6+ 3DSTATE_GS, and delete brw_gs_state.c, together with brw_gs_unit_state. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/Makefile.sources| 1 - src/mesa/drivers/dri/i965/brw_gs_state.c | 101

[Mesa-dev] [PATCH 08/18] intel/genxml: Use the same naming convention for Floating Point Mode.

In newer gens, this field has a prefix and the non-I-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli --- src/intel/genxml/gen6.xml | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 17/18] i965: Convert CLIP_STATE to genxml.

The code doesn't get exactly a lot simpler but at least it is in a single place, and we delete more than we add. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/Makefile.sources| 1 - src/mesa/drivers/dri/i965/brw_clip_state.c| 147

[Mesa-dev] [PATCH 06/18] intel/genxml: Rename field on WM_STATE to match gen6+.

"Pixel Shader Kill Pixel" -> "Pixel Shader Kills Pixel", which is how it's called on newer gens. Signed-off-by: Rafael Antognolli --- src/intel/genxml/gen4.xml | 2 +- src/intel/genxml/gen45.xml | 2 +- src/intel/genxml/gen5.xml

[Mesa-dev] [PATCH 05/18] intel/genxml: Normalize fields on WM_STATE.

On gen4, WM_STATE only has one Kernel Start Pointer and one GRF Register Count, but we can make the code that handles this on multiple gens simpler if we add an index 0 to it too. Signed-off-by: Rafael Antognolli --- src/intel/genxml/gen4.xml | 4

[Mesa-dev] [PATCH 07/18] intel/genxml: Normalize URB Data field in WM_STATE.

On gen6+, this is called "Dispatch GRF Start Register For Constant/Setup Data 0", while on gen5 and lower it's called only "Dispatch GRF Start Register For URB Data", but it's essentially the same thing (URB data), so rename it to match newer gens and simplify the C code that handles it.

[Mesa-dev] [PATCH 14/18] i965: Remove upload_gs_state_for_tf.

This function only emits a particular case of 3DSTATE_GS. Instead, we can do that inside genX(upload_gs_state), and later reuse part of that code for emitting gen4-5 state. There's the additional benefit of allowing us to remove gen6_gs_state.c, which was only left because of this function.

[Mesa-dev] [PATCH 15/18] i965: Prepare gs_state emitting code to include gen4-5.

Since we always call brw_batch_emit anyways, we can hopefully make things simpler by calling it only once, and then branching inside its body. This can be helpful when bringing the gen4-5 code into this function. Additionally, check for GEN_GEN == 6 instead of < 7 in cases that won't apply to

[Mesa-dev] [PATCH 02/18] intel/genxml: Add missing fields to CLIP_STATE on gen4-5.

These fields are set by brw_clip_unit, so we need them when converting to genxml. Signed-off-by: Rafael Antognolli --- src/intel/genxml/gen45.xml | 1 + src/intel/genxml/gen5.xml | 1 + 2 files changed, 2 insertions(+) diff --git a/src/intel/genxml/gen45.xml

[Mesa-dev] [PATCH 04/18] intel/genxml: Add missing field to CLIP_STATE.

Just because it's not set doesn't mean that it doesn't exist. And since the field is there on newer gens, having it on gen5 simplifies the code when porting gen5 and lower. Also add missing value to API Mode on CLIP_STATE on gen4. Signed-off-by: Rafael Antognolli

[Mesa-dev] [PATCH 10/18] i965: Make a helper function for blend entry related state.

Add a helper function to reuse code that fills blend entry related state, and make genX(upload_blend_state) use it. This function can later be used by gen4-5 color calc state to set the blend related bits. Signed-off-by: Rafael Antognolli ---

[Mesa-dev] [PATCH 01/18] intel/genxml: Normalize GS_STATE.

Rename "Rendering Enable" to "Rendering Enabled", so it matches gen6+. Signed-off-by: Rafael Antognolli --- src/intel/genxml/gen5.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/genxml/gen5.xml b/src/intel/genxml/gen5.xml index

[Mesa-dev] [PATCH 03/18] intel/genxml: Fix type of UserClipFlags ClipTest Enable Bitmask.

This is a bitmask, so it can't be a boolean. Also rename it so it matches gen6+. Signed-off-by: Rafael Antognolli --- src/intel/genxml/gen4.xml | 2 +- src/intel/genxml/gen45.xml | 2 +- src/intel/genxml/gen5.xml | 2 +- 3 files changed, 3 insertions(+), 3

[Mesa-dev] [PATCH 12/18] i965: Convert CC state on gen4-5 to genxml.

Use set_blend_entry_bits and set_depth_stencil_bits to fill most of the color calc struct, and then manually update the rest. Signed-off-by: Rafael Antognolli --- src/mesa/drivers/dri/i965/brw_cc.c| 174 --

Re: [Mesa-dev] [PATCH 2/2] svga: add new num-failed-allocations HUD query

For the series, Reviewed-by: Neha Bhende Regards, Neha From: Brian Paul Sent: Friday, June 16, 2017 3:39:12 PM To: mesa-dev@lists.freedesktop.org Cc: Charmaine Lee; Neha Bhende Subject: [PATCH 2/2] svga: add new

Re: [Mesa-dev] [PATCH 9/9] i965: Fall back to normal blorp clear instead of meta clear

On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > When intel_miptree_alloc_non_msrt_mcs fails, fall back to normal blorp > color clear instead of falling back to meta. With this change, > brw_blorp_clear_color can

Re: [Mesa-dev] [PATCH 8/9] intel/blorp: Apply source offset in the TEX case

Reviewed-by: Jason Ekstrand On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > Previously the offset was only applied in the TXF case. > > Signed-off-by: Ian Romanick >

Re: [Mesa-dev] [PATCH 7/9] intel/blorp: Apply Gen4 coord. normalization after cubemap sizes are adjusted

Reviewed-by: Jason Ekstrand On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > Otherwise the values used for coordinate normalization use the wrong > sizes. > > Signed-off-by: Ian Romanick

Re: [Mesa-dev] [PATCH 4/9] meta/blit: Silence unused parameter warning

Reviewed-by: Jason Ekstrand On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > drivers/common/meta_blit.c: In function ‘setup_glsl_msaa_blit_scaled_ > shader’: > drivers/common/meta_blit.c:62:58:

Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemaps

I probably shouldn't review a patch that says it's from me, but why not Reviewed-by: Jason Ekstrand On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Jason Ekstrand > > We call convert_to_single_slice so they

Re: [Mesa-dev] [PATCH 3/9] meta: Silence unused parameter warning

Reviewed-by: Jason Ekstrand On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > drivers/common/meta.c:2694:71: warning: unused parameter ‘dims’ > [-Wunused-parameter] >

Re: [Mesa-dev] [PATCH 2/9] genxml: Silence about a billion unused parameter warnings

On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > Signed-off-by: Ian Romanick > --- > src/intel/genxml/gen_pack_header.py | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff

Re: [Mesa-dev] [PATCH 1/9] i965: Fix incorrect comment

Reviewed-by: Jason Ekstrand On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick wrote: > From: Ian Romanick > > There is no intel_miptree_slice_has_hiz function, but there is a > intel_miptree_level_has_hiz function. I assume

Re: [Mesa-dev] [PATCH 5/9] i965/urb: Trigger upload_urb on NEW_BLORP

Technically, this isn't actually a problem because blorp manually whacks BRW_NEW_URB_SIZE. That said, triggering on NEW_BLORP is a better plan anyway. With this patch, we can probably remove the line from blorp where it sets NEW_URB_SIZE. On Fri, Jun 16, 2017 at 2:01 PM, Ian Romanick

[Mesa-dev] [PATCH 29/30] i965/miptree: More conservatively resolve external images

Instead of always doing a full resolve, only resolve the bits that are needed. This means that we only do a partial resolve when the miptree modifier is I915_FORMAT_MOD_Y_TILED_CCS. --- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 37

[Mesa-dev] [PATCH 22/30] i965/screen: Drop get_tiled_height

It's no longer used. --- src/mesa/drivers/dri/i965/intel_screen.c | 20 +++- 1 file changed, 3 insertions(+), 17 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index a896bc4..94787ff 100644 ---

[Mesa-dev] [PATCH 27/30] i965/screen: Support import and export of surfaces with CCS

--- src/mesa/drivers/dri/i965/intel_screen.c | 55 +--- 1 file changed, 50 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 94787ff..7d6adb7 100644 ---

[Mesa-dev] [Bug 101471] Mesa fails to build: unknown typename bool

https://bugs.freedesktop.org/show_bug.cgi?id=101471 --- Comment #3 from Christoph Haag --- Well, the cause was https://cgit.freedesktop.org/mesa/mesa/commit/?id=81945ded0dc3d25d55eaf682dce220fa4c2de9fe On the mailing list I saw a v3, but the commit was v2, so maybe

[Mesa-dev] [PATCH 28/30] i965: Pretend that CCS modified images are two planes

From: Ben Widawsky v2: move is_aux into if block. (Jason) Use else block instead of goto (Jason) v3: Fix up logic for is_aux (Ben) Fix up size calculations and add FIXME (Ben) v4 (Jason Ekstrand): Use the aux_pitch in the image instead of calculating it Cc: Jason Ekstrand

[Mesa-dev] [PATCH 26/30] intel/isl: Add a row_pitch parameter to surf_get_ccs_surf

--- src/intel/isl/isl.c | 4 +++- src/intel/isl/isl.h | 3 ++- src/intel/vulkan/anv_image.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 +--- 4 files changed, 11 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 23/30] intel/isl: Add support for I915_FORMAT_MOD_Y_TILED_CCS

--- src/intel/isl/isl_drm.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/intel/isl/isl_drm.c b/src/intel/isl/isl_drm.c index 1dc3da2..e2e873d 100644 --- a/src/intel/isl/isl_drm.c +++ b/src/intel/isl/isl_drm.c @@ -52,6 +52,10 @@ isl_tiling_to_i915_tiling(enum isl_tiling

[Mesa-dev] [PATCH 24/30] i965: Support images with aux buffers

From: Ben Widawsky Previously images did not support any auxiliary compression surfaces (CCS, MCS, or HiZ). That's about to change. This patch just adds the fields to __DRIimageRec to make auxiliary surfaces possible. v2 (Jason Ekstrand): - Add an aux_pitch parameter as

[Mesa-dev] [PATCH 10/30] i965: Use miptree_create_for_dri_image in image_target_renderbuffer_storage

--- src/mesa/drivers/dri/i965/intel_fbo.c | 23 +-- 1 file changed, 1 insertion(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 6a64bcb..f1a997b 100644 --- a/src/mesa/drivers/dri/i965/intel_fbo.c +++

[Mesa-dev] [PATCH 25/30] i965/miptree: Allocate mcs_buf for an image's CCS

From: Ben Widawsky This code will disable actually creating these buffers for the scanout, but it puts the allocation in place. Primarily this patch is split out for review, it can be squashed in later if preferred. v2: assert(mt->offset == 0) in ccs creation (as requested

[Mesa-dev] [PATCH 30/30] i965: Advertise the CCS modifier

From: Ben Widawsky v2: Rename modifier to be more smart (Jason) FINISHME: Use the kernel's final choice for the fb modifier bwidawsk@norris2:~/intel-gfx/kmscube (modifiers $) ~/scripts/measure_bandwidth.sh ./kmscube none Read bandwidth: 603.91 MiB/s Write bandwidth: 615.28

[Mesa-dev] [PATCH 20/30] i965/screen: Use ISL for allocating image BOs

--- src/mesa/drivers/dri/i965/intel_screen.c | 51 ++-- 1 file changed, 29 insertions(+), 22 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 3cf10b8..e5acd31 100644 ---

[Mesa-dev] [PATCH 21/30] i965/screen: Use ISL for doing image import checks

--- src/mesa/drivers/dri/i965/intel_screen.c | 32 1 file changed, 28 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index e5acd31..a896bc4 100644 ---

[Mesa-dev] [PATCH 18/30] intel/isl: Add basic modifier introspection

--- src/intel/Makefile.am | 1 + src/intel/Makefile.sources | 1 + src/intel/isl/isl.h| 22 + src/intel/isl/isl_drm.c| 59 ++ 4 files changed, 83 insertions(+) create mode 100644 src/intel/isl/isl_drm.c diff --git

[Mesa-dev] [PATCH 16/30] i965/miptree: Move CCS allocation into create_for_dri_image

Any form of CCS on gen9+ only works on Y-tiled images. The only caller of create_for_bo which uses Y-tiled BOs is create_for_dri_image. --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 25 - 1 file changed, 12 insertions(+), 13 deletions(-) diff --git

[Mesa-dev] [PATCH 14/30] i965/miptree: Add support for window system images to create_for_dri_image

We want to start using create_for_dri_image for all miptrees created from __DRIimage, including those which come from a window system. In order to allow for fast clears to still work on window system buffers, we need to allow for creating aux surfaces. --- src/mesa/drivers/dri/i965/intel_fbo.c

[Mesa-dev] [PATCH 13/30] i965/miptree: Add an explicit format parameter to create_for_dri_image

--- src/mesa/drivers/dri/i965/intel_fbo.c | 3 ++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 7 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 3 ++- src/mesa/drivers/dri/i965/intel_tex_image.c | 3 ++- 4 files changed, 10 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 17/30] i965: Add an isl_device to intel_screen

--- src/mesa/drivers/dri/i965/brw_context.c | 2 +- src/mesa/drivers/dri/i965/intel_screen.c | 3 +++ src/mesa/drivers/dri/i965/intel_screen.h | 4 3 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c

[Mesa-dev] [PATCH 04/30] i965: Clamp clear colors to the representable range

Starting with Sky Lake, we can clear to arbitrary floats or integers. Unfortunately, the hardware isn't particularly smart when it comes sampling from that clear color. If the clear color is out of range for the surface format, it will happily return whatever we put in the surface state packet

[Mesa-dev] [PATCH 12/30] i965/miptree: Allocate mt earlier in update winsys

From: Ben Widawsky Allows us to continue utilizing common miptree creation using __DRIimage without creating a new DRIimage (for the intel_process_dri2_buffer() case). This is a bit ugly, but I think it's the best one can do. v2: This patch let's us remove the temporary

[Mesa-dev] [PATCH 09/30] i965/miptree: Set level_x/h in create_for_dri_image

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index a1be37e..6e94ba3 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++

[Mesa-dev] [PATCH 02/30] i965/miptree: Rename the non_msrt_mcs functions to _ccs

While we're here, we also make the two support checks static since there are no users outside intel_mipmap_tree.c. --- src/mesa/drivers/dri/i965/brw_blorp.c | 2 +- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 45 +--

[Mesa-dev] [PATCH 03/30] i965: Don't bother with HiZ in renderbuffer_move_to_temp

This function is only used on gen4-5 which don't support HiZ. --- src/mesa/drivers/dri/i965/intel_fbo.c | 4 1 file changed, 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index 864ff32..ee4aba9 100644 ---

[Mesa-dev] [PATCH 01/30] i965/miptree: Delete the layered rendering resolve

We never fast-clear more than the base slice (LOD 0, layer 0) anyway, so layered rendering without a resolve is always perfectly safe. Should this ever change in the future, we'll have to put some sort of resolve back in but we can cross that bridge when we come to it. ---

[Mesa-dev] [PATCH 19/30] intel/isl: Add a helper to convert tilings fro ISL to i915

--- src/intel/isl/isl.h | 3 +++ src/intel/isl/isl_drm.c | 23 +++ 2 files changed, 26 insertions(+) diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h index eb05b54..dc3eada 100644 --- a/src/intel/isl/isl.h +++ b/src/intel/isl/isl.h @@ -1513,6 +1513,9 @@

[Mesa-dev] [PATCH 08/30] i965/miptree: Add tile_x/y to total_width/height

This is what we do in intel_image_target_renderbuffer_storage and it makes more sense than stomping them. Because the image gets created as a 2D image with one miplevel, they should already be equal to the provided width/height. Adding the tile offset makes some sense depending on how you

[Mesa-dev] [PATCH 15/30] i965: Use create_for_dri_image in intel_update_image_buffer

--- src/mesa/drivers/dri/i965/brw_context.c | 11 ++- 1 file changed, 2 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_context.c b/src/mesa/drivers/dri/i965/brw_context.c index f57045f..9a55e44 100644 --- a/src/mesa/drivers/dri/i965/brw_context.c +++

[Mesa-dev] [PATCH 11/30] i965/miptree: Add a return for updating of winsys

From: Ben Widawsky There is nothing particularly useful to do currently if the update fails, but there is no point carrying on either. As a result, this has a behavior change. v2: Make the return type a bool (Topi) v3: Don't leak the bo if update_winsys_renderbuffer fails.

[Mesa-dev] [PATCH 06/30] i965: Move the DRIimage -> miptree code to intel_mipmap_tree.c

This is mostly a direct port. The only bit of refactoring that was done was to make creating a planar miptree be an early return from the non-planar case. Alternatively, we could have three functions: two helpers and a main function to just call the right helper. Making the planar case an early

[Mesa-dev] [PATCH 05/30] i965/miptree: Rework aux enabling

This commit replaces the complex and confusing set of disable flags with two fairly straightforward fields which describe the intended auxiliary surface usage and whether or not the miptree supports fast clears. Right now, supports_fast_clear can be entirely derived from aux_usage but that will

[Mesa-dev] [PATCH 00/30] i965: Add support for I915_FORMAT_MOD_Y_TILED_CCS

This series is a rework of Ben's series to enable the CCS format modifier. It started as an attempt to rebase his original patches on top of my resolve reworks inside the miptree code. However, as I started to dive deeper, I found a number of subtle issues: 1) Thanks to the terrible set of

[Mesa-dev] [PATCH 07/30] i965/miptree: Pass the offset into create_for_bo in create_for_dri_image

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 023c6aa..3bc6827 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 2/2] svga: add new num-failed-allocations HUD query

This counter is incremented if we fail to allocate memory for vertex/index/const buffers, textures, etc. --- src/gallium/drivers/svga/svga_context.h| 1 + src/gallium/drivers/svga/svga_pipe_query.c | 7 +++ src/gallium/drivers/svga/svga_resource.c | 17 +++--

[Mesa-dev] [PATCH 1/2] gallium/hud: support GALLIUM_HUD_DUMP_DIR feature on Windows

Use a dummy implementation of the access() function. Use \ path separator. Add a few comments. --- src/gallium/auxiliary/hud/hud_context.c | 36 +++-- 1 file changed, 30 insertions(+), 6 deletions(-) diff --git a/src/gallium/auxiliary/hud/hud_context.c

Re: [Mesa-dev] [PATCH 1/3] ac: resolve conflicts introduced with "ac: remove amdgpu.h dependency"

The series is Reviewed-by: Bas Nieuwenhuizen Tested-by: Bas Nieuwenhuizen On Fri, Jun 16, 2017 at 10:09 PM, Emil Velikov wrote: > From: Emil Velikov > > The commit did not add the

Re: [Mesa-dev] [PATCH v3 06/10] gallium/docs: add precise instruction modifier

While you're at it, you could also add something to TGSI_OPCODE_MAD itself, that it can be either fused or unfused, whatever is fastest. But either way, Reviewed-by: Roland Scheidegger Signed-off-by: Karol Herbst

[Mesa-dev] [Bug 101471] Mesa fails to build: unknown typename bool

https://bugs.freedesktop.org/show_bug.cgi?id=101471 --- Comment #2 from Emil Velikov --- The following series should do it. Please let me know how if it helps on your end. https://patchwork.freedesktop.org/series/25934/ -- You are receiving this mail because: You are

Re: [Mesa-dev] [PATCH] svga: add some missing SVGA_STATS_* enum values, prefix strings

Reviewed-by: Charmaine Lee From: Brian Paul Sent: Friday, June 16, 2017 12:21 PM To: mesa-dev@lists.freedesktop.org Cc: Charmaine Lee; Neha Bhende Subject: [PATCH] svga: add some missing SVGA_STATS_* enum values,

Re: [Mesa-dev] [PATCH] i965: Ignore anisotropic filtering in nearest mode.

On Friday, June 16, 2017 1:39:47 PM PDT Dylan Baker wrote: > From: Kenneth Graunke > > This fixes both Europa Universalis IV and Steallirs rendering on i965. > This was tested on SKL. > > This fix was discovered by Jakub Szuppe at Stream HPC > (https://streamhpc.com/). >

[Mesa-dev] [PATCH 4/9] meta/blit: Silence unused parameter warning

From: Ian Romanick drivers/common/meta_blit.c: In function ‘setup_glsl_msaa_blit_scaled_shader’: drivers/common/meta_blit.c:62:58: warning: unused parameter ‘filter’ [-Wunused-parameter] GLenum target, GLenum filter)

[Mesa-dev] [PATCH 2/9] genxml: Silence about a billion unused parameter warnings

From: Ian Romanick Signed-off-by: Ian Romanick --- src/intel/genxml/gen_pack_header.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/genxml/gen_pack_header.py b/src/intel/genxml/gen_pack_header.py index

[Mesa-dev] [PATCH 8/9] intel/blorp: Apply source offset in the TEX case

From: Ian Romanick Previously the offset was only applied in the TXF case. Signed-off-by: Ian Romanick Suggested-by: Jason Ekstrand --- src/intel/blorp/blorp_blit.c | 3 +++ 1 file changed, 3 insertions(+) diff

[Mesa-dev] [PATCH 7/9] intel/blorp: Apply Gen4 coord. normalization after cubemap sizes are adjusted

From: Ian Romanick Otherwise the values used for coordinate normalization use the wrong sizes. Signed-off-by: Ian Romanick Suggested-by: Jason Ekstrand --- src/intel/blorp/blorp_blit.c | 20 +++- 1

[Mesa-dev] [PATCH 3/9] meta: Silence unused parameter warning

From: Ian Romanick drivers/common/meta.c:2694:71: warning: unused parameter ‘dims’ [-Wunused-parameter] copytexsubimage_using_blit_framebuffer(struct gl_context *ctx, GLuint dims, ^~~~

[Mesa-dev] [PATCH 9/9] i965: Fall back to normal blorp clear instead of meta clear

From: Ian Romanick When intel_miptree_alloc_non_msrt_mcs fails, fall back to normal blorp color clear instead of falling back to meta. With this change, brw_blorp_clear_color can never fail. Signed-off-by: Ian Romanick ---

[Mesa-dev] [PATCH 1/9] i965: Fix incorrect comment

From: Ian Romanick There is no intel_miptree_slice_has_hiz function, but there is a intel_miptree_level_has_hiz function. I assume that's the correct one to use. Signed-off-by: Ian Romanick --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h

[Mesa-dev] [PATCH 5/9] i965/urb: Trigger upload_urb on NEW_BLORP

From: Jason Ekstrand It's a bit rare, but blorp can trigger a urb reconfiguration. When that happens, we need to re-upload the URB config. Fortunately, this isn't as bad as it looks because gen7_upload_urb will not re-emit the packet if it would end up being a no-op

[Mesa-dev] [PATCH 6/9] intel/blorp: Set needs_(dst|src)_offset for Gen4 cubemaps

From: Jason Ekstrand We call convert_to_single_slice so they may end up with a non-trivial offset that needs to be taken into account. v2 (idr): Also set needs_src_offset. Suggested by Jason. Fixes

Re: [Mesa-dev] [PATCH] i965: Ignore anisotropic filtering in nearest mode.

Quoting Dylan Baker (2017-06-16 13:39:47) > From: Kenneth Graunke > > This fixes both Europa Universalis IV and Steallirs rendering on i965. ^ I fixed this typo locally, I just forgot to commit it before I send this :/ >

[Mesa-dev] [PATCH] i965: Ignore anisotropic filtering in nearest mode.

From: Kenneth Graunke This fixes both Europa Universalis IV and Steallirs rendering on i965. This was tested on SKL. This fix was discovered by Jakub Szuppe at Stream HPC (https://streamhpc.com/). bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96958 bugzilla:

[Mesa-dev] [PATCH 1/2] glsl: allow inputs in interface blocks in interpolateAt*

From: Nicolai Hähnle Since interface blocks are simply considered groupings of input variables, this is allowed. var->data.must_be_shader_input is now determined on-the-fly after lowering interface blocks, since we don't want to disable varying packing for an entire

[Mesa-dev] [PATCH 2/2] radeonsi: support indirect indexing in INTERP_* opcodes

From: Nicolai Hähnle The hardware doesn't support it, so we just interpolate all array elements and then use indirect indexing on the resulting vector. Clearly, this is not very efficient. There is an argument to be had for adding if/else, or perhaps even pulling the

[Mesa-dev] [PATCH 0/2] glsl,radeonsi: interpolateAt* fixes

Hi all, Two fixes related to interpolateAt* functions: allowing inputs in interface blocks, and fixing dynamic array indices in radeonsi. I've also sent out some piglit tests to exercise these corner cases a bit more. Please review! Thanks, Nicolai -- src/compiler/glsl/ast_function.cpp

Re: [Mesa-dev] [PATCH 3/3] radeonsi: include ac_binary.h for struct ac_shader_binary

On 16 June 2017 at 21:09, Emil Velikov wrote: > NB! The series seems to build fine on my end and within Travis, yet > Jenkin results are still pending. Sent early for people to skim through. > The Jenkins build seem happy with the series. -Emil

[Mesa-dev] [PATCH 2/3] r600, radeon: move radeon_shader_binary_{init, clean} back to radeon

From: Emil Velikov Those are used by r600 and radeonsi, so moving them within the former was a bad idea. Fixes: d96a210842b ("r600g,compute: provide local copy of functions from ac_binary.c") Cc: Jan Vesely Cc: Aaron Watry

[Mesa-dev] [PATCH 1/3] ac: resolve conflicts introduced with "ac: remove amdgpu.h dependency"

From: Emil Velikov The commit did not add the relevant includes - in particular stdint.h and stdbool.h for the respective standard types. At the same time, the amdgpu_device_handle typedef redeclaration was off. Fixes: 81945ded0dc ("ac: remove amdgpu.h dependency")

[Mesa-dev] [PATCH 3/3] radeonsi: include ac_binary.h for struct ac_shader_binary

From: Emil Velikov The header embeds the struct so it needs the header inclusion instead of the dummy forward declaration. Cc: Nicolai Hähnle Cc: Marek Olšák Cc: Tom Stellard Fixes: 32206c5e560

Re: [Mesa-dev] [RFC PATCH 00/17] Introducing SPIR-V support to clover

Hello, I am working on an updated version of this series, which will include changes that have been suggested, as well as support for structures as a kernel argument. Along those, I was also thinking of doing some other changes to the SPIR-V linker: a) Store some metadata about the SPIR-V

Re: [Mesa-dev] [PATCH v1 3/3] i965/i915: Add UYVY as the supported format Trigger the correct sampler options for it. Similar with YUYV

Johnson Lin writes: Commit subject is too long. Make it a brief summary under 72 characters wide. Explain further, if necessary in commit body. See https://chris.beams.io/posts/git-commit/ for a good guide and rationale. > --- > src/intel/compiler/brw_compiler.h

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