Re: [Mesa-dev] [PATCH 7/7] i965: Fix asynchronous mappings on !LLC platforms.

On Wednesday, July 5, 2017 2:24:55 PM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2017-07-05 21:56:54) > > --- > > src/mesa/drivers/dri/i965/brw_bufmgr.c | 15 +-- > > 1 file changed, 13 insertions(+), 2 deletions(-) > > > > diff --git a/src/mesa/drivers/dri/i965/brw_bufmgr.c

Re: [Mesa-dev] [PATCH 6/7] i965: Don't use PREAD for glGetBufferSubData().

On Thursday, July 6, 2017 4:21:28 AM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2017-07-05 21:56:53) > > diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c > > b/src/mesa/drivers/dri/i965/intel_buffer_objects.c > > index a9ac29a6a81..2b0f7b9a698 100644 > > ---

[Mesa-dev] [PATCH] radeonsi: enable support for EXT_memory_object v2

v2: fix an indentation error Signed-off-by: Andres Rodriguez --- src/gallium/drivers/r600/r600_pipe.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c

[Mesa-dev] [PATCH 24/25] radv: generate the same driver UUID as radeonsi

These need to match for interop compatibility queries. Signed-off-by: Andres Rodriguez --- src/amd/vulkan/radv_device.c | 9 - src/amd/vulkan/radv_private.h | 1 + 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/amd/vulkan/radv_device.c

[Mesa-dev] [PATCH 25/25] radeonsi: enable support for EXT_memory_object

Signed-off-by: Andres Rodriguez --- src/gallium/drivers/r600/r600_pipe.c | 2 +- src/gallium/drivers/radeonsi/si_pipe.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/r600/r600_pipe.c b/src/gallium/drivers/r600/r600_pipe.c index

[Mesa-dev] [PATCH 20/25] mesa: hook up queries for NUM_TILING_TYPES and TILING_TYPES

These are just basic implementations. Signed-off-by: Andres Rodriguez --- src/mesa/main/formatquery.c | 17 + src/mesa/main/mtypes.h | 3 +++ src/mesa/main/texparam.c| 27 +++ 3 files changed, 47 insertions(+) diff --git

[Mesa-dev] [PATCH 22/25] radv: rename physical_device->uuid[] to cache_uuid[]

We have a few UUIDs, so lets be more specific. Signed-off-by: Andres Rodriguez --- src/amd/vulkan/radv_device.c | 4 ++-- src/amd/vulkan/radv_pipeline_cache.c | 4 ++-- src/amd/vulkan/radv_private.h| 2 +- 3 files changed, 5 insertions(+), 5 deletions(-)

[Mesa-dev] [PATCH 23/25] radv: generate same device UUID as radeonsi v2

This is required for interop use cases. The same device must report identical UUIDs through the GL and Vulkan APIs so that users can identify when it is safe to perform a memory object import. v2: use ac helpers to calculate the uuid Signed-off-by: Andres Rodriguez ---

[Mesa-dev] [PATCH 16/25] gallium: introduce device/driver UUID queries

Signed-off-by: Andres Rodriguez --- src/gallium/drivers/ddebug/dd_screen.c | 17 + src/gallium/include/pipe/p_defines.h | 1 + src/gallium/include/pipe/p_screen.h| 13 + 3 files changed, 31 insertions(+) diff --git

[Mesa-dev] [PATCH 21/25] mesa: fix error handling for memory objects

Signed-off-by: Andres Rodriguez --- src/mesa/main/externalobjects.c | 63 + 1 file changed, 51 insertions(+), 12 deletions(-) diff --git a/src/mesa/main/externalobjects.c b/src/mesa/main/externalobjects.c index 919a81c..73c9d4b 100644

[Mesa-dev] [PATCH 18/25] ac/gpu: add driver/device UUID query helpers

We need vulkan and gl to produce the same UUIDs. Therefore we should keep the mechanism to compute these in a common location to guarantee they are updated in lockstep. Signed-off-by: Andres Rodriguez --- src/amd/common/ac_gpu_info.c | 27 +++

[Mesa-dev] [PATCH 19/25] radeonsi: hook up device/driver UUID queries

Signed-off-by: Andres Rodriguez --- src/gallium/drivers/radeon/r600_pipe_common.c | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c b/src/gallium/drivers/radeon/r600_pipe_common.c index fd67d9a..c14d4eb 100644

[Mesa-dev] MRT rendering speed up from the pro driver

Hi, Hopefully someone in here can help with this, and maybe ask the internal Vulkan team how this works. I've been looking into a large perf cliff in radv vs pro when MRT rendering is enabled (I didn't know that was what I was looking for until today - about 2-3 weeks ago I was just digging

[Mesa-dev] [PATCH 17/25] mesa: hook up UUID queries for driver and device v2

v2: respective changes for new gallium interface Signed-off-by: Andres Rodriguez --- src/mesa/main/dd.h | 15 +++ src/mesa/main/get.c | 17 + src/mesa/main/version.c | 13 +

[Mesa-dev] [PATCH 12/25] mesa: hook up (Named)BufferStorageMem api

Include no_error variants as well. Signed-off-by: Andres Rodriguez --- src/mapi/glapi/gen/EXT_external_objects.xml | 4 +- src/mesa/main/bufferobj.c | 80 +++-- src/mesa/main/bufferobj.h | 16 +-

[Mesa-dev] [PATCH 15/25] mesa: Implement glGetUnsignedByte{v|i_v}

These are used by EXT_external_objects to present UUIDs for the device and the driver. Signed-off-by: Andres Rodriguez --- src/mesa/main/get.c | 177 1 file changed, 177 insertions(+) diff --git a/src/mesa/main/get.c

[Mesa-dev] [PATCH 14/25] mesa: expose EXT_memory_object and EXT_memory_object_fd v2

v2: use PIPE_CAP_MEMOBJ to guard the extension Signed-off-by: Andres Rodriguez --- src/mesa/main/extensions_table.h | 2 ++ src/mesa/main/mtypes.h | 2 ++ src/mesa/state_tracker/st_extensions.c | 5 + 3 files changed, 9 insertions(+) diff --git

[Mesa-dev] [PATCH 13/25] gallium: introduce PIPE_CAP_MEMOBJ

This can be used to guard support for EXT_memory_object and related extensions. Signed-off-by: Andres Rodriguez --- src/gallium/drivers/etnaviv/etnaviv_screen.c | 1 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c

[Mesa-dev] [PATCH 07/25] mesa: hook up memory object multisamples tex(ture)storage api

Signed-off-by: Andres Rodriguez --- src/mesa/main/externalobjects.c | 53 src/mesa/main/teximage.c| 76 + src/mesa/main/teximage.h| 10 ++ 3 files changed, 110 insertions(+), 29

[Mesa-dev] [PATCH 09/25] radeonsi: add basic memory object support

From: Dave Airlie Signed-off-by: Andres Rodriguez --- src/gallium/drivers/radeon/r600_pipe_common.h | 7 ++ src/gallium/drivers/radeon/r600_texture.c | 112 ++ 2 files changed, 119 insertions(+) diff --git

[Mesa-dev] [PATCH 11/25] mesa: implement memory objects as a backend for buffer objects

Use a memory object instead of user memory. Signed-off-by: Andres Rodriguez --- src/mesa/main/dd.h | 12 + src/mesa/state_tracker/st_cb_bufferobjects.c | 66 +--- 2 files changed, 61 insertions(+), 17 deletions(-) diff

[Mesa-dev] [PATCH 10/25] mesa: fix inconsistent indentation of st_cb_bufferobjects.c

No changes, just re-indent. Signed-off-by: Andres Rodriguez --- src/mesa/state_tracker/st_cb_bufferobjects.c | 36 ++-- 1 file changed, 18 insertions(+), 18 deletions(-) diff --git a/src/mesa/state_tracker/st_cb_bufferobjects.c

[Mesa-dev] [PATCH 08/25] mesa/st: implement memory objects as a backend for texture storage v2

From: Dave Airlie Instead of allocating memory to back a texture, use the provided memory object. v2: split off extension exposure logic Signed-off-by: Andres Rodriguez --- src/mesa/state_tracker/st_cb_texture.c | 123 +

[Mesa-dev] [PATCH 06/25] mesa: hook up memoryobject tex(ture)storage api

Signed-off-by: Andres Rodriguez --- src/mesa/main/dd.h | 9 src/mesa/main/externalobjects.c | 93 - src/mesa/main/texstorage.c | 76 - src/mesa/main/texstorage.h | 13 +-

[Mesa-dev] [PATCH 05/25] mesa/st: start adding memory object support v2

From: Dave Airlie v2: pass dedicated flag Signed-off-by: Andres Rodriguez --- src/mesa/Makefile.sources| 2 + src/mesa/state_tracker/st_cb_memoryobjects.c | 66

[Mesa-dev] [PATCH 01/25] mapi: add EXT_external_objects and EXT_external_objects_fd

Includes implementation stubs. Signed-off-by: Andres Rodriguez --- src/mapi/glapi/gen/EXT_external_objects.xml| 234 + src/mapi/glapi/gen/EXT_external_objects_fd.xml | 28 +++ src/mapi/glapi/gen/Makefile.am | 2 +

[Mesa-dev] [PATCH 04/25] gallium: introduce memory object v2

From: Dave Airlie v2: fix comment regarding fd ownership, define pipe_memory_object --- src/gallium/drivers/ddebug/dd_screen.c | 40 ++ src/gallium/include/pipe/p_screen.h| 36 ++

[Mesa-dev] [PATCH 03/25] mesa: add support for memory object parameters

Signed-off-by: Andres Rodriguez --- src/mesa/main/externalobjects.c | 54 - src/mesa/main/mtypes.h | 5 +++- 2 files changed, 57 insertions(+), 2 deletions(-) diff --git a/src/mesa/main/externalobjects.c

[Mesa-dev] [PATCH] Initial support for EXT_external_objects v2

This series is an initial step towards the implementation of EXT_external_objects. It implements the functionality under EXT_memory_object and EXT_memory_object_fd. This updated version of the series has the following changes: * Re-worked UUIDs to be provided by the gallium driver * Use a

[Mesa-dev] [PATCH 02/25] mesa: add support for memory object creation/import/delete

Used by EXT_external_objects and EXT_external_objects_fd Signed-off-by: Andres Rodriguez --- src/mesa/drivers/common/driverfuncs.c | 4 + src/mesa/main/dd.h| 36 + src/mesa/main/externalobjects.c | 145 +-

[Mesa-dev] [PATCH] loader/dri3: Use dri3_find_back in loader_dri3_swap_buffers_msc

From: Thomas Hellstrom If the application hasn't done any drawing since the last call, we would reuse the same back buffer which was used for the previous swap, which may not have completed yet. This could result in various issues such as tearing or application hangs. In

Re: [Mesa-dev] [PATCH 03/20] nir: Support lowering vote intrinsics

On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner wrote: > ... trivially (as allowed by the spec!) by reusing the existing > nir_opt_intrinsics code. > --- > src/compiler/nir/nir.h| 4 > src/compiler/nir/nir_opt_intrinsics.c | 6 +++--- > 2 files changed, 7

Re: [Mesa-dev] [PATCH 16/20] nir: Add a ballot32 intrinsic

I've thought about this a little bit, and I think we'd rather just decrease the bitsize of the intrinsic rather than add a whole new one. The separate intrinsic isn't really buying you anything, I don't think it's going to make anything simpler. On Thu, Jul 6, 2017 at 4:48 PM, Matt Turner

Re: [Mesa-dev] [PATCH 3/6] ac/nir: rewrite local variable handling

On Thu, Jul 6, 2017 at 6:36 PM, Matt Arsenault wrote: > > On Jul 6, 2017, at 18:31, Connor Abbott wrote: > > After looking into it some more, I think LLVM won't promote allocas to > registers at all when there are non-constant indices in the mix, and >

Re: [Mesa-dev] [PATCH 3/6] ac/nir: rewrite local variable handling

> On Jul 6, 2017, at 18:31, Connor Abbott wrote: > > After looking into it some more, I think LLVM won't promote allocas to > registers at all when there are non-constant indices in the mix, and > fixing it seems kinda involved. I guess a better solution for now

Re: [Mesa-dev] [PATCH 3/6] ac/nir: rewrite local variable handling

On Thu, Jul 6, 2017 at 2:18 PM, Connor Abbott wrote: > On Thu, Jul 6, 2017 at 2:01 PM, Bas Nieuwenhuizen > wrote: >> On Thu, Jul 6, 2017 at 9:48 PM, Connor Abbott >> wrote: >>> From: Connor Abbott

Re: [Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

On Thu, Jul 6, 2017 at 5:07 PM, Connor Abbott wrote: > FYI, I already have another series which adds ARB_shader_ballot and > ARB_shader_group_vote intrinsics, in addition to adding some more > precise semantics to represent the restrictions on ballotARB() and > similar things

Re: [Mesa-dev] [Mesa-stable] [st/va] Fix leak in VAAPI subpictures

It looks like we could want this into -stable (?) On Thu, 2017-07-06 at 21:10 +0300, Andres Gomez wrote: > On Thu, 2017-06-22 at 09:25 +, Namburu, Chandu-babu wrote: > > From: Chandu Babu N > > Subject: [PATCH] [st/va] Fix leak in VAAPI subpictures > >   > > sampler view

Re: [Mesa-dev] [PATCH 01/17] nir: introduce new convergent and cross-thread attributes

On Mon, Jun 12, 2017 at 9:26 PM, Jason Ekstrand wrote: > On Mon, Jun 12, 2017 at 7:38 PM, Connor Abbott wrote: >> >> On Mon, Jun 12, 2017 at 7:19 PM, Jason Ekstrand >> wrote: >> > On Mon, Jun 12, 2017 at 11:58 AM, Nicolai Hähnle

[Mesa-dev] [PATCH 09/11] i965: Push UBO data, but don't use it just yet.

This patch starts uploading UBO data via 3DSTATE_CONSTANT_* packets, and updates the compiler to know that there's extra payload data, so things continue working. However, it still issues pull loads for all data. I wanted to separate the two aspects for greater bisectability. ---

[Mesa-dev] [PATCH 08/11] i965: Pad buffer objects by 2kB in robust contexts to avoid OOB access.

This is an annoyingly big hammer, but it seems less mean than disabling UBO pushing, and I'm not sure what else to do. --- src/mesa/drivers/dri/i965/intel_buffer_objects.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 02/11] i965: Require a UBO offset alignment of 32 bytes.

Soon, we're going to start providing UBO data to shaders as push constants, rather than requiring them to issue pull loads. The 3DSTATE_CONSTANT_* commands require 32 byte aligned pointers. So, we need to increase this from 16 to 32. --- src/mesa/drivers/dri/i965/brw_context.c | 5 - 1 file

[Mesa-dev] [PATCH 04/11] i965: Store per-stage push constant BO pointers.

Right now, we always upload new push constant data, and immediately emit 3DSTATE_CONSTANT_* packets. We call intel_upload_space and store the resulting BO pointer in brw->curbe.curbe_bo. We read that when emitting the packets. This works today, but is fragile - it depends on upload and packet

[Mesa-dev] [PATCH 11/11] i965: Use pushed UBO data in the scalar backend.

This actually takes advantage of the newly pushed UBO data, avoiding pull loads. XXX: quote performance numbers --- src/intel/compiler/brw_fs.cpp | 35 ++- src/intel/compiler/brw_fs.h | 2 ++ src/intel/compiler/brw_fs_nir.cpp | 28

[Mesa-dev] [PATCH 03/11] i965: Select ranges of UBO data to be uploaded as push constants.

This adds a NIR pass that decides which portions of UBOS we should upload as push constants, rather than pull constants. --- src/intel/Makefile.sources | 1 + src/intel/compiler/brw_compiler.h | 11 + src/intel/compiler/brw_nir.h| 4 +

[Mesa-dev] [PATCH 10/11] i965: Factor out push locations.

With UBOs, the answer of "have we decided to push this uniform" gets a bit more complicated - for one, we have multiple surfaces. This patch refactors things so we can add the new code in a single place. --- src/intel/compiler/brw_fs.cpp | 39 +++

[Mesa-dev] [PATCH 07/11] i965: Stop re-uploading push constants after URB reconfiguration.

Previously we would re-upload the constant data to the batchbuffer, then re-emit the packets. We only need to do the last step (causing the existing data in the batchbuffer to be re-uploaded to the push constant staging area in the L3). Now that we've separated the two, it's pretty easy to

[Mesa-dev] [PATCH 05/11] i965: Introduce a BRW_NEW_DRAW_CALL dirty bit.

This allows us to have atoms which are signalled on every draw call. --- src/mesa/drivers/dri/i965/brw_context.h | 2 ++ src/mesa/drivers/dri/i965/brw_draw.c | 5 + src/mesa/drivers/dri/i965/brw_state_upload.c | 1 + 3 files changed, 8 insertions(+) diff --git

[Mesa-dev] [PATCH 06/11] i965: Separate uploading push constant data from the pointer packets.

I hope to upload UBO via 3DSTATE_CONSTANT_XS packets, in addition to normal uniforms. In order to do that, I'll need to re-emit the packets when UBOs change. But I don't want to re-copy the regular uniform data to the batchbuffer every time. This patch separates out the data uploading from the

[Mesa-dev] [PATCH 00/11] i965: UBO pushing for fun and profit?

Hello, This series begins pushing UBOs (rather than resorting to pull loads) for scalar shaders on Gen7.5+, for the OpenGL driver. Future work is to hook it up for Vulkan (haven't started), for the vec4 shader stages (I have about 75% of the code written), and for Gen7 (I have a plan). Note

[Mesa-dev] [PATCH 01/11] i965: Switch to absolute addressing for constant buffer 0.

By default, 3DSTATE_CONSTANT_* Constant Buffer 0 is relative to dynamic state base address. This makes it unusable for pushing UBOs. I'd like to be able to use all four push buffers. There is a bit in the INSTPM register (or CS_DEBUG_MODE2 on Skylake) which controls whether buffer 0 is relative

Re: [Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

FYI, I already have another series which adds ARB_shader_ballot and ARB_shader_group_vote intrinsics, in addition to adding some more precise semantics to represent the restrictions on ballotARB() and similar things [0]. The problem is that marking ballot as can_eliminate but not can_reorder is

[Mesa-dev] [Bug 101712] CPU lockup after ring 0 stalled

https://bugs.freedesktop.org/show_bug.cgi?id=101712 guiscara...@gmail.com changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |dri-devel@lists.freedesktop

[Mesa-dev] [PATCH 20/20] nir: Narrow unnecessary 64-bit operations to 32-bits

If we know the high bits are zero, we can just do a 32-bit comparison on the low bytes instead. --- src/compiler/nir/nir_opt_algebraic.py | 14 +- src/compiler/nir/nir_search_helpers.h | 48 +++ 2 files changed, 61 insertions(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 18/20] i965/fs: Add support for ballot32

No use in taking a 64-bit value when we know the high 32-bits are zero. --- src/intel/compiler/brw_compiler.c | 2 +- src/intel/compiler/brw_fs_nir.cpp | 9 +++-- 2 files changed, 8 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_compiler.c

[Mesa-dev] [PATCH 17/20] i965: Normalize types for FBL, FBH, etc

Allows the instructions to be compacted. The documentation claims that some of these only accept UD types, even though the type doesn't change the operation performed. Just normalize the types to ensure we get instruction compaction. The only functional changes are for FBL and CBIT (always use UD

[Mesa-dev] [PATCH 15/20] i965: Enable ARB_shader_ballot on Gen8+

--- docs/features.txt| 2 +- docs/relnotes/17.2.0.html| 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/features.txt b/docs/features.txt index ec78447e88..1f628e1c03 100644

[Mesa-dev] [PATCH 19/20] nir: Optimize find_lsb/imsb/umsb error checks

Two of the ARB_shader_ballot piglit tests hit the find_lsb case, removing some of the noise allowed me to better debug the test when it was failing. --- src/compiler/nir/nir_opt_algebraic.py | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/compiler/nir/nir_opt_algebraic.py

[Mesa-dev] [PATCH 12/20] i965/fs: Handle explicit flag sources in flags_read()

The implementations of the ARB_shader_ballot intrinsics will explicitly read the flag as a source register. --- src/intel/compiler/brw_fs.cpp | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index

[Mesa-dev] [PATCH 14/20] i965/fs: Implement ARB_shader_ballot operations

--- src/intel/compiler/brw_fs_nir.cpp | 41 +++ src/intel/compiler/brw_nir.c | 1 + 2 files changed, 42 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 17f35e081d..25e9b703eb 100644 ---

[Mesa-dev] [PATCH 16/20] nir: Add a ballot32 intrinsic

Some hardware, like i965, doesn't support group sizes greater than 32. In that case, we can use the ballot32 intrinsic instead, which will simplify our code generation. --- src/compiler/nir/nir.h| 2 ++ src/compiler/nir/nir_intrinsics.h | 3 +++

[Mesa-dev] [PATCH 13/20] i965/fs: Do not move MOVs writing the flag outside of control flow

The implementation of ballotARB() will start by zeroing the flags register. So, a doing something like if (gl_SubGroupInvocationARB % 2u == 0u) { ... = ballotARB(true); [...] } else { ... = ballotARB(true); [...]

[Mesa-dev] [PATCH 07/20] i965: Enable ARB_shader_group_vote

--- docs/features.txt| 2 +- docs/relnotes/17.2.0.html| 1 + src/mesa/drivers/dri/i965/intel_extensions.c | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/docs/features.txt b/docs/features.txt index 79b71de543..ec78447e88 100644

[Mesa-dev] [PATCH 09/20] nir: Add system values from ARB_shader_ballot

We already had a channel_num system value, which I'm renaming to subgroup_invocation to match the rest of the new system values. Note that while ballotARB(true) will return zeros in the high 32-bits on systems where gl_SubGroupSizeARB <= 32, the gl_SubGroup??MaskARB variables do not consider

[Mesa-dev] [PATCH 08/20] nir: Add intrinsics from ARB_shader_ballot

--- src/compiler/glsl/glsl_to_nir.cpp | 45 +++ src/compiler/nir/nir_intrinsics.h | 13 +++ 2 files changed, 58 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp b/src/compiler/glsl/glsl_to_nir.cpp index 43d7e07042..23632f27c2 100644 ---

[Mesa-dev] [PATCH 06/20] i965/fs: Implement ARB_shader_group_vote operations

--- src/intel/compiler/brw_fs_nir.cpp | 36 1 file changed, 36 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a9dce42c38..264398f38e 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 11/20] i965/fs: Allow emit_uniformize() to broadcast a specific channel

This function will be used to implement read_invocation (by specifying a specific channel) and read_first_invocation (by not specifying a channel). --- src/intel/compiler/brw_fs_builder.h | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 10/20] nir: Add pass to scalarize read_invocation/read_first_invocation

i965 will want these to be scalar operations. --- src/compiler/Makefile.sources | 1 + src/compiler/nir/nir.h | 2 +- .../nir/nir_lower_read_invocation_to_scalar.c | 112 + 3 files changed, 114 insertions(+), 1

[Mesa-dev] [PATCH 05/20] i965/fs: Handle explicit flag destinations in flags_written()

The implementations of the ARB_shader_group_vote intrinsics will explicitly write the flag as the destination register. --- src/intel/compiler/brw_fs.cpp | 12 ++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp

[Mesa-dev] [PATCH 02/20] nir: Add pass to optimize intrinsics

Specifically, constant fold intrinsics from ARB_shader_group_vote, but I suspect it'll be useful for other things in the future. --- src/compiler/Makefile.sources | 1 + src/compiler/nir/nir.h| 2 + src/compiler/nir/nir_opt_intrinsics.c | 102

[Mesa-dev] [PATCH 04/20] i965/vec4: Lower ARB_shader_group_vote intrinsics

I don't expect anyone is going to care about using this in vec4 programs (vertex/tessellation/geometry on Gen6/7), no one has come up with a good way to implement it much less test it. --- src/intel/compiler/brw_compiler.c | 3 +++ 1 file changed, 3 insertions(+) diff --git

[Mesa-dev] [PATCH 03/20] nir: Support lowering vote intrinsics

... trivially (as allowed by the spec!) by reusing the existing nir_opt_intrinsics code. --- src/compiler/nir/nir.h| 4 src/compiler/nir/nir_opt_intrinsics.c | 6 +++--- 2 files changed, 7 insertions(+), 3 deletions(-) diff --git a/src/compiler/nir/nir.h

[Mesa-dev] [PATCH 01/20] nir: Add intrinsics from ARB_shader_group_vote

These are intrinsics rather than opcodes, because they operate across channels. --- src/compiler/glsl/glsl_to_nir.cpp | 22 ++ src/compiler/nir/nir_intrinsics.h | 5 + 2 files changed, 27 insertions(+) diff --git a/src/compiler/glsl/glsl_to_nir.cpp

[Mesa-dev] [PATCH 0/3] MOCS versioning

Copying the kernel commit message: Starting with GEN9, Memory Object Control State (MOCS) becomes an index into a table as opposed to the direct programming within the command. The table has 62 usable entries (ie 6 bits can represent all settings), and each buffer type may use one of these 62

[Mesa-dev] [PATCH 3/3] intel: Make driver aware of MOCS table version

We don't yet have optimal MOCS settings, but we have enough to know how to at least determine when we might have non-optimal settings within our driver. Signed-off-by: Ben Widawsky --- src/intel/vulkan/anv_device.c | 12 src/intel/vulkan/anv_private.h

[Mesa-dev] [Bug 101703] No stencil buffer allocated when requested by GLUT

https://bugs.freedesktop.org/show_bug.cgi?id=101703 Brian Paul changed: What|Removed |Added Resolution|--- |FIXED

[Mesa-dev] [PATCH 2/3] intel: Merge latest i915 uapi

Signed-off-by: Ben Widawsky --- src/intel/drm/i915_drm.h | 8 1 file changed, 8 insertions(+) diff --git a/src/intel/drm/i915_drm.h b/src/intel/drm/i915_drm.h index c26bf7c125..69e38ce89f 100644 --- a/src/intel/drm/i915_drm.h +++ b/src/intel/drm/i915_drm.h @@ -431,6

[Mesa-dev] [PATCH 1/1] drm/i915: Version the MOCS settings

From: Ben Widawsky Starting with GEN9, Memory Object Control State (MOCS) becomes an index into a table as opposed to the direct programming within the command. The table has 62 usable entries (ie 6 bits can represent all settings), and each buffer type may use one

Re: [Mesa-dev] [PATCH 3/3] mesa: fix glPrimitiveRestartNV crash inside a render list.

Thanks for the patches, Olivier! I'm a bit short on time, but I'll test/commit them ASAP. I'll take a closer look at the VBO issue too. -Brian On 07/06/2017 09:45 AM, Olivier Lauffenburger wrote: glPrimitiveRestartNV crashes when it is called during the compilation of a render list. There

[Mesa-dev] [Bug 101712] CPU lockup after ring 0 stalled

https://bugs.freedesktop.org/show_bug.cgi?id=101712 --- Comment #2 from guiscara...@gmail.com --- Created attachment 132488 --> https://bugs.freedesktop.org/attachment.cgi?id=132488=edit DSMEG (more detailed log) Here it is a more detailed log -- You are receiving this mail because: You are

[Mesa-dev] [Bug 101712] CPU lockup after ring 0 stalled

https://bugs.freedesktop.org/show_bug.cgi?id=101712 guiscara...@gmail.com changed: What|Removed |Added Priority|medium |high --- Comment #1 from

[Mesa-dev] [Bug 101712] CPU lockup after ring 0 stalled

https://bugs.freedesktop.org/show_bug.cgi?id=101712 Bug ID: 101712 Summary: CPU lockup after ring 0 stalled Product: Mesa Version: unspecified Hardware: x86-64 (AMD64) OS: Linux (All) Status: NEW

Re: [Mesa-dev] [PATCH 2/2] ac/nir: Fix ordering of parameters for image atomic cmpswap intrinsics

Thanks! Pushed and cc'd it to stable. Not pushing the first patch as I assume that is superseded by Connors patches. On Fri, Jun 30, 2017 at 12:15 PM, Alex Smith wrote: > The NIR parameters are ordered "compare, data", matching GLSL, but both > the image and buffer

Re: [Mesa-dev] [PATCH] etnaviv: fix refcnt initialization in etna_screen

On Thu, Jul 6, 2017 at 11:18 PM, Aleksander Morgado wrote: > Despite being a member of the etna_screen struct, 'refcnt' is used by > the winsys-specific logic to track the reference count of the object > managed in a hash table. When the count reaches zero, the pipe

Re: [Mesa-dev] [PATCH 2/6] nir/lower_io_to_temporaries: don't set compact on shadow vars

Reviewed-by: Jason Ekstrand On Thu, Jul 6, 2017 at 12:48 PM, Connor Abbott wrote: > From: Connor Abbott > > The compact flag doesn't make sense on local variables, since the > packing on them is up to the driver. This fixes

Re: [Mesa-dev] [PATCH 6/6] radv: don't lower indirect derefs

On Thu, Jul 6, 2017 at 9:50 PM, Connor Abbott wrote: > From: Connor Abbott > > Radeonsi doesn't either. As of the last commit, these should be handled > properly as long as LLVM has scratch support. We also should use >

Re: [Mesa-dev] [PATCH] radv/ac: drop setting xnack

Reviewed-by: Bas Nieuwenhuizen On Fri, Jul 7, 2017 at 12:10 AM, Dave Airlie wrote: > From: Dave Airlie > > Since radv uses compute rings and we can't know when we are setting > up the shaders what ring they are to be used on, we

Re: [Mesa-dev] [PATCH 0/6] radv: Rewrite local & shared variable handling

On 6 July 2017 at 22:20, Connor Abbott wrote: > On Thu, Jul 6, 2017 at 12:48 PM, Connor Abbott > wrote: >> From: Connor Abbott >> >> This series grew out of trying to get rid of the copy-n-pasted index >> calculation code in

[Mesa-dev] [PATCH] radv/ac: drop setting xnack

From: Dave Airlie Since radv uses compute rings and we can't know when we are setting up the shaders what ring they are to be used on, we should just use the default xnack setting. This may be suboptimal in some places, but if we hit a problem, we likely should try and

Re: [Mesa-dev] [PATCH 09/19] radeonsi: add basic memory object support

On 2017-07-04 12:39 PM, Andres Rodriguez wrote: On 2017-07-04 09:30 AM, Christian König wrote: Am 04.07.2017 um 15:13 schrieb Nicolai Hähnle: On 01.07.2017 01:03, Andres Rodriguez wrote: From: Dave Airlie Signed-off-by: Andres Rodriguez ---

Re: [Mesa-dev] [PATCH 1/4] radeonsi: fix DCC fast clear for luminance and alpha formats

On Thu, Jul 6, 2017 at 8:24 PM, Andres Gomez wrote: > Marek, would we want this series in -stable or we shouldn't bother ? Don't bother. Patch 1 isn't that important. Other patches are for features not enabled in 17.1. Marek ___

Re: [Mesa-dev] [PATCH 0/6] radv: Rewrite local & shared variable handling

On Thu, Jul 6, 2017 at 12:48 PM, Connor Abbott wrote: > From: Connor Abbott > > This series grew out of trying to get rid of the copy-n-pasted index > calculation code in radv's NIR-to-LLVM path, in particular in > radv_get_deref_offset(). I

[Mesa-dev] [PATCH] etnaviv: fix refcnt initialization in etna_screen

Despite being a member of the etna_screen struct, 'refcnt' is used by the winsys-specific logic to track the reference count of the object managed in a hash table. When the count reaches zero, the pipe screen is removed from the table and destroyed. Fix the logic by initializing the refcnt to 1

Re: [Mesa-dev] [PATCH 5/6] radv: reorder and add passes to match i965

Reviewed-by: Bas Nieuwenhuizen On Thu, Jul 6, 2017 at 9:50 PM, Connor Abbott wrote: > From: Connor Abbott > > This makes the radv shader pipeline much closer to brw_preprocess_nir(). > The main changes are: > > - Now we

Re: [Mesa-dev] [PATCH 3/6] ac/nir: rewrite local variable handling

On Thu, Jul 6, 2017 at 2:01 PM, Bas Nieuwenhuizen wrote: > On Thu, Jul 6, 2017 at 9:48 PM, Connor Abbott > wrote: >> From: Connor Abbott >> >> The old way was very TGSI-based, and couldn't handle indirect >> dereferences

Re: [Mesa-dev] [PATCH 3/4] ac/llvm: set xnack like radeonsi does.

On Thu, Jul 6, 2017 at 4:56 PM, Marek Olšák wrote: > On Thu, Jul 6, 2017 at 8:12 PM, Alex Deucher wrote: >> On Thu, Jul 6, 2017 at 1:13 PM, Jan Vesely wrote: >>> On Thu, 2017-07-06 at 12:09 +1000, Dave Airlie wrote: From:

Re: [Mesa-dev] [PATCH 4/6] ac/nir: rewrite shared variable handling

Patches 3-4 look technically correct to me, so for just using it for shared vars Reviewed-by: Bas Nieuwenhuizen On Thu, Jul 6, 2017 at 9:48 PM, Connor Abbott wrote: > From: Connor Abbott > > Similar to before, do the direct

Re: [Mesa-dev] [PATCH mesa] build systems: move git_sha1_gen.sh to bin/

LGTM. Reviewed-by: Brian Paul On 07/06/2017 02:08 PM, Eric Engestrom wrote: There was no reason for this script to live outside the scripts directory. Suggested-by: Brian Paul Signed-off-by: Eric Engestrom --- Makefile.am

Re: [Mesa-dev] [PATCH 1/6] nir: don't segfault when printing variables with no name

Reviewed-by: Bas Nieuwenhuizen On Thu, Jul 6, 2017 at 9:48 PM, Connor Abbott wrote: > From: Connor Abbott > > While normally we give variables whose name field is NULL a temporary > name when called from

Re: [Mesa-dev] [PATCH 3/6] ac/nir: rewrite local variable handling

On Thu, Jul 6, 2017 at 9:48 PM, Connor Abbott wrote: > From: Connor Abbott > > The old way was very TGSI-based, and couldn't handle indirect > dereferences at all. Instead, pass through the type information NIR has I think the old code should

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