[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 gloriouseggr...@gmail.com changed: What|Removed |Added CC||gloriouseggr...@gmail.com

Re: [Mesa-dev] [RFC 2/2] anv: enable VK_EXT_shader_viewport_index_layer

Reviewed-by: Iago Toral Quiroga However, I think we should not push this until we have testing coverage for using gl_Layer from Vertex and TessEval shaders. For now you only submitted a test for gl_ViewportIndex to CTS right? Iago On Fri, 2018-02-23 at 14:09 -0800, Caio

Re: [Mesa-dev] [PATCH v3 1/2] spirv: Add SpvCapabilityShaderViewportIndexLayerEXT

This patch is: Reviewed-by: Iago Toral Quiroga On Fri, 2018-02-23 at 14:09 -0800, Caio Marcelo de Oliveira Filho wrote: > This capability allows gl_ViewportIndex and gl_Layer to also be used > as outputs in Vertex and Tesselation shaders. > > v2: Make conditional to the

Re: [Mesa-dev] [PATCH 04/12] vbo: Implement vbo_loopback_vertex_list in terms of the VAO.

Hi Brian, On Wednesday, 28 February 2018 00:55:33 CET Brian Paul wrote: > Minor nit-picks below. > > @@ -94,17 +94,15 @@ struct loopback_attr { > >*/ > > static void > > loopback_prim(struct gl_context *ctx, > > - const GLfloat *buffer, > > + const GLubyte

Re: [Mesa-dev] [PATCH 11/12] vbo: Remove vbo_save_vertex_list::buffer_offset.

Hi Brian, On Wednesday, 28 February 2018 00:56:36 CET Brian Paul wrote: > On 02/26/2018 11:12 PM, mathias.froehl...@gmx.net wrote: > > From: Mathias Fröhlich > > > > The buffer_offset is used in aligned_vertex_buffer_offset. > > But now that most of these decisions are

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

Can someone review this patch? The bug if fixes is blocking the 18.0 release. Iago On Tue, 2018-02-27 at 08:02 +0100, Iago Toral Quiroga wrote: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, > instead

Re: [Mesa-dev] [PATCH 4/4] i965/tiled_memcpy: Add support for Yf and Ys tiling/detiling

Ilia Mirkin writes: > On Feb 27, 2018 11:22 PM, "Scott D Phillips" > wrote: > > > Yf and Ys are a family of tilings similar to Y. The actual address > > bit interleavings for Yf* and Ys* depend upon the bits-per-pixel > > value of the surface,

[Mesa-dev] [PATCH] r600/shader: when using images always load thread id gpr at start (v2)

From: Dave Airlie The delayed loading code was fail if we had control flow. This fixes: tests/spec/arb_shader_image_load_store/execution/image_checkerboard.shader_test v2: don't use temp_reg before setting temp_reg up. Signed-off-by: Dave Airlie ---

[Mesa-dev] [PATCH] r600/shader: when using images always load thread id gpr at start

From: Dave Airlie The delayed loading code was fail if we had control flow. This fixes: tests/spec/arb_shader_image_load_store/execution/image_checkerboard.shader_test Signed-off-by: Dave Airlie --- src/gallium/drivers/r600/r600_shader.c | 18

[Mesa-dev] [PATCH v4] anv: enable VK_EXT_shader_stencil_export

v2: An attempt to support SpvExecutionModeStencilRefReplacingEXT's behavior also follows, with the interpretation to said mode being we prevent writes to the built-in FragStencilRefEXT variable when the execution mode isn't set. v3: A more cautious reading of

Re: [Mesa-dev] [PATCH 3/3] mesa: Fix tautological compare

On 02/27/2018 07:38 PM, Brian Paul wrote: > On 02/27/2018 06:07 PM, Ian Romanick wrote: >> From: Ian Romanick >> >> _BaseFormat is GLenum16, but it is compared with an integer -1.  Even if >> _mesa_base_tex_format returned -1, it becomes 0x, and the >> comparison,

[Mesa-dev] [Bug 104302] Wolfenstein 2 (2017) under wine graphical artifacting on RADV

https://bugs.freedesktop.org/show_bug.cgi?id=104302 --- Comment #9 from gloriouseggr...@gmail.com --- Sorry for the delayed response, have been at work. Today roderickc/wine-vulkan patches were implemented into mainline wine and wine-staging was rebased, so I was able to run the following video

Re: [Mesa-dev] [PATCH 4/4] i965/tiled_memcpy: Add support for Yf and Ys tiling/detiling

On Feb 27, 2018 11:22 PM, "Scott D Phillips" wrote: Yf and Ys are a family of tilings similar to Y. The actual address bit interleavings for Yf* and Ys* depend upon the bits-per-pixel value of the surface, where 128-, 32-, and 8-bpp tiles are square and 64- and 16-bpp

[Mesa-dev] [PATCH] r600: partly revert disabling tiling for 1d texture.

From: Dave Airlie Previously we had a check for 1d of narrow 2D textures, however narrow 2d textures caused gpu hangs, but it was correct for 1d textures. This fixes a bunch of 1D image piglits for me. --- src/gallium/drivers/r600/r600_texture.c | 5 + 1 file changed, 5

[Mesa-dev] [PATCH 3/4] i965/tiled_memcpy: Add tile_addr_fn to compute the address of a tile

Replace the calculation of the individual tile address with a call through a function pointer to the calculation. This will be important with Ys tiling where a more complicated calculation is needed to derive the 4 kbyte sub-tile address. --- src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 29

[Mesa-dev] [PATCH 2/4] i965/tiled_memcpy: Pass cpp to tiling/untiling functions

As preparation for doing Yf/Ys tiling, pass the image's cpp into this tiling/untiling functions. The layout of Yf/Ys differ depending on cpp. Also plumb tiling and cpp through to the per-tile functions for ytile. --- src/mesa/drivers/dri/i965/intel_pixel_read.c | 1 +

[Mesa-dev] [PATCH 1/4] i965/tiled_memcpy: ytiled_to_linear a cache line at a time

Similar to the transformation applied to linear_to_ytiled, also align each readback from the ytiled source to a cacheline (i.e. transfer a whole cacheline from the source before moving on to the next column). This will allow us to utilize movntqda (_mm_stream_si128) in a subsequent patch to obtain

[Mesa-dev] [PATCH 4/4] i965/tiled_memcpy: Add support for Yf and Ys tiling/detiling

Yf and Ys are a family of tilings similar to Y. The actual address bit interleavings for Yf* and Ys* depend upon the bits-per-pixel value of the surface, where 128-, 32-, and 8-bpp tiles are square and 64- and 16-bpp tiles have a 2:1 aspect ratio. The address bit layout of Yf and Ys are the same

[Mesa-dev] [PATCH 1/2] cso: don't cycle through PIPE_MAX_SHADER_SAMPLER_VIEWS on context destroy

From: Roland Scheidegger There's no point, we know the highest non-null one. --- src/gallium/auxiliary/cso_cache/cso_context.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/gallium/auxiliary/cso_cache/cso_context.c

[Mesa-dev] [PATCH 2/2] softpipe: don't iterate through PIPE_MAX_SHADER_SAMPLER_VIEWS

From: Roland Scheidegger We were setting view to NULL if the iteration was larger than i. But in fact if the view is NULL the code did nothing anyway... --- src/gallium/drivers/softpipe/sp_state_sampler.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [Mesa-dev] [PATCH] RFC: gallium: increase PIPE_MAX_SHADER_SAMPLER_VIEWS to 128

Am 27.02.2018 um 19:07 schrieb Roland Scheidegger: > Am 27.02.2018 um 17:39 schrieb Brian Paul: >> On 02/26/2018 07:45 PM, Roland Scheidegger wrote: >>> Am 27.02.2018 um 03:38 schrieb srol...@vmware.com: From: Roland Scheidegger Some state trackers require 128.

[Mesa-dev] [Bug 105285] Mesa-utils -8.4 - glxinfo report has a blank value in GL_NUM_SHADING_LANGUAGE_VERSIONS subsection and also the aligniment below 4.3 seems not correct

https://bugs.freedesktop.org/show_bug.cgi?id=105285 Bug ID: 105285 Summary: Mesa-utils -8.4 - glxinfo report has a blank value in GL_NUM_SHADING_LANGUAGE_VERSIONS subsection and also the aligniment below 4.3 seems not correct

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

I think you just have to rely on the default of them being disabled. It is a bug of an app calling into mesa with non-default float state. Roland Am 28.02.2018 um 04:35 schrieb Jason Ekstrand: > On Tue, Feb 27, 2018 at 7:28 PM, Connor Abbott >

Re: [Mesa-dev] [PATCH 3/3] mesa: Fix tautological compare

On 02/27/2018 06:07 PM, Ian Romanick wrote: From: Ian Romanick _BaseFormat is GLenum16, but it is compared with an integer -1. Even if _mesa_base_tex_format returned -1, it becomes 0x, and the comparison, after type promotion, will always fail. Fix this by

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

On Tue, Feb 27, 2018 at 7:28 PM, Connor Abbott wrote: > Floating point division shouldn't signal on division by zero, it > should just return an appropriately-signed infinity, which seems like > a sane thing to do, and way better than just returning 0. I think that depends

[Mesa-dev] [PATCH v2] nir: fix interger divide by zero crash during constant folding

From the GLSL 4.60 spec Section 5.9 (Expressions): "Dividing by zero does not cause an exception but does result in an unspecified value." Fixes: 89285e4d47a6 "nir: add new constant folding infrastructure" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105271 ---

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

On Tue, Feb 27, 2018 at 7:20 PM, Timothy Arceri wrote: > On 28/02/18 14:13, Jason Ekstrand wrote: > >> On February 27, 2018 19:11:49 Jason Ekstrand >> wrote: >> >> On February 27, 2018 19:07:43 Timothy Arceri >>> wrote: >>>

[Mesa-dev] [Bug 54763] glCopyPixels dirties the context and all rendering is slower after that

https://bugs.freedesktop.org/show_bug.cgi?id=54763 Daniel van Vugt changed: What|Removed |Added Resolution|--- |WONTFIX

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

Floating point division shouldn't signal on division by zero, it should just return an appropriately-signed infinity, which seems like a sane thing to do, and way better than just returning 0. So we shouldn't do this with fdiv. I guess 0 is as good a result as any for the integer division, though

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

On 28/02/18 14:13, Jason Ekstrand wrote: On February 27, 2018 19:11:49 Jason Ekstrand wrote: On February 27, 2018 19:07:43 Timothy Arceri wrote: From the GLSL 4.60 spec Section 5.9 (Expressions):    "Dividing by zero does not cause an

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

On February 27, 2018 19:11:49 Jason Ekstrand wrote: On February 27, 2018 19:07:43 Timothy Arceri wrote: From the GLSL 4.60 spec Section 5.9 (Expressions): "Dividing by zero does not cause an exception but does result in an unspecified

Re: [Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

On February 27, 2018 19:07:43 Timothy Arceri wrote: From the GLSL 4.60 spec Section 5.9 (Expressions): "Dividing by zero does not cause an exception but does result in an unspecified value." Fixes: 89285e4d47a6 "nir: add new constant folding infrastructure"

[Mesa-dev] [PATCH] nir: fix divide by zero crash during constant folding

From the GLSL 4.60 spec Section 5.9 (Expressions): "Dividing by zero does not cause an exception but does result in an unspecified value." Fixes: 89285e4d47a6 "nir: add new constant folding infrastructure" Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=105271 ---

Re: [Mesa-dev] [PATCH 1/6] intel/l3: Don't allocate SLM partition on ICL+.

Reviewed-by: Jordan Justen On 2018-02-27 13:38:23, Francisco Jerez wrote: > SLM has a chunk of special-purpose memory separate from L3 on ICL+, we > shouldn't allocate a partition for it on L3 anymore. > --- > src/intel/common/gen_l3_config.c | 2 +- > 1 file changed,

Re: [Mesa-dev] [PATCH 1/3] mesa: Silence unused parameter warning in compressedteximage_only_format

Series Reviewed-by: Jordan Justen On 2018-02-27 17:06:59, Ian Romanick wrote: > From: Ian Romanick > > Passing ctx to compressedteximage_only_format was the only use of the > ctx parameter in _mesa_format_no_online_compression, so that

Re: [Mesa-dev] [PATCH v3 06/13] intel/isl: Add support to emit clear value address.

On Tue, Feb 27, 2018 at 05:00:24PM -0800, Jordan Justen wrote: > On 2018-02-26 21:35:42, Jason Ekstrand wrote: > > On Mon, Feb 26, 2018 at 8:12 PM, Jordan Justen > > wrote: > > > > > On 2018-02-26 17:08:12, Jason Ekstrand wrote: > > > > On Mon, Feb 26, 2018 at 1:14 PM,

[Mesa-dev] [PATCH 2/3] mesa: Silence remaining unused parameter warnings in teximage.c

From: Ian Romanick src/mesa/main/teximage.c: In function ‘_mesa_test_proxy_teximage’: src/mesa/main/teximage.c:1301:51: warning: unused parameter ‘level’ [-Wunused-parameter] GLuint numLevels, GLint level,

[Mesa-dev] [PATCH 3/3] mesa: Fix tautological compare

From: Ian Romanick _BaseFormat is GLenum16, but it is compared with an integer -1. Even if _mesa_base_tex_format returned -1, it becomes 0x, and the comparison, after type promotion, will always fail. Fix this by explicitly casting both to GLenum16. This should

[Mesa-dev] [PATCH 1/3] mesa: Silence unused parameter warning in compressedteximage_only_format

From: Ian Romanick Passing ctx to compressedteximage_only_format was the only use of the ctx parameter in _mesa_format_no_online_compression, so that parameter had to go too. ../../SOURCE/master/src/mesa/main/teximage.c: In function ‘compressedteximage_only_format’:

Re: [Mesa-dev] [PATCH v3 06/13] intel/isl: Add support to emit clear value address.

On 2018-02-26 21:35:42, Jason Ekstrand wrote: > On Mon, Feb 26, 2018 at 8:12 PM, Jordan Justen > wrote: > > > On 2018-02-26 17:08:12, Jason Ekstrand wrote: > > > On Mon, Feb 26, 2018 at 1:14 PM, Jordan Justen < > > jordan.l.jus...@intel.com> > > > wrote: > > > > > > >

Re: [Mesa-dev] [PATCH v3 12/13] anv: Emit the fast clear color address, instead of value.

On Tue, Feb 27, 2018 at 4:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Tue, Feb 27, 2018 at 02:58:01PM -0800, Jason Ekstrand wrote: > > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < > rafael.antogno...@intel.com > > > wrote: > > > > On Gen10+, instead of copying

Re: [Mesa-dev] [PATCH v3 12/13] anv: Emit the fast clear color address, instead of value.

On Tue, Feb 27, 2018 at 02:58:01PM -0800, Jason Ekstrand wrote: > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli > > wrote: > > On Gen10+, instead of copying the clear color from the state buffer to > the surface state, just use the address of the state

Re: [Mesa-dev] [PATCH v2] anv: set maxResourceSize to the respective value for each generation

On Tue, Feb 27, 2018 at 2:43 AM, Samuel Iglesias Gonsálvez < sigles...@igalia.com> wrote: > v2: > - Add the proper values to gen9+ (Jason) > > Signed-off-by: Samuel Iglesias Gonsálvez > --- > src/intel/vulkan/anv_formats.c | 14 +- > 1 file changed, 13

Re: [Mesa-dev] [PATCH] ac/radv: move load base vertex abi setup to vertex shader.

Reviewed-by: Bas Nieuwenhuizen On Wed, Feb 28, 2018 at 12:55 AM, Dave Airlie wrote: > From: Dave Airlie > > This was segfaulting: > dEQP-VK.memory.pipeline_barrier.host_write_index_buffer.1024 > > Fixes: 8de6f797070 (ac/radeonsi:

[Mesa-dev] [PATCH] radeon/vcn: use enc profile instead of pic profile

From: Boyuan Zhang Picture profile might not be set in some cases. Therefore, better to use the profile stored in encoder base. Signed-off-by: Boyuan Zhang --- src/gallium/drivers/radeon/radeon_vcn_enc.c | 4 ++--

Re: [Mesa-dev] [PATCH 11/12] vbo: Remove vbo_save_vertex_list::buffer_offset.

On 02/26/2018 11:12 PM, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich The buffer_offset is used in aligned_vertex_buffer_offset. But now that most of these decisions are done in compile_vertex_list we can work on local variables instead of struct members in

Re: [Mesa-dev] [PATCH 04/12] vbo: Implement vbo_loopback_vertex_list in terms of the VAO.

Minor nit-picks below. On 02/26/2018 11:12 PM, mathias.froehl...@gmx.net wrote: From: Mathias Fröhlich Use the information already present in the VAO to replay a display list node using immediate mode draw commands. Use a hand full of helper methods that will be

[Mesa-dev] [PATCH] ac/radv: move load base vertex abi setup to vertex shader.

From: Dave Airlie This was segfaulting: dEQP-VK.memory.pipeline_barrier.host_write_index_buffer.1024 Fixes: 8de6f797070 (ac/radeonsi: add load_base_vertex() to the abi) Signed-off-by: Dave Airlie --- src/amd/common/ac_nir_to_llvm.c | 2 +- 1 file

Re: [Mesa-dev] [PATCH v3 00/13] Use clear color address in surface state.

I've now read through the whole thing and sprinkled some comments. Over-all, I think it's looking pretty good. There are a couple of bits of follow-on work that could be done: 1) Now that we have indirect clear colors, we can allow non-default clear values for texturing and transfer ops in ANV.

Re: [Mesa-dev] [Mesa-users] GraphicsFuzz metamorphic testing of shader compilers

On 02/27/2018 10:27 AM, Hugues Evrard wrote: Hi all, I have just reported a Mesa (i965) crash which was triggered by a shader from the GraphicsFuzz demo (bug ID 105271), and I wanted to give a broader context on that bug report. We are three academics (Alastair, Paul and myself) from

Re: [Mesa-dev] [PATCH v3 11/13] i965/surface_state: Silence warning.

Reviewed-by: Jason Ekstrand On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > This warning showed up after aux_bo started being used inside > > if (use_clear_address) {... > > But use_clear_address depends on aux_surf being not

Re: [Mesa-dev] [PATCH v3 08/13] i965/miptree: Add space to store the clear value in the aux surface.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > Similarly to vulkan where we store the clear value in the aux surface, > we can do the same in GL. > > v2: Remove unneeded extra function. > v3: Use clear_value_state_size instead of clear_value_size. > >

Re: [Mesa-dev] [PATCH v3 09/13] i965/blorp: Update the fast clear color entry buffer.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Gen10, whenever the fast clear color changes, update it on the clear > color entry buffer. This allow us to use it directly when emitting the > surface state. > > Signed-off-by: Rafael Antognolli

Re: [Mesa-dev] [PATCH 1/4] radv: Implement WaitForFences with !waitAll.

For the series. Reviewed-by: Dave Airlie On 27 February 2018 at 09:37, Bas Nieuwenhuizen wrote: > Nothing to do except using a busy wait loop. At least for old kernels. > > A better implementation for newer kernels to come later. > > Bugzilla:

Re: [Mesa-dev] [PATCH] gallium: remove llvm from ir struct

Acked-by: Dave Airlie On 28 February 2018 at 08:36, Timothy Arceri wrote: > Ping? > > On 02/02/18 08:54, Timothy Arceri wrote: >> >> This was added in 425dc4c4b366 but never used. Also since >> 100796c15c3a native has superseded llvm. >> --- >>

[Mesa-dev] [Bug 105274] Buffer overflow in gallium/auxiliary/hud/hud_cpufreq.c

https://bugs.freedesktop.org/show_bug.cgi?id=105274 --- Comment #3 from Gert Wollny --- The sscanf will accept the number and not check the rest of the string, yes, but later in the code you have char basename[256]; snprintf(basename, sizeof(basename),

Re: [Mesa-dev] [PATCH v3 12/13] anv: Emit the fast clear color address, instead of value.

On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Gen10+, instead of copying the clear color from the state buffer to > the surface state, just use the address of the state buffer in the > surface state directly. This way we can avoid the copy from

Re: [Mesa-dev] [PATCH] radeonsi: fix radeon create encoder return

On Tue, Feb 27, 2018 at 5:43 PM, wrote: > From: Boyuan Zhang > > Previous patch missed a "return" when trying to modify the create encoder > function, which made the whole logic fail. Therefore, add the return back. > > Signed-off-by: Boyuan Zhang

[Mesa-dev] [PATCH] radeonsi: fix radeon create encoder return

From: Boyuan Zhang Previous patch missed a "return" when trying to modify the create encoder function, which made the whole logic fail. Therefore, add the return back. Signed-off-by: Boyuan Zhang --- src/gallium/drivers/radeonsi/si_uvd.c | 2 +- 1

Re: [Mesa-dev] [PATCH] gallium: remove llvm from ir struct

Ping? On 02/02/18 08:54, Timothy Arceri wrote: This was added in 425dc4c4b366 but never used. Also since 100796c15c3a native has superseded llvm. --- src/gallium/include/pipe/p_state.h | 1 - 1 file changed, 1 deletion(-) diff --git a/src/gallium/include/pipe/p_state.h

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

On 2018-02-26 16:05:46, Kenneth Graunke wrote: > This allows most GPU objects to use the full 48-bit address space > offered by Gen8+ platforms, rather than being stuck with 32-bit. > This expands the available GPU memory from 4G to 256TB or so. > > A few objects - instruction, scratch, and

Re: [Mesa-dev] [PATCH v4] anv: implement VK_EXT_global_priority extension

Reviewed-by: Jason Ekstrand On Tue, Feb 27, 2018 at 12:14 AM, Tapani Pälli wrote: > v2: add ANV_CONTEXT_REALTIME_PRIORITY (Chris) > use unreachable with unknown priority (Samuel) > > v3: add stubs in gem_stubs.c (Emil) > use priority

Re: [Mesa-dev] [PATCH 01/17] intel: Add a preliminary device for Ice Lake

On Tuesday, February 20, 2018 9:15:08 PM PST Matt Turner wrote: > From: Anuj Phogat > > Signed-off-by: Anuj Phogat [...] > + .urb = { \ > + .size = 1024, \ > + } This

[Mesa-dev] [PATCH 2/6] intel/ir: Allow representing additional flag subregisters in the IR.

This allows representing conditional mods and predicates on f1.0-f1.1 at the IR level by adding an extra bit to the flag_subreg backend_instruction field. --- src/intel/compiler/brw_fs.cpp| 12 +++- src/intel/compiler/brw_fs_generator.cpp | 4 ++--

[Mesa-dev] [PATCH 1/6] intel/l3: Don't allocate SLM partition on ICL+.

SLM has a chunk of special-purpose memory separate from L3 on ICL+, we shouldn't allocate a partition for it on L3 anymore. --- src/intel/common/gen_l3_config.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/common/gen_l3_config.c b/src/intel/common/gen_l3_config.c

[Mesa-dev] [PATCH 6/6] Revert "i965/fs: Predicate byte scattered writes if needed"

This reverts commit a4031bdfa927fb4c3c5d0bdadc70634f3c1a5eac. It's redundant with the sample mask predication done at this point by the common logical send lowering infrastructure, and rather buggy because it wasn't applying the correct sample mask in shaders using discard, since the dispatch

[Mesa-dev] [PATCH 3/6] intel/ir: Allow arbitrary scratch flag registers for SHADER_OPCODE_FIND_LIVE_CHANNEL.

This shouldn't cause any functional change at this point, it changes SHADER_OPCODE_FIND_LIVE_CHANNEL to use the flag register specified at the IR level instead of the hard-coded f1.0, now that it can be represented in backend_instruction::flag_subreg. This will be necessary for scheduling to

[Mesa-dev] [PATCH 5/6] intel/fs: Handle surface opcode sample masks via predication.

The main motivation is to enable HDC surface opcodes on ICL which no longer allows the sample mask to be provided in a message header, but this is enabled all the way back to IVB when possible because it decreases the instruction count of some shaders using HDC messages significantly, e.g. one of

[Mesa-dev] [PATCH 4/6] intel/eu: Plumb header present bit to codegen helpers for HDC messages.

This makes sure that the header-present bit of the message descriptor is in sync with the IR instruction fields, which gives the optimizer more control to avoid the overhead of setting up a message header when it's possible to do so. --- src/intel/compiler/brw_eu.h | 18

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 --- Comment #6 from Brian Paul --- (In reply to Francisco Jerez from comment #5) > Should be fixed in master now, closing. Looks good here. Thanks! -- You are receiving this mail because: You are the assignee for the bug.

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

Quoting Kenneth Graunke (2018-02-27 20:56:29) > On Tuesday, February 27, 2018 12:35:32 AM PST Chris Wilson wrote: > > Quoting Kenneth Graunke (2018-02-27 00:05:46) > > > +static bool > > > +gem_supports_48b_addresses(int fd) > > > +{ > > > + struct drm_i915_gem_exec_object2 obj = { > > > +

[Mesa-dev] [Bug 105274] Buffer overflow in gallium/auxiliary/hud/hud_cpufreq.c

https://bugs.freedesktop.org/show_bug.cgi?id=105274 --- Comment #2 from vesim...@gmail.com --- It is possible in both, you can create directory named "cpu0" and it will be accepted by that sscanf. The easiest fix for it is by using strcpy_s instead of strcpy. -- You are receiving this mail

[Mesa-dev] [AppVeyor] mesa master #7037 completed

Build mesa 7037 completed Commit cb309d27c5 by Francisco Jerez on 1/26/2018 7:48 PM: intel/ir: Fix invalid type aliasing with undefined behavior in test_eu_compact.\n\ntest_fuzz_compact_instruction() was attempting to modify the uint64_t\ndata array of a

[Mesa-dev] [Bug 105052] compiler/test_eu_compact failure with GCC 8

https://bugs.freedesktop.org/show_bug.cgi?id=105052 Francisco Jerez changed: What|Removed |Added Status|NEW |RESOLVED

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 Francisco Jerez changed: What|Removed |Added Status|NEW |RESOLVED

Re: [Mesa-dev] [PATCH] i965: Allow 48-bit addressing on Gen8+.

On Tuesday, February 27, 2018 12:35:32 AM PST Chris Wilson wrote: > Quoting Kenneth Graunke (2018-02-27 00:05:46) > > +static bool > > +gem_supports_48b_addresses(int fd) > > +{ > > + struct drm_i915_gem_exec_object2 obj = { > > + .flags = EXEC_OBJECT_SUPPORTS_48B_ADDRESS, > > + }; > > +

[Mesa-dev] [PATCH 2/4] intel/isl: Add isl_format_is_valid

Signed-off-by: Jordan Justen --- src/intel/isl/gen_format_layout.py | 8 src/intel/isl/isl.h| 2 ++ 2 files changed, 10 insertions(+) diff --git a/src/intel/isl/gen_format_layout.py b/src/intel/isl/gen_format_layout.py index

[Mesa-dev] [PATCH 1/4] intel: Split gen_device_info out into libintel_dev

Signed-off-by: Jordan Justen --- src/intel/Android.dev.mk | 35 ++ src/intel/Makefile.am | 1 + src/intel/Makefile.dev.am | 31 +++

[Mesa-dev] [PATCH 3/4] intel/common: Use isl for decoder surface formats

Signed-off-by: Jordan Justen --- src/intel/common/gen_decoder.c | 8 src/intel/common/meson.build | 1 + src/intel/meson.build | 2 +- 3 files changed, 10 insertions(+), 1 deletion(-) diff --git a/src/intel/common/gen_decoder.c

Re: [Mesa-dev] [PATCH] disk cache: Link with -latomic if necessary

On Tue, Feb 27, 2018 at 2:26 AM, Thierry Reding wrote: > On Mon, Feb 26, 2018 at 11:14:05AM -0800, Matt Turner wrote: >> On Fri, Feb 23, 2018 at 5:18 AM, Thierry Reding >> wrote: >> > From: Thierry Reding >> > >> > The disk

Re: [Mesa-dev] [PATCH 2/2] anv/pipeline: don't pass constant view index in multiview

On Tue, Feb 27, 2018 at 11:46 AM, Caio Marcelo de Oliveira Filho < caio.olive...@intel.com> wrote: > If view mask has only one bit set, view index is effectively a > constant, so doesn't need to be passed to the next stages, just always > set it. > > Part of this was in the original patch that

[Mesa-dev] [PATCH v2 6/7] swr/rast: Faster frustum prim culling

Fix clipper validMask setting. We don't need to run frustum rejected primitives through the clipper. Perform frustum culling with only frustum clip codes. Guardband clip codes cannot be used because they overlap frustum codes. --- src/gallium/drivers/swr/rasterizer/core/clip.h | 10 +++--- 1

[Mesa-dev] [PATCH v2 5/7] swr/rast: Consolidate TRANSLATE_ADDRESS

Translate is now part of an overloaded LOAD call which required a change to the code gen to skip the load functions in order to handle them manually to make them virtual. --- .../swr/rasterizer/codegen/gen_llvm_ir_macros.py | 3 ++- .../drivers/swr/rasterizer/jitter/builder_mem.cpp| 20

[Mesa-dev] [PATCH v2 3/7] swr/rast: Remove draw type from event definitions

- Have the draw type sent to DrawInfoEvent in handlers created in archrast.cpp. The draw type no longer needs to be sent during during AR_API_EVENT() call in api.cpp. - Remove draw type from event defintions in events_private.proto, no longer needed ---

[Mesa-dev] [PATCH v2 7/7] swr/rast: revert clip distance precision

Breaks a whole bunch of piglit tests --- src/gallium/drivers/swr/rasterizer/core/backend_impl.h | 4 +--- src/gallium/drivers/swr/rasterizer/core/binner.cpp | 17 - 2 files changed, 17 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH v2 4/7] swr/rast: Code generation cleanup

Generate more compact code from gen_llvm.hpp. --- .../swr/rasterizer/codegen/templates/gen_llvm.hpp | 36 +- 1 file changed, 21 insertions(+), 15 deletions(-) diff --git a/src/gallium/drivers/swr/rasterizer/codegen/templates/gen_llvm.hpp

[Mesa-dev] [PATCH v2 0/7] Merged 2 patchsets

v2 is a merged patchset of the following email threads: <1519312447-27403-1-git-send-email-george.kyria...@intel.com> <1519317122-3529-1-git-send-email-george.kyria...@intel.com> The cc to mesa-stable is going to be dealt with in a different patch, since the surrounding context is different, and

[Mesa-dev] [PATCH v2 1/7] swr/rast: Fix index buffer overfetch issue for non-indexed draws

Populate pLastIndex, even for the non-indexed case. An zero pLastIndex can cause the index offsets inside the fetcher to have non-sensical values that can be either very large positive or very large negative numbers. v2: split whitespace change into new commit ---

[Mesa-dev] [PATCH v2 2/7] swr/rast: whitespace change

v2: this commit contains whitespace change split from another commit --- src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/gallium/drivers/swr/rasterizer/jitter/fetch_jit.cpp

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On Tue, Feb 27, 2018 at 11:55 AM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Tue, Feb 27, 2018 at 11:46:12AM -0800, Jason Ekstrand wrote: > > On Tue, Feb 27, 2018 at 9:35 AM, Rafael Antognolli < > rafael.antogno...@intel.com > > > wrote: > > > > On Mon, Feb 26, 2018 at

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 --- Comment #4 from Francisco Jerez --- (In reply to Brian Paul from comment #3) > What's going on with this bug? I'm tempted to revert the change soon if it > can't be fixed. It can be fixed, a fix has been on the ML

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On Tue, Feb 27, 2018 at 11:46:12AM -0800, Jason Ekstrand wrote: > On Tue, Feb 27, 2018 at 9:35 AM, Rafael Antognolli > > wrote: > > On Mon, Feb 26, 2018 at 05:04:37PM -0800, Jason Ekstrand wrote: > > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < >

Re: [Mesa-dev] [PATCH 05/21] intel/isl: Use a 4D physical total extent for size calculations

On Tue, Feb 27, 2018 at 4:33 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Thu, Feb 22, 2018 at 11:06:45PM -0800, Jason Ekstrand wrote: > > With Yf and Ys tiling, everything is actually four dimensional because > > we can have multiple depth or multisampled array slices in the

[Mesa-dev] [PATCH 2/2] anv/pipeline: don't pass constant view index in multiview

If view mask has only one bit set, view index is effectively a constant, so doesn't need to be passed to the next stages, just always set it. Part of this was in the original patch that added anv_nir_lower_multiview.c but disabled. --- src/intel/vulkan/anv_nir_lower_multiview.c | 17

[Mesa-dev] [Bug 105238] ast.h:648:16: error: union member 'i' has a non-trivial constructor

https://bugs.freedesktop.org/show_bug.cgi?id=105238 --- Comment #3 from Brian Paul --- What's going on with this bug? I'm tempted to revert the change soon if it can't be fixed. -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact

[Mesa-dev] [PATCH 1/2] anv/pipeline: use less instructions for multiview

The view_index is encoded in the remainder of dividing instance id by the number of views in the view mask (n). In the general case (handled by the else clause), there is a need to map from 0..n-1 into the number of the view being masked. For that a map is encoded. In the case only the first n

Re: [Mesa-dev] [PATCH v3 05/13] intel/genxml: Add Clear Color struct.

On Tue, Feb 27, 2018 at 9:35 AM, Rafael Antognolli < rafael.antogno...@intel.com> wrote: > On Mon, Feb 26, 2018 at 05:04:37PM -0800, Jason Ekstrand wrote: > > On Wed, Feb 21, 2018 at 1:45 PM, Rafael Antognolli < > rafael.antogno...@intel.com > > > wrote: > > > > The size of the clear color

Re: [Mesa-dev] [PATCH 08/21] intel/isl: Implement correct tile size calculations for Ys/Yf

On Tue, Feb 27, 2018 at 6:13 AM, Pohjolainen, Topi < topi.pohjolai...@gmail.com> wrote: > On Thu, Feb 22, 2018 at 11:06:48PM -0800, Jason Ekstrand wrote: > > The tile size calculations use a clever bit of math to make them short > > and simple. We add unit tests to assert that they identically

Re: [Mesa-dev] [PATCH 08/15] glsl: Switch ast_type_qualifier to a 128-bit bitset.

Not my area of expertise, but sure. Reviewed-by: Roland Scheidegger Am 27.02.2018 um 20:14 schrieb Francisco Jerez: > Do you care enough to give me a reviewed-by so I could land it right > away? > > Roland Scheidegger writes: > >> Please don't wait any

[Mesa-dev] [Bug 105274] Buffer overflow in gallium/auxiliary/hud/hud_cpufreq.c

https://bugs.freedesktop.org/show_bug.cgi?id=105274 --- Comment #1 from Gert Wollny --- cpufreq_info::sysfs_filename is a buffer of char[128] and the string fn is of the same size and it is written to by using snprintf, indicating its size, so unless I miss something the

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