Re: [Mesa-dev] [PATCH v2 00/13] query validation fixes

Thanks, _mesa_has makes things a lot cleaner and simpler to manage; Reviewed-by: Tapani Pälli On 11/8/18 2:42 PM, Erik Faye-Lund wrote: Here's v2 of this series. Changes are as follows: - 5/13: also check for ARB_occlusion_query2, for core-contexts - 8/13: also check for

Re: [Mesa-dev] [PATCH 0/3] i965: add support for sampling from AYUV images

Wanted to note that I'm not sure if we need this for Android but if so we will need and entry in platform_android.c droid_yuv_formats table too. It looks like there's no matching HAL format, so it would be a new HAL_PIXEL_FORMAT_IMPLEMENTATION_DEFINED entry. On 11/8/18 8:23 PM, Lionel

Re: [Mesa-dev] [PATCH 2/3] dri: add AYUV format

Reviewed-by: Tapani Pälli On 11/8/18 8:23 PM, Lionel Landwerlin wrote: Signed-off-by: Lionel Landwerlin --- include/GL/internal/dri_interface.h | 2 ++ src/egl/drivers/dri2/egl_dri2.c | 1 + 2 files changed, 3 insertions(+) diff --git a/include/GL/internal/dri_interface.h

Re: [Mesa-dev] [PATCH v2] glsl: Correct several built-in functions availability

On 2/11/18 6:41 am, Ian Romanick wrote: On 10/31/2018 03:05 PM, Timothy Arceri wrote: If we are going to start tightening up this stuff I would really really like to see CTS tests (not piglit tests) to go along with this stuff. We are already way stricter with these type of things than the

[Mesa-dev] [PATCH B 10/14] nir/opt_algebraic: Drop bit-size suffixes from conversions

Suffixes are dropped from a bunch of conversion opcodes when it makes sense to do so. Others are kept if we really do want the bit-size restriction. --- src/compiler/nir/nir_opt_algebraic.py | 58 +-- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git

[Mesa-dev] [PATCH B 14/14] FIXUP: Fix NIR producers and consumers to use unsized conversions

--- src/amd/common/ac_nir_to_llvm.c | 12 src/compiler/glsl/glsl_to_nir.cpp | 2 +- src/compiler/nir/nir_builder.h| 12 src/compiler/spirv/vtn_glsl450.c | 4 ++-- .../drivers/freedreno/ir3/ir3_compiler_nir.c | 11

[Mesa-dev] [PATCH B 07/14] nir/algebraic: Refactor codegen a bit

Instead of using an OrderedDict, just have a (necessarily sorted) array of transforms and a set of opcodes. --- src/compiler/nir/nir_algebraic.py | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py

[Mesa-dev] [PATCH B 12/14] nir: Make boolean conversions sized just like the others

Instead of a single i2b and b2i, we now have i2b32 and b2iN where N is one if 8, 16, 32, or 64. This leads to having a few more opcodes but now everything is consistent and booleans aren't a weird special case anymore. --- src/compiler/nir/nir.h | 4 ++--

[Mesa-dev] [PATCH B 08/14] nir/algebraic: Add support for unsized conversion opcodes

All conversion opcodes require a destination size but this makes constructing certain algebraic expressions rather cumbersome. This commit adds support to nir_search and nir_algebraic for writing conversion opcodes without a size. These meta-opcodes match any conversion of that type regardless

[Mesa-dev] [PATCH B 13/14] FIXUP: nir/opt_algebraic: Add suffixes to some x2b opcodes

Many of the x2b optimizations in nir_opt_algebraic can be handled by the generic untyped conversion opcodes we just added. However, there are a few that still need an explicit size for some reason. --- src/compiler/nir/nir_opt_algebraic.py | 14 +++--- 1 file changed, 7 insertions(+), 7

[Mesa-dev] [PATCH B 09/14] nir/opt_algebraic: Simplify an optimization using the new search ops

--- src/compiler/nir/nir_opt_algebraic.py | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 8b24daddfdc..cda0aaf17f5 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++

[Mesa-dev] [PATCH B 11/14] nir/opt_algebraic: Add 32-bit specifiers to a bunch of booleans

--- src/compiler/nir/nir_opt_algebraic.py | 112 +- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 75a34e4a673..aeed5a8e4da 100644 ---

[Mesa-dev] [PATCH 13/14] FIXUP: nir/opt_algebraic: Add suffixes to some x2b opcodes

Many of the x2b optimizations in nir_opt_algebraic can be handled by the generic untyped conversion opcodes we just added. However, there are a few that still need an explicit size for some reason. --- src/compiler/nir/nir_opt_algebraic.py | 14 +++--- 1 file changed, 7 insertions(+), 7

[Mesa-dev] [PATCH 12/14] nir: Make boolean conversions sized just like the others

Instead of a single i2b and b2i, we now have i2b32 and b2iN where N is one if 8, 16, 32, or 64. This leads to having a few more opcodes but now everything is consistent and booleans aren't a weird special case anymore. --- src/compiler/nir/nir.h | 4 ++--

[Mesa-dev] [PATCH 11/14] nir/opt_algebraic: Add 32-bit specifiers to a bunch of booleans

--- src/compiler/nir/nir_opt_algebraic.py | 112 +- 1 file changed, 56 insertions(+), 56 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 75a34e4a673..aeed5a8e4da 100644 ---

[Mesa-dev] [PATCH 10/14] nir/opt_algebraic: Drop bit-size suffixes from conversions

Suffixes are dropped from a bunch of conversion opcodes when it makes sense to do so. Others are kept if we really do want the bit-size restriction. --- src/compiler/nir/nir_opt_algebraic.py | 58 +-- 1 file changed, 29 insertions(+), 29 deletions(-) diff --git

[Mesa-dev] [PATCH 14/14] FIXUP: Fix NIR producers and consumers to use unsized conversions

--- src/amd/common/ac_nir_to_llvm.c | 12 src/compiler/glsl/glsl_to_nir.cpp | 2 +- src/compiler/nir/nir_builder.h| 12 src/compiler/spirv/vtn_glsl450.c | 4 ++-- .../drivers/freedreno/ir3/ir3_compiler_nir.c | 11

[Mesa-dev] [PATCH A 15/15] nir: Make boolean conversions unsized like other types

--- src/compiler/glsl/glsl_to_nir.cpp | 2 +- src/compiler/nir/nir_builder.h | 12 src/compiler/nir/nir_lower_idiv.c | 2 +- src/compiler/nir/nir_lower_int64.c | 2 +- src/compiler/nir/nir_opcodes.py | 11 +++ src/compiler/spirv/vtn_glsl450.c| 4 ++--

[Mesa-dev] [PATCH A 14/15] nir/algebraic: Add 32-bit specifiers to a bunch of booleans

--- src/compiler/nir/nir_opt_algebraic.py | 116 +- 1 file changed, 58 insertions(+), 58 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 6ce65c4ad10..42dd1e2f980 100644 ---

[Mesa-dev] [PATCH 07/14] nir/algebraic: Refactor codegen a bit

Instead of using an OrderedDict, just have a (necessarily sorted) array of transforms and a set of opcodes. --- src/compiler/nir/nir_algebraic.py | 21 +++-- 1 file changed, 11 insertions(+), 10 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py

[Mesa-dev] [PATCH A 11/15] nir: Switch conversions to unsized opcodes

--- src/compiler/nir/nir.c| 67 ++ src/compiler/nir/nir_opcodes.py | 38 +++ src/compiler/nir/nir_opcodes_c.py | 79 --- 3 files changed, 83 insertions(+), 101 deletions(-) diff --git a/src/compiler/nir/nir.c

[Mesa-dev] [PATCH 09/14] nir/opt_algebraic: Simplify an optimization using the new search ops

--- src/compiler/nir/nir_opt_algebraic.py | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/compiler/nir/nir_opt_algebraic.py b/src/compiler/nir/nir_opt_algebraic.py index 8b24daddfdc..cda0aaf17f5 100644 --- a/src/compiler/nir/nir_opt_algebraic.py +++

[Mesa-dev] [PATCH A 10/15] nir/algebraic: Add support for unsized conversion opcodes

Unsized conversion opcodes require special handling in opt_algebraic because they fallow different bit size rules from regular opcodes. In particular, we now have a new case where we have an opcode with multiple variable-size inputs and outputs but no common size. ---

[Mesa-dev] [PATCH 05/15] nir/algebraic: Clean up some __str__ cruft

Both of these things are already handled in the Value base class so we don't need to handle them explicitly in Constant. --- src/compiler/nir/nir_algebraic.py | 4 1 file changed, 4 deletions(-) diff --git a/src/compiler/nir/nir_algebraic.py b/src/compiler/nir/nir_algebraic.py index

[Mesa-dev] [PATCH A 12/15] FIXUP: Fix NIR producers and consumers to use unsized conversions

--- src/amd/common/ac_nir_to_llvm.c | 32 ++-- src/gallium/auxiliary/nir/tgsi_to_nir.c | 8 +- .../drivers/freedreno/ir3/ir3_compiler_nir.c | 148 -- src/gallium/drivers/vc4/vc4_program.c | 8 +- src/intel/compiler/brw_fs_nir.cpp | 78

[Mesa-dev] [PATCH A 07/15] nir: Add a concept of an unsized conversion opcode

--- src/compiler/nir/nir.h| 7 src/compiler/nir/nir_opcodes.py | 61 +-- src/compiler/nir/nir_opcodes_c.py | 1 + src/compiler/nir/nir_validate.c | 4 ++ 4 files changed, 45 insertions(+), 28 deletions(-) diff --git a/src/compiler/nir/nir.h

[Mesa-dev] [PATCH A 13/15] FIXUP: nir/opt_algebraic: Drop bit-size suffixes from conversions

Some suffixes are straight-up dropped when it makes sense while others are converted to the @bit-size form because we really do require an exact size in order for the expression to be well-formed. --- src/compiler/nir/nir_opt_algebraic.py | 79 +-- 1 file changed, 37

[Mesa-dev] [PATCH 08/14] nir/algebraic: Add support for unsized conversion opcodes

All conversion opcodes require a destination size but this makes constructing certain algebraic expressions rather cumbersome. This commit adds support to nir_search and nir_algebraic for writing conversion opcodes without a size. These meta-opcodes match any conversion of that type regardless

[Mesa-dev] [PATCH A 08/15] nir/builder: Create sized helpers for unsized conversion opcodes

Because we need to know the size and we can't infer it from the source, we add a suffixed builder helper for each possible destination size the opcode supports. --- src/compiler/nir/nir_builder.h| 18 +++--- src/compiler/nir/nir_builder_opcodes_h.py | 16 ++--

[Mesa-dev] [PATCH 06/15] nir/algebraic: Improve error messages for replace expressions

In bf441d22a7917f38c, I wrote a bunch of descriptive asserts for various bit size checks in the validation of search expressions. This commit improves a few of those and adds descriptive asserts for replace expressions as well. We also rework _validate_bit_class_down so that it can properly

[Mesa-dev] [PATCH 02/15] nir/opcodes: Rename tbool to tbool32

--- src/compiler/nir/nir_opcodes.py | 22 +++--- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/src/compiler/nir/nir_opcodes.py b/src/compiler/nir/nir_opcodes.py index d69d09d30ce..00720708305 100644 --- a/src/compiler/nir/nir_opcodes.py +++

[Mesa-dev] [PATCH 00/15] nir: Rework boolean (and maybe all?) conversions

Welcome to this choose-your-own-adventure patch series! The first six patches are good-to-go regardless of choices made later. However, starting with patch 7, we have a choice to make. Version A of this series reworks NIR conversion opcodes to not have sizes and instead simply accept any source

[Mesa-dev] [PATCH A 09/15] nir/constant_expressions: Handle unsized conversion ops

--- src/compiler/nir/nir_constant_expressions.h | 3 +- src/compiler/nir/nir_constant_expressions.py | 34 src/compiler/nir/nir_loop_analyze.c | 7 ++-- src/compiler/nir/nir_opt_constant_folding.c | 5 +-- src/compiler/spirv/spirv_to_nir.c| 3 +- 5

[Mesa-dev] [PATCH 01/15] nir/opcodes: Pull in the type helpers from constant_expressions

While we're at it, we rework them a bit to all use regular expressions and assert more. --- src/compiler/nir/nir_constant_expressions.py | 25 ++ src/compiler/nir/nir_opcodes.py | 34 +--- src/compiler/nir/nir_opcodes_c.py| 11 ++- 3 files

[Mesa-dev] [PATCH 03/15] nir/algebraic: Improve a couple error messages

There is a possible functional change here because we're now using canonical bit classes in the check in validate(). If anything, it should be more precise than the old check. The other changes just make us print out the canonical classes in the error messages. We do this because, if we have an

[Mesa-dev] [PATCH 04/15] nir/algebraic: Set variable classes to the explicit bit size

Previously, we were checking for a matching bit size late when propagating bit sizes back down the tree by checking if the variable had an explicit bit size and if it matched the requested bit class. However, this check wasn't quite as accurate because it didn't handle the case where an explicitly

[Mesa-dev] [PATCH] intel/fs: Prevent emission of IR instructions not aligned to their own execution size.

This can occur during payload setup of SIMD-split send message instructions, which can lead to the emission of header setup instructions with a non-zero channel group and fixed SIMD width. Such instructions could end up using undefined channel enable signals except they don't care since they're

[Mesa-dev] [PATCH v3] Allow fd.o to join forces with X.Org

The leadership of freedesktop.org (fd.o) has recently expressed interest in having an elected governing body. Given the tight connection between fd.o and X.Org and the fact that X.Org has such a governing body it seemed obvious to consider extending X.Org's mandate to fd.o. Quite a bit of

Re: [Mesa-dev] [PATCH 06/13] anv: move helper function internally

I left a nit on 3. Otherwise, 1-6 are Reviewed-by: Jason Ekstrand On Mon, Nov 5, 2018 at 9:36 AM Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > It's only used in anv_image.c > > Signed-off-by: Lionel Landwerlin > --- > src/intel/vulkan/anv_image.c | 22 ++

Re: [Mesa-dev] [PATCH 03/13] anv/lower_ycbcr: make sure to set 0s on all components

On Mon, Nov 5, 2018 at 9:36 AM Lionel Landwerlin < lionel.g.landwer...@intel.com> wrote: > To play around with debugging, we might want to disable one or the > other component. Having 0s as default values makes this work. > Otherwise we might have NULL components, leading to crashes. > >

Re: [Mesa-dev] [PATCH 6/7] RFC: nir/xfb_info: arrays of basic types adds just one varying

On Thu, Nov 8, 2018 at 7:22 AM Alejandro Piñeiro wrote: > On OpenGL, a array of a simple type adds just one varying. So > gl_transform_feedback_varying_info struct defined at mtypes.h includes > the parameters Type (base_type) and Size (number of elements). > > This commit checks this when the

Re: [Mesa-dev] [PATCH 4/7] nir: add component_offset at nir_xfb_info

This is fine. For Intel hardware, the component mask is actually what we need and I figured ffs(component_mask) - 1 and bitcount(component_mask) wasn't all that onerous. I don't care all that much though. Of we're going this direction, maybe just do size+offset and we can compute the mask in

Re: [Mesa-dev] [PATCH 3/3] egl: Improve the debugging of gbm format matching in DRI configs.

On Thu, 8 Nov 2018 at 18:01, Eric Anholt wrote: > Previously the debug would be: > > libEGL debug: No DRI config supports native format 0x20203852 > libEGL debug: No DRI config supports native format 0x38385247 > > but > > libEGL debug: No DRI config supports native format R8 > libEGL debug: No

Re: [Mesa-dev] [PATCH 3/7] nir: fix output offset compute for dvec3/4

On Thu, Nov 8, 2018 at 7:22 AM Alejandro Piñeiro wrote: > The offset compute was working fine for the case of attrib_slots=1, > and updating the offset for the following varying. > > But in the case of attrib_slots=2 (so dvec3/4), we are basically > splitting the comp_slots needed in two

Re: [Mesa-dev] [PATCH 2/7] nir: don't assert when xfb_buffer/stride is present but not xfb_offset

On Thu, Nov 8, 2018 at 7:22 AM Alejandro Piñeiro wrote: > In order to allow nir_gather_xfb_info to be used on OpenGL, > specifically ARB_gl_spirv. > > So, from OpenGL 4.6 spec, section 11.1.2.1, "Output Variables": > > "outputs specifying both an *XfbBuffer* and an *Offset* are >

Re: [Mesa-dev] [PATCH 1/7] spirv/nir: update Xfb decoration comment

On Thu, Nov 8, 2018 at 7:22 AM Alejandro Piñeiro wrote: > Although it is true that Vulkan doesn't support transform feedback > yet, spirv to nir is handling it due ARB_gl_spirv support. Having said > so, those decorations are handled elsewhere. > Actually, the RADV guys shipped their patches

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] i965: Set ForceZeroRTAIndexEnable based on slots_valid

On Thu, Nov 8, 2018 at 9:32 AM Emil Velikov wrote: > Hi Jason, > > On Sat, 27 Oct 2018 at 22:35, Jason Ekstrand wrote: > > > > Instead of setting it based on the number of layers in the framebuffer, > > disable it whenever the shader does not explicitly write the value. > > Otherwise, if the

Re: [Mesa-dev] [PATCH v2 2/2] i965: Implement ARB_compute_variable_group_size.

any update on that? I could take care of extracting the bits myself, I was just expecting that you would take care of that. On Thu, Jun 28, 2018 at 6:53 PM Manolova, Plamena wrote: > > Hi Karol, > Thank you for reviewing! I'll go ahead and push the changes you need from >

[Mesa-dev] [PATCH] freedreno/drm: Move drm_msm.h to include/drm-uapi

So the future Vulkan driver can share it. I tested Meson, but not Autotools nor Android.mk. Signed-off-by: Chad Versace --- Makefile.am| 1 + .../drivers/freedreno/drm => include/drm-uapi}/msm_drm.h | 0

[Mesa-dev] [PATCH] i965: Fix -Wswitch on INTEL_COPY_STREAMING_LOAD

The warning is emitted when building without INLINE_SSE41. --- src/mesa/drivers/dri/i965/intel_tiled_memcpy.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c b/src/mesa/drivers/dri/i965/intel_tiled_memcpy.c index

Re: [Mesa-dev] [PATCH v2] nir: add new linking opt nir_move_out_const_to_consumer()

On 9/11/18 6:53 am, Samuel Pitoiset wrote: On 11/7/18 9:36 AM, Timothy Arceri wrote: This pass moves constant outputs to the consuming shader stage where possible. V2: limit pass to scalars for now ---   V2 doesn't change any shader-db/vkpipeline-db results as all 32bit   varyings that we

Re: [Mesa-dev] [PATCH] i965: Lift restriction in external textures for EGLImage support

On Thu 08 Nov 2018, Chad Versace wrote: > On Wed 31 Oct 2018, Aditya Swarup wrote: > > For Intel platforms, we support external textures only for EGLImages > > created with EGL_EXT_image_dma_buf_import. This restriction seems to > > be Intel specific and not present for other platforms. > > > >

Re: [Mesa-dev] [PATCH] i965: Lift restriction in external textures for EGLImage support

On Wed 31 Oct 2018, Aditya Swarup wrote: > For Intel platforms, we support external textures only for EGLImages > created with EGL_EXT_image_dma_buf_import. This restriction seems to > be Intel specific and not present for other platforms. > > While running SKQP test - unitTest_EGLImageTest,

Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: adjust the VGT workaround for prim restart on GFX9

On 11/8/18 5:49 PM, Emil Velikov wrote: On Thu, 8 Nov 2018 at 16:01, Samuel Pitoiset wrote: On 11/8/18 4:43 PM, Emil Velikov wrote: HI guys, On Tue, 16 Oct 2018 at 22:06, Marek Olšák wrote: On Thu, Oct 11, 2018 at 4:43 AM Samuel Pitoiset wrote: WD_SWITCH_ON_EOP seems to be the only

Re: [Mesa-dev] [PATCH v2] nir: add new linking opt nir_move_out_const_to_consumer()

On 11/7/18 9:36 AM, Timothy Arceri wrote: This pass moves constant outputs to the consuming shader stage where possible. V2: limit pass to scalars for now --- V2 doesn't change any shader-db/vkpipeline-db results as all 32bit varyings that we don't skip are already scalar. V2 just avoids

Re: [Mesa-dev] [PATCH] radv: include LLVM IR in the VK_AMD_shader_info "disassembly"

On 11/8/18 4:15 PM, Nicolai Hähnle wrote: From: Nicolai Hähnle Helpful for debugging compiler backend problems: this allows us to easily retrieve the LLVM IR from RenderDoc. -- For the peanut gallery: AMD's official stance on radv hasn't changed. But we take regressions for radv caused by

Re: [Mesa-dev] [PATCH v2] nir: add new linking opt nir_move_out_const_to_consumer()

Timothy Arceri writes: > This pass moves constant outputs to the consuming shader stage > where possible. > > V2: limit pass to scalars for now > --- > > V2 doesn't change any shader-db/vkpipeline-db results as all 32bit > varyings that we don't skip are already scalar. V2 just avoids a >

Re: [Mesa-dev] [PATCH] intel/l3: update ICL L3 configurations

Lionel, I have this patch along with few other patches in my 'icl-urb-configs' branch at https://github.com/aphogat/mesa. But, I'm getting many piglit regressions with these patches. That's the reason I haven't sent them out to the list. I also talked to Ken about my changes. Unfortunately we

[Mesa-dev] [PATCH 2/3] dri: add AYUV format

Signed-off-by: Lionel Landwerlin --- include/GL/internal/dri_interface.h | 2 ++ src/egl/drivers/dri2/egl_dri2.c | 1 + 2 files changed, 3 insertions(+) diff --git a/include/GL/internal/dri_interface.h b/include/GL/internal/dri_interface.h index 6f9c2c8b8cf..072f3799eac 100644 ---

[Mesa-dev] [PATCH 3/3] i965: add support for sampling from AYUV

Signed-off-by: Lionel Landwerlin --- src/intel/compiler/brw_compiler.h| 1 + src/intel/compiler/brw_nir.c | 1 + src/mesa/drivers/dri/i965/brw_wm.c | 6 ++ src/mesa/drivers/dri/i965/intel_screen.c | 3 +++ 4 files changed, 11 insertions(+) diff --git

[Mesa-dev] [PATCH 1/3] nir/lower_tex: Add AYUV lowering support

Signed-off-by: Lionel Landwerlin --- src/compiler/nir/nir.h | 1 + src/compiler/nir/nir_lower_tex.c | 36 ++-- 2 files changed, 31 insertions(+), 6 deletions(-) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index f4f6b106505..2a843de8ae1

[Mesa-dev] [PATCH 0/3] i965: add support for sampling from AYUV images

Hi all, This series is a copycat of what Johnson Lin did to add UYVY support a while ago, only this time adding AYUV. Hopefully I didn't get the byte ordering as I had to write the piglit tests for it too :) https://patchwork.freedesktop.org/series/52254/ Cheers, Lionel Landwerlin (3):

[Mesa-dev] [Bug 35268] initial-exec TLS model breaks dlopen'ed libGL

https://bugs.freedesktop.org/show_bug.cgi?id=35268 --- Comment #29 from Rich Felker --- It turns out there's more code that needs to be refitted or removed from src/mapi/entry_*_tls.h, including powerpc64le asm I wasn't aware of before. There's a lot of code to generate executable stubs at

[Mesa-dev] [PATCH 1/3] gbm: Move gbm_format_canonicalize() to the core.

I want it for the format name debugging code. --- src/gbm/backends/dri/gbm_dri.c | 16 src/gbm/main/gbm.c | 16 src/gbm/main/gbmint.h | 3 +++ 3 files changed, 19 insertions(+), 16 deletions(-) diff --git a/src/gbm/backends/dri/gbm_dri.c

[Mesa-dev] [PATCH 3/3] egl: Improve the debugging of gbm format matching in DRI configs.

Previously the debug would be: libEGL debug: No DRI config supports native format 0x20203852 libEGL debug: No DRI config supports native format 0x38385247 but libEGL debug: No DRI config supports native format R8 libEGL debug: No DRI config supports native format GR88 is a lot easier to

[Mesa-dev] [PATCH 2/3] gbm: Introduce a helper function for printing GBM format names.

This requires that the caller make a little (stack) allocation to store the string. v2: Use gbm_format_canonicalize (suggested by Daniel) --- src/gbm/main/gbm.c | 20 src/gbm/main/gbm.h | 6 ++ 2 files changed, 26 insertions(+) diff --git a/src/gbm/main/gbm.c

Re: [Mesa-dev] [PATCH EGL/MESA] EGL/mesa: Initial writeup for MESA_query_renderer

On Thu, 2018-11-08 at 02:42 +0530, Veluri Mithun wrote: > Hi all, > Thanks Adam for your interest in this. > > > > +New Tokens > > > + > > > +Accepted as an in EGLQueryRendererIntegerMESA and > > > +EGLQueryCurrentRendererIntegerMESA: > > > + > > > +EGL_RENDERER_VENDOR_ID_MESA

Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: adjust the VGT workaround for prim restart on GFX9

On Thu, 8 Nov 2018 at 16:01, Samuel Pitoiset wrote: > > On 11/8/18 4:43 PM, Emil Velikov wrote: > > HI guys, > > > > On Tue, 16 Oct 2018 at 22:06, Marek Olšák wrote: > >> > >> On Thu, Oct 11, 2018 at 4:43 AM Samuel Pitoiset > >> wrote: > >>> > >>> WD_SWITCH_ON_EOP seems to be the only

Re: [Mesa-dev] [PATCH] gallivm: fix improper clamping of vertex index when fetching gs inputs

Am 08.11.18 um 14:59 schrieb Jose Fonseca: > Good find. > > On 08/11/2018 01:54, srol...@vmware.com wrote: >> From: Roland Scheidegger >> >> Because we only have one file_max for the (2d) gs input file, the value >> actually represents the max of attrib and vertex index (although I'm >> not

[Mesa-dev] [AppVeyor] mesa staging/18.3 #9274 completed

Build mesa 9274 completed Commit 4c995fcae7 by Gert Wollny on 11/1/2018 9:49 AM: virgl/vtest-winsys: Use virgl version of bind flags\n\nThe bind flags defined by mesa/gallium might not always be in sync\nwith the ones copied to virglrenderer/gallium.

[Mesa-dev] [AppVeyor] mesa master #9273 failed

Build mesa 9273 failed Commit d28bc35ece by Jason Ekstrand on 11/7/2018 9:47 PM: intel/fs: Add an assert to optimize_frontfacing_ternary\n\nReviewed-by: Kenneth Graunke Configure your notification preferences

Re: [Mesa-dev] [PATCH] virgl/vtest-winsys: Use virgl version of bind flags

On Fri, 2 Nov 2018 at 15:23, Emil Velikov wrote: > > On Thu, 1 Nov 2018 at 09:50, Gert Wollny wrote: > > > > From: Gert Wollny > > > > The bind flags defined by mesa/gallium might not always be in sync > > with the ones copied to virglrenderer/gallium. Therefore, use the > > flags defined in

Re: [Mesa-dev] [PATCH 1/2] i965/state: Set CullTestEnableBitmask based on the last geometry stage

On Thu, Nov 8, 2018 at 9:34 AM Emil Velikov wrote: > On Sat, 27 Oct 2018 at 22:34, Jason Ekstrand wrote: > > > > Instead of hard-coding it to look at the VS stage, look at whatever the > > last geometry stage is. > > > > Cc: mesa-sta...@lists.freedesktop.org > > --- > >

Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: adjust the VGT workaround for prim restart on GFX9

On 11/8/18 4:43 PM, Emil Velikov wrote: HI guys, On Tue, 16 Oct 2018 at 22:06, Marek Olšák wrote: On Thu, Oct 11, 2018 at 4:43 AM Samuel Pitoiset wrote: WD_SWITCH_ON_EOP seems to be the only workaround that fixes the GPU hangs with Yakuza and The Evil Within on Vega. I don't like as it

Re: [Mesa-dev] [PATCH 0/5] add support for EXT_shader_implicit_conversions

On Fri, 2 Nov 2018 at 16:06, Erik Faye-Lund wrote: > > On Fri, 2018-11-02 at 15:40 +, Emil Velikov wrote: > > On Tue, 30 Oct 2018 at 17:11, Erik Faye-Lund > > wrote: > > > EXT_shader_implicit_conversions is a useful extension that adds > > > implicit > > > conversions to OpenGL ES 3.1. Since

Re: [Mesa-dev] [Mesa-stable] [PATCH] mapi: avoid text relocation in x86 tsd stubs

On Fri, 2 Nov 2018 at 00:02, Jonathan Gray wrote: > > On Thu, Nov 01, 2018 at 12:26:34PM -0700, Ian Romanick wrote: > > On 10/31/2018 09:08 PM, Jonathan Gray wrote: > > > Make similiar changes to libglvnd to avoid a text relocation in > > > x86 tsd stubs fixing the build with lld. > > > > > >

Re: [Mesa-dev] [PATCH EGL/MESA] EGL/mesa: Initial write up for EGL_MESA_query_driver

Hi Rob, FYI, we are implementing this extension for getScreenDriver and getDrvierConfig functions. This extension is different from queryRenderer. Thanks, Veluri. On Mon, Nov 5, 2018 at 11:38 PM Veluri Mithun wrote: > Signed-off-by: Veluri Mithun > --- >

Re: [Mesa-dev] [PATCH v3] autotools: library-dependency when no sse and 32-bit

On Thu, 1 Nov 2018 at 11:03, Sergii Romantsov wrote: > > Building of 32bit Mesa may fail if __SSE__ is not specified. > Added missed dependency from libm. > > v2: avoided dependecy on any flag, just link > > v3: meson doesn't fail, but have added dependency on libm > > CC: Dylan Baker > CC:

Re: [Mesa-dev] [Mesa-stable] [PATCH] radv: adjust the VGT workaround for prim restart on GFX9

HI guys, On Tue, 16 Oct 2018 at 22:06, Marek Olšák wrote: > > On Thu, Oct 11, 2018 at 4:43 AM Samuel Pitoiset > wrote: > > > > WD_SWITCH_ON_EOP seems to be the only workaround that fixes > > the GPU hangs with Yakuza and The Evil Within on Vega. I don't > > like as it might decrease geometry

Re: [Mesa-dev] [PATCH 1/2] i965/state: Set CullTestEnableBitmask based on the last geometry stage

On Sat, 27 Oct 2018 at 22:34, Jason Ekstrand wrote: > > Instead of hard-coding it to look at the VS stage, look at whatever the > last geometry stage is. > > Cc: mesa-sta...@lists.freedesktop.org > --- > src/mesa/drivers/dri/i965/genX_state_upload.c | 14 +- > 1 file changed, 13

Re: [Mesa-dev] [PATCH EGL/MESA] EGL/mesa: Initial writeup for MESA_query_renderer

On Wed, Nov 7, 2018 at 4:12 PM Veluri Mithun wrote: > > Hi all, > Thanks Adam for your interest in this. > >> > +New Tokens >> > + >> > +Accepted as an in EGLQueryRendererIntegerMESA and >> > +EGLQueryCurrentRendererIntegerMESA: >> > + >> > +EGL_RENDERER_VENDOR_ID_MESA

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] i965: Set ForceZeroRTAIndexEnable based on slots_valid

Hi Jason, On Sat, 27 Oct 2018 at 22:35, Jason Ekstrand wrote: > > Instead of setting it based on the number of layers in the framebuffer, > disable it whenever the shader does not explicitly write the value. > Otherwise, if the shader doesn't write the value but you do have a > layered

Re: [Mesa-dev] [Mesa-stable] [PATCH] vulkan/wsi/wayland: Respect non-blocking AcquireNextImage

Hi Dan, On Tue, 30 Oct 2018 at 12:57, Daniel Stone wrote: > > If the client has requested that AcquireNextImage not block at all, with > a timeout of 0, then don't make any non-blocking calls. > > This will still potentially block infinitely given a non-infinte > timeout, but the fix for that is

[Mesa-dev] [PATCH v4 10/10] intel/genxml: Add engine definition to render engine instructions (gen11)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine definition

[Mesa-dev] [PATCH v4 08/10] intel/genxml: Add engine definition to render engine instructions (gen9)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added more missing engine

[Mesa-dev] [PATCH v4 04/10] intel/genxml: Add engine definition to render engine instructions (gen6)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to

[Mesa-dev] [PATCH v4 06/10] intel/genxml: Add engine definition to render engine instructions (gen75)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. --- src/intel/genxml/gen75.xml | 214

[Mesa-dev] [PATCH v4 05/10] intel/genxml: Add engine definition to render engine instructions (gen7)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. --- src/intel/genxml/gen7.xml | 166

[Mesa-dev] [PATCH v4 03/10] intel/genxml: Add engine definition to render engine instructions (gen5)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. --- src/intel/genxml/gen5.xml | 60

[Mesa-dev] [PATCH v4 02/10] intel/genxml: Add engine definition to render engine instructions (gen45)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added addition engine definitions. --- src/intel/genxml/gen45.xml | 54

[Mesa-dev] [PATCH v4 09/10] intel/genxml: Add engine definition to render engine instructions (gen10)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine definition

[Mesa-dev] [PATCH v4 07/10] intel/genxml: Add engine definition to render engine instructions (gen8)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. v4: Added missing engine tag for

[Mesa-dev] [PATCH v4 01/10] intel/genxml: Add engine definition to render engine instructions (gen4)

Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions. --- src/intel/genxml/gen4.xml | 50

[Mesa-dev] [PATCH] radv: include LLVM IR in the VK_AMD_shader_info "disassembly"

From: Nicolai Hähnle Helpful for debugging compiler backend problems: this allows us to easily retrieve the LLVM IR from RenderDoc. -- For the peanut gallery: AMD's official stance on radv hasn't changed. But we take regressions for radv caused by our changes in LLVM seriously. After all, they

[Mesa-dev] [PATCH 1/9] bin/get-pick-list.sh: simplify git oneline printing

From: Emil Velikov Currently we force disable the pager via "|cat" where --no-pager exists. Additionally we could use git show instead of git log -n1. Use those for a slightly more understandable code. Signed-off-by: Emil Velikov Reviewed-by: Eric Engestrom --- bin/get-pick-list.sh | 2 +-

[Mesa-dev] [PATCH 0/9] Enhance the get-pick-list.sh script

Hi all, This is a v2 of the earlier series "Fold typod/fixes scripts within get-pick-list.sh" with updates, few tweaks and extra typos/mistakes that we've been doing. Patches 1-4: original (with comments addressed) and $sha passed as argument to the functions Patch 5: fixups the sed pattern to

[Mesa-dev] [PATCH 8/9] bin/get-pick-list.sh: handle unofficial "broken by" tag

From: Emil Velikov We have a number of cases were devs will use a tag "broken by". While it's not something officially documented or recommended, checking for it is trivial enough. Signed-off-by: Emil Velikov --- bin/get-pick-list.sh | 9 - 1 file changed, 8 insertions(+), 1

[Mesa-dev] [PATCH 5/9] bin/get-pick-list.sh: tweak the commit sha matching pattern

From: Emil Velikov Currently we match on: - any arbitrary length of, - any a-z A-Z and 0-9 characters At the same time, a commit sha consists of lowercase hexadecimal numbers. Any sha shorter than 8 characters is ambiguous - in some cases even 11+ are required. So change the pattern to

[Mesa-dev] [PATCH 9/9] bin/get-pick-list.sh: use test instead of [ ]

From: Emil Velikov Latter is rather picky wrt surrounding white space. The explicit `test` doesn't have that problem, plus the statements read a bit easier. Signed-off-by: Emil Velikov --- bin/get-pick-list.sh | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH 4/9] bin/get-pick-list.sh: handle the fixes tag

From: Emil Velikov Having a separate script to handle the fixes tag, brings a number of issues, so let's fold it in get-pick-list.sh. v2: - pass the sha as argument to the function - Keep original sed pattern Signed-off-by: Emil Velikov --- bin/get-fixes-pick-list.sh | 81

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