Re: [Mesa-dev] Lets talk about autotools

Quoting Dylan Baker (2018-09-17 09:44:07) > I feel like for !windows meson is in good enough shape at this point that we > can start having the discussion about deleting the autotools build. So, is > there > anything left that autotools can do that meson cannot (that we actually want > to >

Re: [Mesa-dev] [PATCH v2 2/5] gallium: Add new PIPE_CAP_MULTISAMPLED_RENDER_TO_TEXTURE

I think the name PIPE_CAP_MULTISAMPLED_RENDER_TO_TEXTURE is slightly misleading, because it doesn't imply anything about the OpenGL ES behavior, which is that a texture is multisampled in the cache, but single-sampled in memory. This should be mentioned somewhere. Marek On Tue, Nov 6, 2018 at

Re: [Mesa-dev] [PATCH] st/mesa: Don't record garbage streamout information in the non-SSO case.

You can try to remove streamout.stride_in_dw and get it directly from the correct shader where stride_in_dw is used. Marek On Wed, Nov 14, 2018 at 12:55 PM Gert Wollny wrote: > Hi Kenneth, > > unfortunately this patch breaks r600. I tried to dig into it to figure > out where things going wrong

Re: [Mesa-dev] [PATCH 08/12] configure.ac: deprecate --with-llvm-prefix

On Thu, Nov 8, 2018 at 6:39 AM Emil Velikov wrote: > On Wed, 7 Nov 2018 at 21:23, Jan Vesely wrote: > > > yes. as long as the setting survives reconfigure+rebuild I'm fine. > The provided option works in the usecase you're interested. I'm not > sure why we're debating this bth. > Can you

[Mesa-dev] [PATCH 21/21] intel/fs: Use split sends for surface writes on gen9+

Surface reads don't need them because they just have the one address payload. With surface writes, on the other hand, we can put the address and the data in the different halves and avoid building the payload all together. --- src/intel/compiler/brw_fs.cpp | 50

[Mesa-dev] [PATCH 17/21] intel/inst: Indent some code

We're about to add some more if cases so let's have the giant re-indent in it's own patch to make review easier. --- src/intel/compiler/brw_eu_emit.c | 360 --- 1 file changed, 183 insertions(+), 177 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c

[Mesa-dev] [PATCH 16/21] intel/inst: Fix the ia16_addr_imm helpers

These have clearly never seen any use On gen8, the bottom 4 bits are missing so we need to shift them off before we call set_bits and shift again when we get the bits. Found by inspection. --- src/intel/compiler/brw_inst.h | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff

[Mesa-dev] [PATCH 19/21] intel/disasm: Properly disassemble split sends

--- src/intel/compiler/brw_disasm.c | 160 1 file changed, 141 insertions(+), 19 deletions(-) diff --git a/src/intel/compiler/brw_disasm.c b/src/intel/compiler/brw_disasm.c index 0fa33d5df26..b6be5963472 100644 --- a/src/intel/compiler/brw_disasm.c +++

[Mesa-dev] [PATCH 18/21] intel/eu: Add support for the SENDS[C] messages

--- src/intel/compiler/brw_eu.h | 11 ++ src/intel/compiler/brw_eu_emit.c | 144 ++- src/intel/compiler/brw_eu_validate.c | 65 +++- src/intel/compiler/brw_inst.h| 57 --- 4 files changed, 258 insertions(+), 19 deletions(-) diff

[Mesa-dev] [PATCH 20/21] intel/fs: Support SENDS in SHADER_OPCODE_SEND

--- src/intel/compiler/brw_fs.cpp | 50 + src/intel/compiler/brw_fs.h | 1 + src/intel/compiler/brw_fs_generator.cpp | 23 3 files changed, 66 insertions(+), 8 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp

[Mesa-dev] [PATCH 07/21] intel/fs: Use the generic SEND opcode for surface messages

--- src/intel/compiler/brw_eu.h | 27 --- src/intel/compiler/brw_eu_emit.c | 72 --- src/intel/compiler/brw_fs.cpp | 181 +- src/intel/compiler/brw_fs_generator.cpp | 62 -- .../compiler/brw_schedule_instructions.cpp

[Mesa-dev] [PATCH 09/21] intel/fs: Use a logical opcode for IMAGE_SIZE

--- src/intel/compiler/brw_eu_defines.h | 1 + src/intel/compiler/brw_fs.cpp | 10 ++ src/intel/compiler/brw_fs_nir.cpp | 14 -- src/intel/compiler/brw_shader.cpp | 2 ++ 4 files changed, 21 insertions(+), 6 deletions(-) diff --git

[Mesa-dev] [PATCH 11/21] intel/fs: Use SHADER_OPCODE_SEND for varying UBO pulls on gen7+

--- src/intel/compiler/brw_eu_defines.h | 1 - src/intel/compiler/brw_fs.cpp | 31 ++-- src/intel/compiler/brw_fs.h | 4 - src/intel/compiler/brw_fs_cse.cpp | 1 - src/intel/compiler/brw_fs_generator.cpp | 73 ---

[Mesa-dev] [PATCH 05/21] intel/eu: Rework surface descriptor helpers

This commit pulls the surface descriptor helpers out into brw_eu.h and makes them no longer depend on the codegen infrastructure. This should allow us to use them directly from the IR code instead of the generator. This change is unfortunately less mechanical than perhaps one would like but it

[Mesa-dev] [PATCH 10/21] intel/fs: Use SHADER_OPCODE_SEND for texturing on gen7+

--- src/intel/compiler/brw_fs.cpp | 138 ++- src/intel/compiler/brw_fs.h | 2 +- src/intel/compiler/brw_fs_generator.cpp | 162 +++--- .../compiler/brw_schedule_instructions.cpp| 17 ++ 4 files changed, 177 insertions(+), 142

[Mesa-dev] [PATCH 08/21] intel/fs: Mark texture surfaces used in brw_fs_nir

Previously, we were marking constant surface used in the generator and non-constant ones in brw_fs_nir. We should pick one and go with it. --- src/intel/compiler/brw_fs_generator.cpp | 2 -- src/intel/compiler/brw_fs_nir.cpp | 16 2 files changed, 8 insertions(+), 10

[Mesa-dev] [PATCH 15/21] intel/disasm: Rework SEND decoding to use descriptors

Instead of fetching the information out of the instruction directly, fetch the descriptor and then pluck the information of of the descriptor. The current scheme works ok for SEND but with SENDS, it all falls to pieces because the descriptor is completely shuffled around. This commit doesn't

[Mesa-dev] [PATCH 14/21] intel/eu: Add more message descriptor helpers

We want to be able to extract data from descriptors as well as unify a bit of the descriptor construction. --- src/intel/compiler/brw_eu.h | 236 1 file changed, 212 insertions(+), 24 deletions(-) diff --git a/src/intel/compiler/brw_eu.h

[Mesa-dev] [PATCH 13/21] intel/eu/validate: SEND restrictions also apply to SENDC

--- src/intel/compiler/brw_eu_validate.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_validate.c b/src/intel/compiler/brw_eu_validate.c index a25010b225c..ef372e9e32c 100644 --- a/src/intel/compiler/brw_eu_validate.c +++

[Mesa-dev] [PATCH 06/21] intel/fs: Add a generic SEND opcode

--- src/intel/compiler/brw_eu_defines.h | 7 src/intel/compiler/brw_fs.cpp | 13 +++ src/intel/compiler/brw_fs.h | 6 src/intel/compiler/brw_fs_cse.cpp | 5 +++ src/intel/compiler/brw_fs_generator.cpp | 35

[Mesa-dev] [PATCH 12/21] intel/eu: Use GET_BITS in brw_inst_set_send_ex_desc

It's a bit more readable --- src/intel/compiler/brw_inst.h | 10 +- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_inst.h b/src/intel/compiler/brw_inst.h index ce89bbba72f..753f09e70cf 100644 --- a/src/intel/compiler/brw_inst.h +++

[Mesa-dev] [PATCH 03/21] intel/fs: Take an explicit exec size in brw_surface_payload_size()

Instead of magically falling back to SIMD8 for atomics and typed messages on Ivy Bridge, explicitly figure out the exec size and pass that into brw_surface_payload_size. --- src/intel/compiler/brw_eu_emit.c | 59 +--- 1 file changed, 39 insertions(+), 20 deletions(-)

[Mesa-dev] [PATCH 04/21] intel/eu: Add has_simd4x2 bools to surface_write functions

--- src/intel/compiler/brw_eu_emit.c | 14 -- 1 file changed, 8 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index d22c5743038..e8235ce05f7 100644 --- a/src/intel/compiler/brw_eu_emit.c +++

[Mesa-dev] [PATCH 00/21] intel/compiler: Add support for SENDS[C]

This series is partly a re-send of my SHADER_OPCODE_SEND series and partially a new series to enable SENDS support on gen9 and above. The first 11 patches introduce a new SHADER_OPCODE_SEND which is a generic send instruction and lower several of our logical opcodes to it. Not everything is

[Mesa-dev] [PATCH 01/21] intel/defines: Explicitly cast to uint32_t in SET_FIELD and SET_BITS

If you pass a bool in as the value to set, the C standard says that it gets converted to an int prior to shifting. If you try to set a bool to bit 31, this lands you in undefined behavior. It's better just to add the explicit cast and let the compiler delete it for us. ---

[Mesa-dev] [PATCH 02/21] intel/fs: Handle IMAGE_SIZE in size_read() and is_send_from_grf()

Like all the other sends, it's just mlen * REG_SIZE. Fixes: 3cbc02e4693 "intel: Use TXS for image_size when we have..." --- src/intel/compiler/brw_fs.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

Anuj Phogat writes: > On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen > wrote: >> >> Hi, >> >> On 16.11.2018 10.33, Francisco Jerez wrote: >> > Kenneth Graunke writes: >> [...] >> >> Perhaps we'll get both configs working, and then will want to be able >> >> to select between them. I question

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

On Fri, Nov 16, 2018 at 6:21 AM Eero Tamminen wrote: > > Hi, > > On 16.11.2018 10.33, Francisco Jerez wrote: > > Kenneth Graunke writes: > [...] > >> Perhaps we'll get both configs working, and then will want to be able > >> to select between them. I question whether the additional URB is truly

[Mesa-dev] [Bug 108734] Regression: [bisected] dEQP-GLES31.functional.tessellation.invariance.* start failing on r600

https://bugs.freedesktop.org/show_bug.cgi?id=108734 mirh changed: What|Removed |Added CC||m...@protonmail.ch -- You are receiving this

Re: [Mesa-dev] [PATCH 5/5] loader: Factor out the common driver opening logic from each loader.

Eric Engestrom writes: > On Thursday, 2018-11-15 15:05:27 -0800, Eric Anholt wrote: >> diff --git a/src/gbm/backends/dri/gbm_dri.c b/src/gbm/backends/dri/gbm_dri.c >> index f32c0cd9885f..8f035b7c7d84 100644 >> --- a/src/gbm/backends/dri/gbm_dri.c >> +++ b/src/gbm/backends/dri/gbm_dri.c >> @@

Re: [Mesa-dev] [PATCH 2/5] glx: Move DRI extensions pointer loading to driOpenDriver().

Emil Velikov writes: > On Thu, 15 Nov 2018 at 23:05, Eric Anholt wrote: > >> --- a/src/glx/dri_glx.c >> +++ b/src/glx/dri_glx.c >> @@ -199,15 +199,9 @@ clear_driver_config_cache() >> static char * >> get_driver_config(const char *driverName) >> { >> - void *handle =

Re: [Mesa-dev] [PATCH] radv: Use structured intrinsics instead of indexing workaround for GFX9.

On Fri, Nov 16, 2018 at 9:34 AM Samuel Pitoiset wrote: > > > > On 11/12/18 10:51 PM, Bas Nieuwenhuizen wrote: > > These force the index to be used in the instruction so we don't need the > > workaround. > > > > Totals: > > SGPRS: 1321642 -> 1321802 (0.01 %) > > VGPRS: 943664 -> 943788 (0.01 %) >

Re: [Mesa-dev] [PATCH] meson: strip rpath when installing megadrivers

I should test this on MacOS... I will do that before pushing. Quoting Dylan Baker (2018-11-16 10:28:36) > This is the script that meson uses to install megadrivers. Meson always > sets rpath for in tree dependencies at build time, and normally rpaths > are stripped at install time. The install

Re: [Mesa-dev] [PATCH] meson: strip rpath when installing megadrivers

Quoting Eric Engestrom (2018-11-16 11:46:02) > > > On November 16, 2018 6:29:55 PM UTC, Dylan Baker wrote: > > This is the script that meson uses to install megadrivers. Meson > > always > > sets rpath for in tree dependencies at build time, and normally rpaths > > are stripped at install time.

Re: [Mesa-dev] [PATCH] meson: strip rpath when installing megadrivers

On November 16, 2018 6:29:55 PM UTC, Dylan Baker wrote: > This is the script that meson uses to install megadrivers. Meson > always > sets rpath for in tree dependencies at build time, and normally rpaths > are stripped at install time. The install megadrivers script breaks > this > by

Re: [Mesa-dev] [PATCH] radeonsi: fix an out-of-bounds read reported by ASAN

Reviewed-by: Marek Olšák On Fri, Nov 16, 2018, 12:33 PM Nicolai Hähnle From: Nicolai Hähnle > > We read 4 values out of sample_locs_8x, so make sure the array is > big enough. > > Fixes: ac76aeef20 ("radeonsi: switch back to standard DX sample positions") > --- >

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

On Tue, Nov 13, 2018 at 6:41 PM Roland Scheidegger wrote: > > Am 14.11.18 um 03:21 schrieb Matt Turner: > > On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger > > wrote: > >> > >> Am 13.11.18 um 23:49 schrieb Dylan Baker: > >>> Quoting Roland Scheidegger (2018-11-13 14:13:00) > Am 13.11.18

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

On Fri, Nov 16, 2018 at 10:34 AM Dylan Baker wrote: > > Quoting Roland Scheidegger (2018-11-13 18:41:00) > > Am 14.11.18 um 03:21 schrieb Matt Turner: > > > On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger > > > wrote: > > >> > > >> Am 13.11.18 um 23:49 schrieb Dylan Baker: > > >>> Quoting

Re: [Mesa-dev] [PATCH 16/28] Replace IROUND_POS with _mesa_roundevenf

Quoting Roland Scheidegger (2018-11-13 18:41:00) > Am 14.11.18 um 03:21 schrieb Matt Turner: > > On Tue, Nov 13, 2018 at 6:03 PM Roland Scheidegger > > wrote: > >> > >> Am 13.11.18 um 23:49 schrieb Dylan Baker: > >>> Quoting Roland Scheidegger (2018-11-13 14:13:00) > Am 13.11.18 um 18:00

Re: [Mesa-dev] [PATCH 2/2] travis: adding missing x11-xcb for meson+vulkan

For this patch, Reviewed-by: Dylan Baker For the first one Xenial was never really supported by travis AFAICT, but cosmic cuttlefish does seem to be supported, so if we need to move from trusty it should be to cosmic. Dylan Quoting Emil Velikov (2018-09-07 06:58:56) > From: Emil Velikov > >

[Mesa-dev] [PATCH] meson: strip rpath when installing megadrivers

This is the script that meson uses to install megadrivers. Meson always sets rpath for in tree dependencies at build time, and normally rpaths are stripped at install time. The install megadrivers script breaks this by bypassing meson's normal install machinery. To fix this I've imported the

[Mesa-dev] [PATCH 2/2] glsl: free or reuse memory allocated for TF varying

From: Gert Wollny When a shader program is de-serialized the gl_shader_program passed in may actually still hold memory allocations for the transform feedback varyings. If that is the case, free the varying names and reallocate the new storage for the names array. This fixes a memory leak:

[Mesa-dev] [PATCH 1/2] r600: Also destroy the GS copy shader when a r600_pipe_shader is destroyed

From: Gert Wollny Fixes memory leak: 104,104 bytes in 13 blocks are definitely lost in loss record 591 of 591 at 0x4C2FE4D: calloc (vg_replace_malloc.c:711) by 0x7E155DE: generate_gs_copy_shader (r600_shader.c:2489) by 0x7E1BD1D: r600_shader_from_tgsi (r600_shader.c:4268) by 0x7E0E669:

Re: [Mesa-dev] [PATCH mesa] loader: deduplicate logger function declaration

Reviewed-by: Emil Velikov -Emil ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] egl: Print the actual message to the console from _eglError().

On Fri, 16 Nov 2018 at 05:15, Eric Anholt wrote: > > Previously we would print errors on the console like: > >libEGL debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED) in eglInitialize > > When we had everything we needed for: > >libEGL debug: EGL user error 0x3001 (EGL_NOT_INITIALIZED)

Re: [Mesa-dev] [PATCH 1/2] travis: drop unneeded x11proto-xf86vidmode-dev

This all seems reasonable, although I'll admit I didn't read too closely, for the series: Acked-by: Dylan Baker Quoting Emil Velikov (2018-11-16 05:59:00) > From: Emil Velikov > > The only place where the package is needed is for building the DRI > based libGL library. > > Cc:

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 Dylan Baker changed: What|Removed |Added Assignee|mesa-dev@lists.freedesktop. |baker.dyla...@gmail.com

Re: [Mesa-dev] [PATCH mesa 1/2] egl: add missing includes

On Fri, 16 Nov 2018 at 10:07, Eric Engestrom wrote: > > Signed-off-by: Eric Engestrom > --- > src/egl/drivers/dri2/egl_dri2.c | 1 + > src/egl/main/eglapi.c | 2 ++ > src/egl/main/eglapi.h | 1 + > src/egl/main/eglglobals.c | 2 ++ > src/egl/main/eglsurface.c | 2

[Mesa-dev] [PATCH] radeonsi: fix an out-of-bounds read reported by ASAN

From: Nicolai Hähnle We read 4 values out of sample_locs_8x, so make sure the array is big enough. Fixes: ac76aeef20 ("radeonsi: switch back to standard DX sample positions") --- src/gallium/drivers/radeonsi/si_state_msaa.c | 4 1 file changed, 4 insertions(+) diff --git

Re: [Mesa-dev] [PATCH 2/5] glx: Move DRI extensions pointer loading to driOpenDriver().

On Thu, 15 Nov 2018 at 23:05, Eric Anholt wrote: > --- a/src/glx/dri_glx.c > +++ b/src/glx/dri_glx.c > @@ -199,15 +199,9 @@ clear_driver_config_cache() > static char * > get_driver_config(const char *driverName) > { > - void *handle = driOpenDriver(driverName); > - const __DRIextension

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 Eric Engestrom changed: What|Removed |Added Blocks|108530 | Referenced Bugs:

[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker

https://bugs.freedesktop.org/show_bug.cgi?id=108530 Eric Engestrom changed: What|Removed |Added Depends on|108766 | Referenced Bugs:

Re: [Mesa-dev] [PATCH v1] virgl: Clean up fences commit

On Fri, 16 Nov 2018 at 13:55, Robert Foss wrote: > > Remove a dead variable, an unneeded int->bool conversion > and some whitespace changes. > > Signed-off-by: Robert Foss > --- > > Sorry about the spam, and this not being included in > v5 which was upstreamed. But nevertheless it should be

Re: [Mesa-dev] [PATCH 1/2] travis: drop unneeded x11proto-xf86vidmode-dev

On Fri, 16 Nov 2018 at 15:23, Eric Engestrom wrote: > > On Friday, 2018-11-16 13:59:00 +, Emil Velikov wrote: > > From: Emil Velikov > > > > The only place where the package is needed is for building the DRI > > based libGL library. > > > > Cc: mesa-sta...@lists.freedesktop.org > >

Re: [Mesa-dev] [PATCH] r600: clean up the GS ring buffers when the context is destroyed

I forgot: Fixes: 1371d65a7fbd695d3516861fe733685569d890d0 r600g: initial support for geometry shaders on evergreen (v2) Am Freitag, den 16.11.2018, 12:48 +0100 schrieb Gert Wollny: > From: Gert Wollny > > This fixes two memory leaks reported by ASAN: > > Direct leak of 248 byte(s) in 1

[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker

https://bugs.freedesktop.org/show_bug.cgi?id=108530 Eric Engestrom changed: What|Removed |Added Depends on||108766 Referenced Bugs:

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 Eric Engestrom changed: What|Removed |Added Blocks||108530 --- Comment #3 from Eric

[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker

https://bugs.freedesktop.org/show_bug.cgi?id=108530 Emil Velikov changed: What|Removed |Added Depends on|108766 | Referenced Bugs:

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 Emil Velikov changed: What|Removed |Added Blocks|108530 | --- Comment #2 from Emil Velikov ---

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 --- Comment #1 from Eric Engestrom --- Issue confirmed, and tracked down to the fact meson passes the build-time file to meson.add_install_script() instead of the install-time one, which has gone through the stripping process and everything.

[Mesa-dev] [ANNOUNCE] mesa 18.3.0-rc3

The third release candidate for Mesa 18.3.0 is now available. Andre Heider (1): st/nine: fix stack corruption due to ABI mismatch Connor Abbott (1): Revert "radv: disable VK_SUBGROUP_FEATURE_VOTE_BIT" Danylo Piliaiev (1): i965: Fix calculation of layers array length for

Re: [Mesa-dev] [PATCH] intel, nir: Move gl_LocalInvocationID lowering to nir_lower_system_values

Looks good to me :) Reviewed-by: Plamena Manolova On Fri, Nov 16, 2018 at 7:02 AM Jason Ekstrand wrote: > It's not at all intel-specific; the formula is dictated by OpenGL and > Vulkan. The only intel-specific thing is that we need the lowering. As > a nice side-effect, the new version is

[Mesa-dev] [PATCH] intel/fs,vec4: Fix a compiler warning

../src/intel/compiler/brw_fs_nir.cpp:3534:46: warning: comparison of integer expressions of different signedness: ‘unsigned int’ and ‘int’ [-Wsign-compare] assert(nir_intrinsic_write_mask(instr) == ^~ (1 << instr->num_components)

Re: [Mesa-dev] [PATCH 1/2] travis: drop unneeded x11proto-xf86vidmode-dev

On Friday, 2018-11-16 13:59:00 +, Emil Velikov wrote: > From: Emil Velikov > > The only place where the package is needed is for building the DRI > based libGL library. > > Cc: mesa-sta...@lists.freedesktop.org > Signed-off-by: Emil Velikov I really can't tell what env you're removing

[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker

https://bugs.freedesktop.org/show_bug.cgi?id=108530 Bug 108530 depends on bug 108330, which changed state. Bug 108330 Summary: WarThunder game performance killed after Ryzen optimisations https://bugs.freedesktop.org/show_bug.cgi?id=108330 What|Removed |Added

Re: [Mesa-dev] [PATCH 2/2] glx: make xf86vidmode mandatory for direct rendering

On Friday, 2018-11-16 13:59:01 +, Emil Velikov wrote: > From: Emil Velikov > > Currently we detect the module and if missing, the glXGetMsc* API is > effectively a stub, always returning false. > > This is what effectively has been happening with our meson build :-( Oops... you're right:

Re: [Mesa-dev] [PATCH] radv: perform subpass transitions for resolve attachments

On 11/16/18 3:45 PM, Rhys Perry wrote: Fixes Sascha Willems's multisampling example on my Vega 64. What make you think that this demo is broken? dEQP-VK.renderpass.multisample_resolve.* didn't exhibit issues because of it's images being 32x32 which disabled DCC/CMASK and made these

Re: [Mesa-dev] [PATCH] radv: perform subpass transitions for resolve attachments

Actually I just realized that something like https://gitlab.freedesktop.org/mesa/mesa/blob/fe3f13cc5a8/src/amd/vulkan/radv_meta_resolve.c#L678-681 would probably be better. On Fri, 16 Nov 2018 at 14:45, Rhys Perry wrote: > > Fixes Sascha Willems's multisampling example on my Vega 64. > >

[Mesa-dev] [Bug 108530] [Tracker] Mesa 18.3 Release Tracker

https://bugs.freedesktop.org/show_bug.cgi?id=108530 Emil Velikov changed: What|Removed |Added Depends on||108766 Referenced Bugs:

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 Emil Velikov changed: What|Removed |Added Blocks||108530 CC|

[Mesa-dev] [PATCH] radv: perform subpass transitions for resolve attachments

Fixes Sascha Willems's multisampling example on my Vega 64. dEQP-VK.renderpass.multisample_resolve.* didn't exhibit issues because of it's images being 32x32 which disabled DCC/CMASK and made these transitions unnecessary. Signed-of-by: Rhys Perry CC: --- src/amd/vulkan/radv_cmd_buffer.c | 6

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

Hi, On 16.11.2018 10.33, Francisco Jerez wrote: Kenneth Graunke writes: [...] Perhaps we'll get both configs working, and then will want to be able to select between them. I question whether the additional URB is truly that valuable - how large are the actual gains? - considering that we

[Mesa-dev] [Bug 108766] Mesa built with meson has RPATH entries

https://bugs.freedesktop.org/show_bug.cgi?id=108766 Bug ID: 108766 Summary: Mesa built with meson has RPATH entries Product: Mesa Version: unspecified Hardware: All OS: All Status: NEW Severity: normal

[Mesa-dev] [PATCH 1/2] travis: drop unneeded x11proto-xf86vidmode-dev

From: Emil Velikov The only place where the package is needed is for building the DRI based libGL library. Cc: mesa-sta...@lists.freedesktop.org Signed-off-by: Emil Velikov --- .travis.yml | 10 -- 1 file changed, 10 deletions(-) diff --git a/.travis.yml b/.travis.yml index

[Mesa-dev] [PATCH 2/2] glx: make xf86vidmode mandatory for direct rendering

From: Emil Velikov Currently we detect the module and if missing, the glXGetMsc* API is effectively a stub, always returning false. This is what effectively has been happening with our meson build :-( Thus users have no chance of using it - they cannot even distinguish if the failure is due to

[Mesa-dev] [PATCH v1] virgl: Clean up fences commit

Remove a dead variable, an unneeded int->bool conversion and some whitespace changes. Signed-off-by: Robert Foss --- Sorry about the spam, and this not being included in v5 which was upstreamed. But nevertheless it should be fixed, and here's the commit.

Re: [Mesa-dev] [PATCH v5] virgl: native fence fd support

Hey Emil, I just pushed v5 upstream. Let me spin a cleanup patch and send that to the ML. Rob. On 2018-11-16 14:03, Emil Velikov wrote: Hi Rob, I've spotted a couple of nitpicks, but I don't feel too strongly either way. On Thu, 15 Nov 2018 at 13:28, Robert Foss wrote: case

Re: [Mesa-dev] [PATCH v5] virgl: native fence fd support

Hi Rob, I've spotted a couple of nitpicks, but I don't feel too strongly either way. On Thu, 15 Nov 2018 at 13:28, Robert Foss wrote: > case PIPE_CAP_VIDEO_MEMORY: >return 0; > case PIPE_CAP_NATIVE_FENCE_FD: > - return 0; > + return !!vscreen->vws->supports_fences;

[Mesa-dev] [PATCH mesa] loader: deduplicate logger function declaration

Signed-off-by: Eric Engestrom --- src/loader/loader.c | 4 ++-- src/loader/loader.h | 3 ++- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/src/loader/loader.c b/src/loader/loader.c index 461f96aa6a448272dedd..018989c201e047159b9a 100644 --- a/src/loader/loader.c +++

[Mesa-dev] [PATCH 1/2] radv: tidy up radv_set_dcc_need_cmask_elim_pred()

This is just a small cleanup. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_cmd_buffer.c | 11 +-- src/amd/vulkan/radv_image.c | 2 +- src/amd/vulkan/radv_meta_clear.c | 4 ++-- src/amd/vulkan/radv_meta_fast_clear.c | 4 ++-- src/amd/vulkan/radv_private.h

[Mesa-dev] [PATCH 2/2] radv: always clear the FCE predicate after DCC/FMASK/CMASK decompressions

DCC and FMASK also imply a fast-clear eliminate, so it should be safe to reset the predicate unconditionally. We still only skip FMASK or CMASK decompressions for now. Signed-off-by: Samuel Pitoiset --- src/amd/vulkan/radv_meta_fast_clear.c | 13 - 1 file changed, 8 insertions(+), 5

Re: [Mesa-dev] [PATCH 4/4] i965: Add support for and expose EXT_texture_sRGB_R8

On Thursday, 2018-11-15 19:01:24 +0100, Gert Wollny wrote: > Emulate MESA_FORMAT_R_SRGB8 by using L8_UNORM_SRGB. This is possible > because component swizzling is handled based on the mesa format and, > hence, the a r001 swizzling can be used to correct the components. > > Enables and makes pass

[Mesa-dev] [PATCH] r600: clean up the GS ring buffers when the context is destroyed

From: Gert Wollny This fixes two memory leaks reported by ASAN: Direct leak of 248 byte(s) in 1 object(s) allocated from: in malloc (/usr/lib64/gcc/x86_64-pc-linux-gnu/7.3.0/libasan.so+0xdb880) in r600_alloc_buffer_struct ../../samba/mesa/src/gallium/drivers/r600/r600_buffer_common.c:578

Re: [Mesa-dev] [PATCH 5/5] loader: Factor out the common driver opening logic from each loader.

On Thursday, 2018-11-15 15:05:27 -0800, Eric Anholt wrote: > I copied the code from egl_dri2.c, but the functionality was equivalent > between all the loaders other than their particular environment variables. > --- > src/egl/Makefile.am | 3 +- > src/egl/drivers/dri2/egl_dri2.c | 75

Re: [Mesa-dev] [PATCH 5/5] intel/aub_viewer: Print blend states properly

Thanks Toni, pushing the whole lot :) On 16/11/2018 11:35, Toni Lönnberg wrote: Reviewed-by: Toni Lönnberg On Fri, Nov 09, 2018 at 04:49:13PM +, Lionel Landwerlin wrote: Identical fix to : commit 70de31d0c106f58d6b7e6d5b79b8d90c1c112a3b Author: Jason Ekstrand Date: Fri Aug 24

Re: [Mesa-dev] [PATCH 5/5] intel/aub_viewer: Print blend states properly

Reviewed-by: Toni Lönnberg On Fri, Nov 09, 2018 at 04:49:13PM +, Lionel Landwerlin wrote: > Identical fix to : > > commit 70de31d0c106f58d6b7e6d5b79b8d90c1c112a3b > Author: Jason Ekstrand > Date: Fri Aug 24 16:05:08 2018 -0500 > > intel/batch_decoder: Print blend states properly >

Re: [Mesa-dev] [PATCH 4/5] intel/aub_viewer: fix dynamic state printing

Reviewed-by: Toni Lönnberg On Fri, Nov 09, 2018 at 04:49:12PM +, Lionel Landwerlin wrote: > Identical fix to : > > commit cbd4bc1346f7397242e157bb66099b950a8c5643 > Author: Jason Ekstrand > Date: Fri Aug 24 16:04:03 2018 -0500 > > intel/batch_decoder: Fix dynamic state printing > >

Re: [Mesa-dev] [PATCH 2/2] travis: adding missing x11-xcb for meson+vulkan

On Fri, 7 Sep 2018 at 15:03, Emil Velikov wrote: > > From: Emil Velikov > > Required by the x11 WSI > > Fixes: df82012b2cb ("travis: add meson build for vulkan drivers.") > Cc: Dylan Baker > Signed-off-by: Emil Velikov > --- > Dylan comparing the list vs the autotools build the meson one is

Re: [Mesa-dev] [PATCH 2/5] glx: Move DRI extensions pointer loading to driOpenDriver().

On Thursday, 2018-11-15 15:05:24 -0800, Eric Anholt wrote: > The only thing you do with a dri driver handle is get the extensions > pointer, so just fold it in to simplify the callers. > --- > src/glx/dri2_glx.c | 8 +--- > src/glx/dri3_glx.c | 8 +--- > src/glx/dri_common.c | 20

Re: [Mesa-dev] [PATCH v7 0/5] Mesa integration for DRM variable refresh rate API

On 2018-10-23 5:38 p.m., Nicholas Kazlauskas wrote: > These patches are part of a proposed new interface for supporting variable > refresh rate via DRM properties. > > It adds a new option for supporting adaptive sync to drirc along with the > implementation of notifying the window manager/DDX

[Mesa-dev] [PATCH mesa 2/2] egl: remove unused include

Signed-off-by: Eric Engestrom --- src/egl/main/egldefines.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/src/egl/main/egldefines.h b/src/egl/main/egldefines.h index d0502f33091a9ecb06bd..c925e0ca55338f73dbec 100644 --- a/src/egl/main/egldefines.h +++ b/src/egl/main/egldefines.h @@ -34,8

[Mesa-dev] [PATCH mesa 1/2] egl: add missing includes

Signed-off-by: Eric Engestrom --- src/egl/drivers/dri2/egl_dri2.c | 1 + src/egl/main/eglapi.c | 2 ++ src/egl/main/eglapi.h | 1 + src/egl/main/eglglobals.c | 2 ++ src/egl/main/eglsurface.c | 2 ++ 5 files changed, 8 insertions(+) diff --git

Re: [Mesa-dev] [Mesa-stable] [PATCH] vulkan/wsi/wayland: Respect non-blocking AcquireNextImage

Hi Emil, On Thu, 8 Nov 2018 at 15:26, Emil Velikov wrote: > On Tue, 30 Oct 2018 at 12:57, Daniel Stone wrote: > > If the client has requested that AcquireNextImage not block at all, with > > a timeout of 0, then don't make any non-blocking calls. > > > > This will still potentially block

Re: [Mesa-dev] [PATCH] vulkan: Add VK_GOOGLE_display_timing extension (x11+display, anv+radv) [v6]

On 2018-11-15 7:06 p.m., Keith Packard wrote: > This adds support for the VK_GOOGLE_display timing extension, which > provides two things: > > 1) Detailed information about when frames are displayed, including > slack time between GPU execution and display frame. > > 2) Absolute time

Re: [Mesa-dev] [PATCH v4] i965: Fix calculation of layers array length for isl_view

Thanks! On 11/16/18 7:09 AM, Jason Ekstrand wrote: Pushed. On Thu, Nov 15, 2018 at 8:15 PM Jason Ekstrand wrote: Thanks. I'm going to push it once it gets done running through CI. On Thu, Nov 15, 2018 at 4:03 AM Danylo Piliaiev wrote: Handle all cases in calculation of layers count for

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

Kenneth Graunke writes: > On Thursday, November 15, 2018 11:16:09 PM PST Francisco Jerez wrote: >> Kenneth Graunke writes: >> >> > On Thursday, November 15, 2018 5:51:18 PM PST Francisco Jerez wrote: >> >> Anuj Phogat writes: >> >> >> >> > Use L3 configuration table specified in h/w

Re: [Mesa-dev] [PATCH] radv: Use structured intrinsics instead of indexing workaround for GFX9.

On 11/12/18 10:51 PM, Bas Nieuwenhuizen wrote: These force the index to be used in the instruction so we don't need the workaround. Totals: SGPRS: 1321642 -> 1321802 (0.01 %) VGPRS: 943664 -> 943788 (0.01 %) Spilled SGPRs: 28468 -> 28480 (0.04 %) Spilled VGPRs: 88 -> 89 (1.14 %) Private

Re: [Mesa-dev] [PATCH 1/5] i965/icl: Fix L3 configurations

On Thursday, November 15, 2018 11:16:09 PM PST Francisco Jerez wrote: > Kenneth Graunke writes: > > > On Thursday, November 15, 2018 5:51:18 PM PST Francisco Jerez wrote: > >> Anuj Phogat writes: > >> > >> > Use L3 configuration table specified in h/w specification. > >> > > >> >