[Mesa-dev] [PATCH v2 50/53] intel/compiler: remove MAD/LRP algebraic optimizations from the backend

NIR already has these so they are redundant. A run of shader-db confirms that the only cases where these backend optimizations are activated are some Tomb Raider shaders where the affected variables are qualified as "precise", which is why NIR won't apply them and why the backend shouldn't either

[Mesa-dev] [PATCH v2 27/53] intel/compiler: add instruction setters for Src1Type and Src2Type.

The original SrcType is a 3-bit field that takes a subset of the types supported for the hardware for 3-source instructions. Since gen8, when the half-float type was added, 3-source floating point operations can use use mixed precision mode, where not all the operands have the same floating-point

[Mesa-dev] [PATCH v2 25/53] compiler/nir: add lowering for 16-bit ldexp

v2 (Topi): - Make bit-size handling order be 16-bit, 32-bit, 64-bit - Clamp lower exponent range at -28 instead of -30. Reviewed-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir_opt_algebraic.py | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff

[Mesa-dev] [PATCH v2 44/53] compiler/spirv: add support for Float16 and Int8 capabilities

v2: - Merge Float16 and Int8 capabilities into a single patch Reviewed-by: Jason Ekstrand (v1) --- src/compiler/shader_info.h| 2 ++ src/compiler/spirv/spirv_to_nir.c | 8 ++-- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/shader_info.h

[Mesa-dev] [PATCH v2 49/53] intel/compiler: fix cmod propagation for non 32-bit types

--- src/intel/compiler/brw_fs_cmod_propagation.cpp | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_cmod_propagation.cpp b/src/intel/compiler/brw_fs_cmod_propagation.cpp index 7bb5c9afbc9..dfef9d720a2 100644 ---

[Mesa-dev] [PATCH v2 42/53] intel/compiler: implement isign for int8

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 25 + 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 57bc8a01a91..2f3ad554147 100644 ---

[Mesa-dev] [PATCH v2 46/53] anv/device: expose shaderFloat16 and shaderInt8 in gen8+

v2: - Merge Float16 and Int8 into a single patch. - Merge extension enable. Reviewed-by: Jason Ekstrand (v1) --- src/intel/vulkan/anv_device.c | 9 + src/intel/vulkan/anv_extensions.py | 1 + 2 files changed, 10 insertions(+) diff --git a/src/intel/vulkan/anv_device.c

[Mesa-dev] [PATCH v2 51/53] intel/compiler: support half-float in the combine constants pass

--- .../compiler/brw_fs_combine_constants.cpp | 60 +++ 1 file changed, 49 insertions(+), 11 deletions(-) diff --git a/src/intel/compiler/brw_fs_combine_constants.cpp b/src/intel/compiler/brw_fs_combine_constants.cpp index e0c95d379b8..24307e365ab 100644 ---

[Mesa-dev] [PATCH v2 40/53] intel/compiler: handle conversions between int and half-float on atom

--- src/intel/compiler/brw_fs_nir.cpp | 15 +++ 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index a9fd98bab68..57bc8a01a91 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH v2 48/53] intel/compiler: add a brw_reg_type_is_integer helper

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_reg_type.h | 18 ++ 1 file changed, 18 insertions(+) diff --git a/src/intel/compiler/brw_reg_type.h b/src/intel/compiler/brw_reg_type.h index ffbec90d3fe..a3365b7e34c 100644 --- a/src/intel/compiler/brw_reg_type.h +++

[Mesa-dev] [PATCH v2 30/53] intel/compiler: allow half-float on 3-source instructions since gen8

Reviewed-by: Topi Pohjolainen --- src/intel/compiler/brw_eu_emit.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index 97e0dda5ef1..0f6498614e8 100644 --- a/src/intel/compiler/brw_eu_emit.c +++

[Mesa-dev] [PATCH v2 31/53] intel/compiler: set correct precision fields for 3-source float instructions

Source0 and Destination extract the floating-point precision automatically from the SrcType and DstType instruction fields respectively when they are set to types :F or :HF. For Source1 and Source2 operands, we use the new 1-bit fields Src1Type and Src2Type, where 0 means normal precision and 1

[Mesa-dev] [PATCH v2 53/53] intel/compiler: allow propagating HF immediates to MAD/LRP

Even if we don't do 3-src algebraic optimizations for MAD and LRP in the backend any more, the combine constants pass can still do a fine job putting grouping these constants into single registers for better register pressure. v2: - updated comment to reference register pressure benefits rather

[Mesa-dev] [PATCH v2 43/53] intel/eu: force stride of 2 on NULL register for Byte instructions

The hardware only allows a stride of 1 on a Byte destination for raw byte MOV instructions. This is required even when the destination is the NULL register. Rather than making sure that we emit a proper NULL:B destination every time we need one, just fix it at emission time. Reviewed-by: Jason

[Mesa-dev] [PATCH v2 29/53] intel/compiler: don't compact 3-src instructions with Src1Type or Src2Type bits

We are now using these bits, so don't assert that they are not set, just avoid compaction in that case. Reviewed-by: Topi Pohjolainen --- src/intel/compiler/brw_eu_compact.c | 5 - 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_eu_compact.c

[Mesa-dev] [PATCH v2 39/53] intel/compiler: add a helper to do conversions between integer and half-float

There are hardware restrictions to consider that seem to affect atom platforms only. --- src/intel/compiler/brw_fs_nir.cpp | 32 +++ 1 file changed, 32 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 45/53] anv/pipeline: support Float16 and Int8 capabilities in gen8+

v2: - Merge Float16 and Int8 in a single patch Reviewed-by: Jason Ekstrand (v1) --- src/intel/vulkan/anv_pipeline.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 6db9945e0d4..c303ba321c3 100644 ---

[Mesa-dev] [PATCH v2 36/53] intel/compiler: split is_partial_write() into two variants

This function is used in two different scenarios that for 32-bit instructions are the same, but for 16-bit instructions are not. One scenario is that in which we are working at a SIMD8 register level and we need to know if a register is fully defined or written. This is useful, for example, in

[Mesa-dev] [PATCH v2 52/53] intel/compiler: fix combine constants for Align16 with half-float prior to gen9

There is a hardware restriction where <0,1,0>:HF in Align16 doesn't replicate a single 16-bit channel, but instead it replicates a full 32-bit channel. --- .../compiler/brw_fs_combine_constants.cpp | 24 +-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH v2 37/53] intel/compiler: activate 16-bit bit-size lowerings also for 8-bit

Particularly, we need the same lowewrings we use for 16-bit integers. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_nir.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 0641b659979..2c265dd2394

[Mesa-dev] [PATCH v2 17/53] intel/compiler: lower some 16-bit float operations to 32-bit

The hardware doesn't support half-float for these. Reviewed-by: Topi Pohjolainen Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_nir.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index a1ab8290271..8801f7f77b0

[Mesa-dev] [PATCH v2 32/53] intel/compiler: don't propagate HF immediates to 3-src instructions

3-src instructions don't support immediates, but since 36bc5f06dd22, we allow them on MAD and LRP relying on the combine constants pass to fix it up later. However, that pass is specialized for 32-bit float immediates and can't handle HF constants at present, so this patch ensures that

[Mesa-dev] [PATCH v2 22/53] intel/compiler: lower 16-bit fmod

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index fe632c5badc..f885e79c3e6 100644 --- a/src/intel/compiler/brw_compiler.c +++

[Mesa-dev] [PATCH v2 47/53] intel/compiler: implement is_zero, is_one, is_negative_one for 8-bit/16-bit

There are no 8-bit immediates, so assert in that case. 16-bit immediates are replicated in each word of a 32-bit immediate, so we only need to check the lower 16-bits. v2: - Fix is_zero with half-float to consider -0 as well (Jason). - Fix is_negative_one for word type. ---

[Mesa-dev] [PATCH v2 21/53] compiler/nir: add lowering option for 16-bit fmod

Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index d99cc6b2d38..96a18d9c9bd 100644 --- a/src/compiler/nir/nir.h +++

[Mesa-dev] [PATCH v2 13/53] intel/compiler: add a helper to handle conversions to 64-bit in atom

--- src/intel/compiler/brw_fs_nir.cpp | 55 ++- 1 file changed, 33 insertions(+), 22 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 92ec85a27cc..15715651aa6 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH v2 04/53] compiler/spirv: implement 16-bit asin

v2: - use nir_fmul_imm and nir_fadd_imm helpers (Jason) --- src/compiler/spirv/vtn_glsl450.c | 23 ++- 1 file changed, 14 insertions(+), 9 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index b54aeb9b217..f411d17cfe4 100644 ---

[Mesa-dev] [PATCH v2 20/53] intel/compiler: allow extended math functions with HF operands

The PRM states that half-float operands are supported since gen9. Reviewed-by: Topi Pohjolainen --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index

[Mesa-dev] [PATCH v2 11/53] compiler/spirv: use 32-bit polynomial approximation for 16-bit asin()

The 16-bit polynomial execution doesn't meet Khronos precision requirements. Also, the half-float denorm range starts at 2^(-14) and with asin taking input values in the range [0, 1], polynomial approximations can lead to flushing relatively easy. An alternative is to use the atan2 formula to

[Mesa-dev] [PATCH v2 06/53] compiler/spirv: implement 16-bit atan

v2: - use nir_fadd_imm and nir_fmul_imm helpers (Jason) - rebased on top of new sized boolean opcodes - use nir_b2f helper --- src/compiler/spirv/vtn_glsl450.c | 23 +++ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c

[Mesa-dev] [PATCH v2 08/53] compiler/spirv: implement 16-bit exp and log

v2 - use nir_fmul_imm helper (Jason) Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_glsl450.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index b8b534397a2..ec91d9308c5 100644 ---

[Mesa-dev] [PATCH v2 23/53] compiler/nir: add lowering for 16-bit flrp

Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 96a18d9c9bd..2f9df3dfe83 100644 --- a/src/compiler/nir/nir.h +++

[Mesa-dev] [PATCH v2 28/53] intel/compiler: add new half-float register type for 3-src instructions

This is available since gen8. --- src/intel/compiler/brw_reg_type.c | 35 +++ 1 file changed, 31 insertions(+), 4 deletions(-) diff --git a/src/intel/compiler/brw_reg_type.c b/src/intel/compiler/brw_reg_type.c index 60240ba1513..72295a2bd75 100644 ---

[Mesa-dev] [PATCH v2 33/53] intel/compiler: fix ddx and ddy for 16-bit float

We were assuming 32-bit elements. Also, In SIMD8 we pack 2 vector components in a single SIMD register, so for example, component Y of a 16-bit vec2 starts is at byte offset 16B. This means that when we compute the offset of the elements to be differentiated we should not stomp whatever base

[Mesa-dev] [PATCH v2 16/53] intel/compiler: handle conversions to half-float

There are some hardware restrictions that brw_nir_lower_conversions should have taken care of before we get here. --- src/intel/compiler/brw_fs_nir.cpp | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH v2 41/53] intel/compiler: assert that lower conversions produces valid strides

The hardware only has two bits to specify the horizontal stride, so the maximum horizontal stride we can use is 4. The pass calculates strides based on the sizes of the types involved, and for conversions between 64-bit and 8-bit types that can lead to strides of 8. The compiler should make sure

[Mesa-dev] [PATCH v2 38/53] intel/compiler: handle 64-bit to 8-bit conversions

These are not directly supported in hardware and brw_nir_lower_conversions should have taken care of that before we get here. --- src/intel/compiler/brw_fs_nir.cpp | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp

[Mesa-dev] [PATCH v2 14/53] intel/compiler: split float to 64-bit opcodes from int to 64-bit

Going forward having these split is a bit more convenient since these two groups have different restrictions. --- src/intel/compiler/brw_fs_nir.cpp | 8 1 file changed, 8 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 35/53] intel/compiler: workaround for SIMD8 half-float MAD in gen < 9

Broadwell hardware has a bug that manifests in SIMD8 executions of 16-bit MAD instructions when any of the sources is a Y or W component. We pack these components in the same SIMD register as components X and Z respectively, but starting at offset 16B (so they live in the second half of the

[Mesa-dev] [PATCH v2 26/53] intel/compiler: Extended Math is limited to SIMD8 on half-float

From the Skylake PRM, Extended Math Function: "The execution size must be no more than 8 when half-floats are used in source or destination operand." Earlier generations do not support Extended Math with half-float. v2 - Rewrite the code to make it more readable (Jason). Reviewed-by:

[Mesa-dev] [PATCH v2 10/53] compiler/spirv: implement 16-bit frexp

Reviewed-by: Jason Ekstrand --- src/compiler/spirv/vtn_glsl450.c | 48 ++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index c8400d6c80f..2540331b6cc 100644 ---

[Mesa-dev] [PATCH v2 15/53] intel/compiler: handle b2i/b2f with other integer conversion opcodes

Since we handle booleans as integers this makes more sense. v2: - rebased to incorporate new boolean conversion opcodes Reviewed-by: Topi Pohjolainen (v1) Reviewed-by: Jason Ekstrand (v1) --- src/intel/compiler/brw_fs_nir.cpp | 20 ++-- 1 file changed, 10 insertions(+), 10

[Mesa-dev] [PATCH v2 18/53] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

Extended math desn't support half-float on these generations. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_nir.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index 8801f7f77b0..0641b659979

[Mesa-dev] [PATCH v2 07/53] compiler/spirv: implement 16-bit atan2

v2: - fix huge_val for 16-bit, it was mean't to be 2^14 not 10^14. v3: - rebase on top of new bool sized opcodes - use nir_b2f helper - use nir_fmul_imm helper --- src/compiler/spirv/vtn_glsl450.c | 18 +++--- 1 file changed, 11 insertions(+), 7 deletions(-) diff --git

[Mesa-dev] [PATCH v2 19/53] intel/compiler: implement 16-bit fsign

v2: - make 16-bit be its own separate case (Jason) Reviewed-by: Topi Pohjolainen (v1) --- src/intel/compiler/brw_fs_nir.cpp | 18 +- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 03/53] compiler/spirv: handle 16-bit float in radians() and degrees()

v2: - use nir_imm_fmul helper (Jason) Reviewed-by: Jason Ekstrand --- src/compiler/nir/nir_builtin_builder.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_builtin_builder.h b/src/compiler/nir/nir_builtin_builder.h index 0e5b9db462a..d1435b37fd4

[Mesa-dev] [PATCH v2 00/53] intel: VK_KHR_shader_float16_int8 implementation

This version rebases the series on top of a more recent master and addresses review feedback to v1. The main change is the rewrite of the type conversion patches to reduce the growing complexity of the backend following discussions with Jason. The main actions I took in the end are: 1) Moved the

[Mesa-dev] [PATCH v2 12/53] intel/compiler: add a NIR pass to lower conversions

Some conversions are not directly supported in hardware and need to be split in two conversion instructions going through an intermediary type. Doing this at the NIR level simplifies a bit the complexity in the backend. --- src/intel/Makefile.sources| 1 +

[Mesa-dev] [PATCH v2 09/53] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

v2: - use nir_fadd_imm and nir_fmul_imm helpers (Jason) --- src/compiler/spirv/vtn_glsl450.c | 44 +++- 1 file changed, 26 insertions(+), 18 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index ec91d9308c5..c8400d6c80f

[Mesa-dev] [PATCH v2 05/53] compiler/spirv: implement 16-bit acos

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index f411d17cfe4..6b471efda2b 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH v2 01/53] compiler/nir: add a nir_b2f() helper

--- src/compiler/nir/nir_builder.h | 12 1 file changed, 12 insertions(+) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 826e549019a..74ecde798d5 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -985,6 +985,18 @@

[Mesa-dev] [PATCH v2 02/53] compiler/nir: add nir_fadd_imm() and nir_fadd_imm() helpers

--- src/compiler/nir/nir_builder.h | 12 1 file changed, 12 insertions(+) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 74ecde798d5..14f3baab20b 100644 --- a/src/compiler/nir/nir_builder.h +++ b/src/compiler/nir/nir_builder.h @@ -571,6 +571,18 @@

Re: [Mesa-dev] [PATCH 03/25] amd/common: cleanup DATA_FORMAT/NUM_FORMAT field names

On 17.12.18 04:23, Marek Olšák wrote: > The definitions weren't changed, but the values were. The names need to > be different, so that si_debug.c prints both the GFX6 and GFX9 values. You're right. I have some larger changes of the debug printing that is smarter about which fields to print

Re: [Mesa-dev] [PATCH] docs: Document and *require* usage of Signed-off-by

On 30/11/18 17:32, Ian Romanick wrote: > On 11/29/2018 03:53 PM, Eric Anholt wrote: >> e<#secure method=pgpmime mode=sign> >> Erik Faye-Lund writes: >> >>> On Wed, 2018-11-28 at 13:43 -0800, Eric Anholt wrote: Jordan Justen writes: > This adds the "Developer's Certificate of

[Mesa-dev] [PATCH v2 5/5] nir: link time opt duplicate varyings

If we are outputting the same value to more than one output component rewrite the inputs to read from a single component. This will allow the duplicate varying components to be optimised away by the existing opts. shader-db results i965 (SKL): total instructions in shared programs: 12869230 ->

[Mesa-dev] [PATCH v2 3/5] nir: add can_replace_varying() helper

This will be reused by the following patch. Reviewed-by: Marek Olšák --- src/compiler/nir/nir_linking_helpers.c | 16 ++-- 1 file changed, 14 insertions(+), 2 deletions(-) diff --git a/src/compiler/nir/nir_linking_helpers.c b/src/compiler/nir/nir_linking_helpers.c index

[Mesa-dev] [PATCH v2 1/5] st/glsl_to_nir: call nir_lower_load_const_to_scalar() in the st

This will help the new opt introduced in the following patches allowing us to remove extra duplicate varyings. Reviewed-by: Marek Olšák --- src/gallium/drivers/radeonsi/si_shader_nir.c | 2 -- src/mesa/state_tracker/st_glsl_to_nir.cpp| 4 +++- 2 files changed, 3 insertions(+), 3

[Mesa-dev] [PATCH v2 2/5] nir: rename nir_link_constant_varyings() nir_link_opt_varyings()

The following patches will add support for an addition optimisation so this function will no longer just optimise varying constants. Reviewed-by: Marek Olšák --- src/amd/vulkan/radv_pipeline.c| 4 ++-- src/compiler/nir/nir.h| 2 +-

[Mesa-dev] [PATCH v2 4/5] nir: rework nir_link_opt_varyings()

This just cleans things up a little and make things more safe for derefs. --- src/compiler/nir/nir_linking_helpers.c | 28 +++--- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/src/compiler/nir/nir_linking_helpers.c b/src/compiler/nir/nir_linking_helpers.c

[Mesa-dev] [Bug 109086] Crash software mesa with gl_select render mode

https://bugs.freedesktop.org/show_bug.cgi?id=109086 --- Comment #8 from Dmitry --- Works good with my applications. When will this patch be included in the release? -- You are receiving this mail because: You are the assignee for the bug. You are the QA Contact for the

[Mesa-dev] [PATCH] freedreno/ir3: Handle GL_NONE in get_num_components_for_glformat()

An earlier patch that introduced the function failed to handle the case where an image format layout qualifier is not specified, which is allowed in Core profiles. In these cases, nir_variable's image format is GL_NONE, and we don't need to print a debug message for those. ---

[Mesa-dev] [PATCH] intel/compiler: move nir_lower_bool_to_int32 before nir_lower_locals_to_regs

The former expects to see SSA-only things, but the latter injects registers. The assertions in the lowering where not seeing this because they asserted on the bit_size values only, not on the is_ssa field, so add that assertion too. Fixes: 11dc1307794e "nir: Add a bool to int32 lowering pass"

Re: [Mesa-dev] [PATCH] docs: Document and *require* usage of Signed-off-by

Part 3, wherein I regroup, and once again present an option where Signed-off-by is optional. (Or ... required :) https://gitlab.freedesktop.org/mesa/mesa/merge_requests/31 I turned it into 3 patches. > 21f1070b6ef docs: Add developer-certificate-of-origin.txt Adds the DCO 1.1 as a separate

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