Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Daniel Vetter
On Fri, May 21, 2021 at 8:08 PM Christian König wrote: > > Am 21.05.21 um 17:16 schrieb Daniel Vetter: > > On Fri, May 21, 2021 at 05:00:46PM +0200, Bas Nieuwenhuizen wrote: > >> On Fri, May 21, 2021 at 4:37 PM Daniel Vetter wrote: > >>> On Fri, May 21, 2021 at 11:46:23AM +0200, Bas

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Christian König
Am 21.05.21 um 17:16 schrieb Daniel Vetter: On Fri, May 21, 2021 at 05:00:46PM +0200, Bas Nieuwenhuizen wrote: On Fri, May 21, 2021 at 4:37 PM Daniel Vetter wrote: On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote: On Fri, May 21, 2021 at 11:10 AM Daniel Vetter wrote: ---

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Matthew Brost
On Fri, May 21, 2021 at 01:00:54PM +0100, Tvrtko Ursulin wrote: > > On 19/05/2021 00:58, Matthew Brost wrote: > > Add entry fpr i915 new parallel submission uAPI plan. > > > > v2: > > (Daniel Vetter): > >- Expand logical order explaination > >- Add dummy header > >- Only allow N

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Matthew Brost
On Thu, May 20, 2021 at 09:41:20PM +0200, Daniel Vetter wrote: > On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote: > > > > On 20/05/2021 10:54, Daniel Vetter wrote: > > > On Wed, May 19, 2021 at 7:19 PM Matthew Brost > > > wrote: > > > > > > > > On Wed, May 19, 2021 at 01:10:04PM

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Matthew Brost
On Thu, May 20, 2021 at 09:44:59PM +0200, Daniel Vetter wrote: > On Thu, May 20, 2021 at 08:10:59AM -0700, Matthew Brost wrote: > > On Thu, May 20, 2021 at 11:54:25AM +0200, Daniel Vetter wrote: > > > On Wed, May 19, 2021 at 7:19 PM Matthew Brost > > > wrote: > > > > > > > > On Wed, May 19, 2021

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Matthew Brost
On Fri, May 21, 2021 at 10:35:37AM +0200, Christian König wrote: > Am 20.05.21 um 23:38 schrieb Jason Ekstrand: > > On Thu, May 20, 2021 at 10:46 AM Matthew Brost > > wrote: > > > On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote: > > > > Am 19.05.21 um 18:51 schrieb Matthew Brost:

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Daniel Vetter
On Fri, May 21, 2021 at 05:00:46PM +0200, Bas Nieuwenhuizen wrote: > On Fri, May 21, 2021 at 4:37 PM Daniel Vetter wrote: > > > > On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote: > > > On Fri, May 21, 2021 at 11:10 AM Daniel Vetter > > > wrote: > > > > --- > > > >

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Bas Nieuwenhuizen
On Fri, May 21, 2021 at 4:37 PM Daniel Vetter wrote: > > On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote: > > On Fri, May 21, 2021 at 11:10 AM Daniel Vetter > > wrote: > > > --- > > > drivers/gpu/drm/amd/amdgpu/amdgpu_cs.c | 4 ++-- > > > 1 file changed, 2 insertions(+), 2

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Daniel Vetter
On Fri, May 21, 2021 at 07:58:57AM -0700, Rob Clark wrote: > On Fri, May 21, 2021 at 2:10 AM Daniel Vetter wrote: > > > > - msm is mildly entertaining. It also supports MSM_SUBMIT_NO_IMPLICIT, > > but because it doesn't use the drm/scheduler it handles fences from > > the wrong context with a

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Rob Clark
On Fri, May 21, 2021 at 2:10 AM Daniel Vetter wrote: > > - msm is mildly entertaining. It also supports MSM_SUBMIT_NO_IMPLICIT, > but because it doesn't use the drm/scheduler it handles fences from > the wrong context with a synchronous dma_fence_wait. See > submit_fence_sync() leading to

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Daniel Vetter
On Fri, May 21, 2021 at 11:46:23AM +0200, Bas Nieuwenhuizen wrote: > On Fri, May 21, 2021 at 11:10 AM Daniel Vetter wrote: > > > > Docs for struct dma_resv are fairly clear: > > > > "A reservation object can have attached one exclusive fence (normally > > associated with write operations) or N

Re: [Mesa-dev] Freenode fallout

2021-05-21 Thread Simon Ser
On Friday, May 21st, 2021 at 1:49 AM, Lyude Paul wrote: > After considering Libera and OFTC as options, the board settled on > recommending OFTC. The primary reason for this is because OFTC is > associated with our parent foundation SPI, and has a long and well known > history of involvement

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Tvrtko Ursulin
On 20/05/2021 20:41, Daniel Vetter wrote: On Thu, May 20, 2021 at 11:57:44AM +0100, Tvrtko Ursulin wrote: On 20/05/2021 10:54, Daniel Vetter wrote: On Wed, May 19, 2021 at 7:19 PM Matthew Brost wrote: On Wed, May 19, 2021 at 01:10:04PM +0200, Daniel Vetter wrote: On Tue, May 18, 2021 at

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Tvrtko Ursulin
On 19/05/2021 00:58, Matthew Brost wrote: Add entry fpr i915 new parallel submission uAPI plan. v2: (Daniel Vetter): - Expand logical order explaination - Add dummy header - Only allow N BBs in execbuf IOCTL - Configure parallel submission per slot not per gem context Cc:

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Christian König
Am 21.05.21 um 11:09 schrieb Daniel Vetter: Docs for struct dma_resv are fairly clear: "A reservation object can have attached one exclusive fence (normally associated with write operations) or N shared fences (read operations)."

Re: [Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Bas Nieuwenhuizen
On Fri, May 21, 2021 at 11:10 AM Daniel Vetter wrote: > > Docs for struct dma_resv are fairly clear: > > "A reservation object can have attached one exclusive fence (normally > associated with write operations) or N shared fences (read > operations)." > >

[Mesa-dev] [PATCH 01/11] drm/amdgpu: Comply with implicit fencing rules

2021-05-21 Thread Daniel Vetter
Docs for struct dma_resv are fairly clear: "A reservation object can have attached one exclusive fence (normally associated with write operations) or N shared fences (read operations)." https://dri.freedesktop.org/docs/drm/driver-api/dma-buf.html#reservation-objects Furthermore a review across

Re: [Mesa-dev] [Intel-gfx] [RFC 2/2] drm/doc/rfc: i915 new parallel submission uAPI plan

2021-05-21 Thread Christian König
Am 20.05.21 um 23:38 schrieb Jason Ekstrand: On Thu, May 20, 2021 at 10:46 AM Matthew Brost wrote: On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote: Am 19.05.21 um 18:51 schrieb Matthew Brost: On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote: Oh, yeah we call