Re: [Mesa-dev] [PATCH] i965/gen6/xfb: handle case where transform feedback is not active

Hi Andrey, Thanks for the report and all the analysis work on your side. I am on holidays at the momentand from tomorrow onwards I won't have reliable internet access but Samuel will be back fromhis vacaction next week and he might be be able to have a look at the problem and your patch.

Re: [Mesa-dev] [PATCH] intel: Switch the order of the 2x MSAA sample positions

Reviewed-by: Iago Toral Quiroga On Wed, 2018-08-08 at 11:30 -0700, Jason Ekstrand wrote: > The Vulkan 1.1.82 spec flipped the order to better match D3D. > > Cc: mesa-sta...@lists.freedesktop.org > --- > src/intel/blorp/blorp_blit.c | 11 ++- >

Re: [Mesa-dev] [PATCH] glsl: handle error case with ast_post_inc, ast_post_dec

Reviewed-by: Iago Toral Quiroga On Tue, 2018-08-07 at 08:20 +0300, Tapani Pälli wrote: > Return ir_rvalue::error_value with ast_post_inc, ast_post_dec if > parser error was emitted previously. This way process_array_size > won't see bogus IR generated like with commit 9c676a64273. &g

Re: [Mesa-dev] [PATCH] intel/compiler: fix lower conversions to account for predication

has been there before that commit. Iago > Reviewed-by: Jose Maria Casanova Crespo > > El 17/07/18 a las 11:10, Iago Toral Quiroga escribió: > > The pass can create a temporary result for the instruction and then > > moves from it to the original destination, however, if the origi

Re: [Mesa-dev] [PATCH] intel/compiler: fix lower conversions to account for predication

This is still pending review, any takers? Iago On Tue, 2018-07-17 at 11:10 +0200, Iago Toral Quiroga wrote: > The pass can create a temporary result for the instruction and then > moves from it to the original destination, however, if the original > instruction was predicated, th

[Mesa-dev] [PATCH] intel/compiler: fix lower conversions to account for predication

The pass can create a temporary result for the instruction and then moves from it to the original destination, however, if the original instruction was predicated, the mov has to be predicated as well. --- src/intel/compiler/brw_fs_lower_conversions.cpp | 5 - 1 file changed, 4 insertions(+),

[Mesa-dev] [PATCH] intel/compiler: remove unused function

--- src/intel/compiler/brw_fs.cpp | 27 --- src/intel/compiler/brw_fs.h | 4 2 files changed, 31 deletions(-) diff --git a/src/intel/compiler/brw_fs.cpp b/src/intel/compiler/brw_fs.cpp index 38a8621f2c..99b21f6d89 100644 --- a/src/intel/compiler/brw_fs.cpp +++

Re: [Mesa-dev] [PATCH] intel/compiler: emit actual barriers for working-group level barriers

Any feedback about this? We need this to fix some new CTS tests. On Thu, 2018-06-21 at 13:52 +0200, Iago Toral Quiroga wrote: > Until now we have assumed that we could skip emitting these barriers > in the general case based on empirical testing and a few assumptions > detailed in

Re: [Mesa-dev] [PATCH] anv/pipeline: honor the pipeline_cache_enabled run-time flag

On Mon, 2018-07-09 at 08:22 +0200, Iago Toral wrote: > On Fri, 2018-07-06 at 15:50 +0100, Lionel Landwerlin wrote: > > On 04/07/18 09:44, Iago Toral Quiroga wrote: > > > --- > > > src/intel/vulkan/anv_pipeline_cache.c | 37 +++- > > > -- > &

Re: [Mesa-dev] [PATCH] anv/pipeline: honor the pipeline_cache_enabled run-time flag

On Fri, 2018-07-06 at 15:50 +0100, Lionel Landwerlin wrote: > On 04/07/18 09:44, Iago Toral Quiroga wrote: > > --- > > src/intel/vulkan/anv_pipeline_cache.c | 37 +++--- > > - > > 1 file changed, 20 insertions(+), 17 deletions(-) >

Re: [Mesa-dev] [PATCH 3/3] intel/compiler: add an optimization pass for booleans

On Thu, 2018-07-05 at 15:47 -0700, Caio Marcelo de Oliveira Filho wrote: > (I had to stop reading to go home last Tuesday, so here are the > remaining comments.) > > > On Tue, May 15, 2018 at 01:05:21PM +0200, Iago Toral Quiroga wrote: > > NIR assumes that all booleans

[Mesa-dev] [PATCH] anv/pipeline: honor the pipeline_cache_enabled run-time flag

--- src/intel/vulkan/anv_pipeline_cache.c | 37 +++ 1 file changed, 20 insertions(+), 17 deletions(-) diff --git a/src/intel/vulkan/anv_pipeline_cache.c b/src/intel/vulkan/anv_pipeline_cache.c index d4c7262dc0..5825bf9f01 100644 ---

Re: [Mesa-dev] [PATCH 3/3] intel/compiler: add an optimization pass for booleans

On Tue, 2018-07-03 at 18:45 -0700, Caio Marcelo de Oliveira Filho wrote: > Hi, > > > > + /* Look for any follow-up instructions that sources from the > > boolean > > +* result of the producer instruction and rewrite them to use > > the correct > > +* bit-size. > > +*/ > > +

Re: [Mesa-dev] [PATCH 4/4] anv/cmd_buffer: only emit state base address if the address changes

On Mon, 2018-07-02 at 08:23 -0500, Jason Ekstrand wrote: > On July 2, 2018 01:09:38 Iago Toral wrote: > > > On Sun, 2018-07-01 at 18:30 -0500, Jason Ekstrand wrote: > > > On June 29, 2018 03:11:00 Iago Toral Quiroga > > > wrote: > > > > > > >

Re: [Mesa-dev] [PATCH v2 0/9] anv, nir: Move large constants to a UBO

For the series: Reviewed-by: Iago Toral Quiroga On Fri, 2018-06-29 at 17:13 -0700, Jason Ekstrand wrote: > This little series adds an optimization pass to NIR and wires up up > in anv > that moves large constant variables to a UBO. This fixes a farily > common > case in some fi

Re: [Mesa-dev] [PATCH 1/4] anv/cmd_buffer: never shrink the push constant buffer size

Sure, I will add that. > Regardless this series is : > > Reviewed-by: Lionel Landwerlin Thanks, I'll push the first 3 for now. > Thanks! > > On 29/06/18 09:10, Iago Toral Quiroga wrote: > > If we have to re-emit push constant data, we need to re-emit all

Re: [Mesa-dev] [PATCH 3/4] anv/cmd_buffer: make descriptors dirty when emitting base state address

On Sun, 2018-07-01 at 18:32 -0500, Jason Ekstrand wrote: > 1-3 are R-b me. Should we cc stable? Yes, I think these should go to stable. > On June 29, 2018 03:11:00 Iago Toral Quiroga > wrote: > > > Every time we emit a new state base address we will need to re-emit > >

Re: [Mesa-dev] [PATCH 4/4] anv/cmd_buffer: only emit state base address if the address changes

On Sun, 2018-07-01 at 18:30 -0500, Jason Ekstrand wrote: > On June 29, 2018 03:11:00 Iago Toral Quiroga > wrote: > > > --- > > src/intel/vulkan/anv_private.h | 5 + > > src/intel/vulkan/genX_cmd_buffer.c | 12 +++- > > 2 files chang

[Mesa-dev] [PATCH 2/4] anv/cmd_buffer: clean dirty push constants flag after emitting push constants

--- src/intel/vulkan/genX_cmd_buffer.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index 97b321ccaeb..66d1ef7d786 100644 --- a/src/intel/vulkan/genX_cmd_buffer.c +++ b/src/intel/vulkan/genX_cmd_buffer.c @@ -3008,6

[Mesa-dev] [PATCH 3/4] anv/cmd_buffer: make descriptors dirty when emitting base state address

Every time we emit a new state base address we will need to re-emit our binding tables, since they might have been emitted with a different base state adress. --- src/intel/vulkan/genX_cmd_buffer.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/vulkan/genX_cmd_buffer.c

[Mesa-dev] [PATCH 4/4] anv/cmd_buffer: only emit state base address if the address changes

--- src/intel/vulkan/anv_private.h | 5 + src/intel/vulkan/genX_cmd_buffer.c | 12 +++- 2 files changed, 12 insertions(+), 5 deletions(-) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index 510471da602..1a9ab7013f2 100644 ---

[Mesa-dev] [PATCH 1/4] anv/cmd_buffer: never shrink the push constant buffer size

If we have to re-emit push constant data, we need to re-emit all of it. --- src/intel/vulkan/anv_cmd_buffer.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_cmd_buffer.c b/src/intel/vulkan/anv_cmd_buffer.c index 33687920a38..3e9f000f7b8 100644 ---

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: emit binding tables always if push constants are dirty

On Thu, 2018-06-28 at 08:47 +0200, Iago Toral wrote: > On Wed, 2018-06-27 at 09:13 -0700, Jason Ekstrand wrote: > > On Wed, Jun 27, 2018 at 2:25 AM, Iago Toral > > wrote: > > > On Tue, 2018-06-26 at 10:59 -0700, Jason Ekstrand wrote: > > > > On Tue, Jun 26,

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: emit binding tables always if push constants are dirty

On Wed, 2018-06-27 at 09:13 -0700, Jason Ekstrand wrote: > On Wed, Jun 27, 2018 at 2:25 AM, Iago Toral > wrote: > > On Tue, 2018-06-26 at 10:59 -0700, Jason Ekstrand wrote: > > > On Tue, Jun 26, 2018 at 4:08 AM, Iago Toral Quiroga > > a.com> wrote: > > >

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: emit binding tables always if push constants are dirty

On Tue, 2018-06-26 at 10:59 -0700, Jason Ekstrand wrote: > On Tue, Jun 26, 2018 at 4:08 AM, Iago Toral Quiroga m> wrote: > > Storage images require to patch push constant stateto work, which > > happens during > > > > binding table emision. In the scenario where ou

[Mesa-dev] [PATCH] anv/cmd_buffer: emit binding tables always if push constants are dirty

Storage images require to patch push constant stateto work, which happens during binding table emision. In the scenario where our pipeline and descriptors are not dirty, we don't re-emit the binding table, however, if our push constant state is dirty, we will re-emit the push constant state,

Re: [Mesa-dev] [PATCH v3] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

Thanks for testing Mark. Andrii, I'll add my Reviewed-by and and push the patch to master later today (I'll also queue it for the next stable release). Thanks for fixing this! Iago On Fri, 2018-06-22 at 13:18 -0700, Mark Janes wrote: > Tested-by: Mark Janes > > Iago Tora

Re: [Mesa-dev] [PATCH v3] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

Thanks Andrii, this version looks good to me. Mark: this change fixes a GPU hang in sandy bridge with geometry shaders (the change itself affects a path in the driver that is only executed in SNB with GS, so nothing else is affected). While I think the change in here is correct according to the

Re: [Mesa-dev] [PATCH v2] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

Hi Andrii, thanks for verifying my suggestion and sending the new patch. However, this patch is the diff against your previous patch, please merge both patches into a single patch so we get a single patch with all the changes against current master. Once we have that I'll run the resulting

[Mesa-dev] [PATCH] intel/compiler: emit actual barriers for working-group level barriers

Until now we have assumed that we could skip emitting these barriers in the general case based on empirical testing and a few assumptions detailed in a comment in the driver code, however, recent CTS tests have showed that we actually need them to produce correct behavior. ---

Re: [Mesa-dev] [PATCH] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

located to those threads. > >Programming Note: [Pre-DevIL] GS and Clip threads must terminate >by sending a URB_WRITE message (with EOT set) with the Complete > bit also >set (therein returning a URB handle marked as either used or un- > used). " > > Only P

Re: [Mesa-dev] [PATCH] i965/gen6/gs: Handle case where a GS doesn't allocate VUE

On Tue, 2018-06-19 at 17:06 +0300, Andrii Simiklit wrote: > We can not use the VUE Dereference flags combination for EOT > message under ILK and SNB because the threads are not initialized > there with initial VUE handle unlike Pre-IL. > So to avoid GPU hangs on SNB and ILK we need > to avoid

Re: [Mesa-dev] [PATCH] Fix 105399 bug GPU hang on SNB using geometry shader. The end of thread (EOT) message with flags Complete=1 and Used=0 will leads to GPU hang on SNB and ILK when GS does not all

Hi Andrii, thanks for the fix! Kenneth, this patch makes it so that we end the GS program with and ENDIF. I remember that back in the day when I wrote this code you had concerns about that (that's why I added that comment), but that was a long time ago so maybe things have changed, do you know

Re: [Mesa-dev] [PATCH mesa] mesa: add missing return in error path

Reviewed-by: Iago Toral Quiroga On Mon, 2018-06-18 at 11:40 +0100, Eric Engestrom wrote: > Fixes: 67f40dadaadacd90 "mesa: add support for > ARB_sample_locations" > Cc: Rhys Perry > Cc: Brian Paul > Signed-off-by: Eric Engestrom > --- > src/mesa/main/fbobje

Re: [Mesa-dev] [PATCH] mesa: add better GLSL override support for compat profile

at = ctx->Version * 10; > + } > break; Looks like we should be able to just do this after the switch right?: ctx->Const.GLSLVersionCompat = ctx->Const.GLSLVersion; I'd prefer this unless there is something I am missing. With that: Reviewed-by: Iago Toral Quiroga >} > } ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa: add ff fragment shader support for geom and tess shaders

On Mon, 2018-06-18 at 10:45 +0200, Gustaw Smolarczyk wrote: > 2018-06-18 10:39 GMT+02:00 Iago Toral : > > On Mon, 2018-06-18 at 09:43 +0200, Gustaw Smolarczyk wrote: > > > 2018-06-18 4:39 GMT+02:00 Timothy Arceri : > > > > This is required for

Re: [Mesa-dev] [PATCH] mesa: add ff fragment shader support for geom and tess shaders

uldn't you also update the if condition on line 178? Otherwise, > you won't reach the if tree you change when the vertex shader is > missing (unless that was intended - I am not really familiar with how > fixed function shaders work alongside new features). You don't have Tesselation / Geo

Re: [Mesa-dev] [PATCH 1/6] i965/fs: Optimize OR with 0 into a MOV

I dropped a suggestion in patch 1 that also applies to patch 3, feel free to take it or not, and then I pointed out a small issue in patch 6 that I think should be addressed that I think should be fixed. Otherwise, the series is: Reviewed-by: Iago Toral Quiroga On Thu, 2018-06-14 at 17:43 -0700

Re: [Mesa-dev] [PATCH 6/6] i965/fs: Propagate conditional modifiers from not instructions

On Thu, 2018-06-14 at 17:43 -0700, Ian Romanick wrote: > From: Ian Romanick > > Skylake > total instructions in shared programs: 14399081 -> 14399010 (<.01%) > instructions in affected programs: 26961 -> 26890 (-0.26%) > helped: 57 > HURT: 0 > helped stats (abs) min: 1 max: 6 x̄: 1.25 x̃: 1 >

Re: [Mesa-dev] [PATCH 1/6] i965/fs: Optimize OR with 0 into a MOV

On Thu, 2018-06-14 at 17:43 -0700, Ian Romanick wrote: > From: Ian Romanick > > fs_visitor::set_gs_stream_control_data_bits generates some code like > "control_data_bits | stream_id << ((2 * (vertex_count - 1)) % 32)" as > part of EmitVertex. The first time this (dynamically) occurs in the >

Re: [Mesa-dev] [PATCH 07/14] intel/compiler: shuffle_from_32bit_read for 64-bit do_untyped_vector_read

On Fri, 2018-06-15 at 00:20 +0200, Chema Casanova wrote: > > On 14/06/18 03:26, Jason Ekstrand wrote: > > On Sat, Jun 9, 2018 at 4:13 AM, Jose Maria Casanova Crespo > > mailto:jmcasan...@igalia.com>> wrote: > > > > do_untyped_vector_read is used at load_ssbo and load_shared. > > > > The

Re: [Mesa-dev] [PATCH 0/3] intel: implement an optimization pass to clean-up boolean conversions

This isn't reviewed yet, any feedback? Iago On Tue, 2018-05-15 at 13:05 +0200, Iago Toral Quiroga wrote: > NIR assumes that all booleans are 32-bit, so drivers need to produce > 32-bit > booleans even if they can produce native booleans of a different bit- > size, like > Intel d

Re: [Mesa-dev] [PATCH] glsl: Add ir_binop_vector_extract in NIR

On Fri, 2018-06-01 at 12:26 +0200, Iago Toral wrote: > On Fri, 2018-06-01 at 11:25 +0200, Juan A. Suarez Romero wrote: > > On Wed, 2018-05-30 at 15:10 -0700, Eric Anholt wrote: > > > "Juan A. Suarez Romero" writes: > > > > > > > Implement ir

Re: [Mesa-dev] [PATCH] glsl: Add ir_binop_vector_extract in NIR

On Fri, 2018-06-01 at 11:25 +0200, Juan A. Suarez Romero wrote: > On Wed, 2018-05-30 at 15:10 -0700, Eric Anholt wrote: > > "Juan A. Suarez Romero" writes: > > > > > Implement ir_binop_vector_extract using NIR operations. Based on > > > SPIR-V > > > to NIR approach. > > > > > > This fixes: > >

Re: [Mesa-dev] [PATCH 2/2] nir: Lower !f2b(x) to x == 0.0

Reviewed-by: Iago Toral Quiroga On Thu, 2018-05-31 at 17:21 -0700, Ian Romanick wrote: > From: Ian Romanick > > Some trivial help now, but it also prevents ~40 regressions caused by > Samuel's "nir: implement the GLSL equivalent of if simplication in > nir_opt_if&q

Re: [Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

On Mon, 2018-05-21 at 13:49 +0300, Eero Tamminen wrote: > Hi, > > On 21.05.2018 10:42, Iago Toral wrote: > > On Fri, 2018-05-18 at 12:08 +0300, Eero Tamminen wrote: > > > On 17.05.2018 14:25, Eero Tamminen wrote: > > > > On 17.05.2018 11:46, Iago Toral Quir

Re: [Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

On Thu, 2018-05-17 at 06:59 -0700, Jason Ekstrand wrote: > > On May 17, 2018 01:47:11 Iago Toral Quiroga <ito...@igalia.com> > wrote: > > > --- > > src/compiler/spirv/vtn_alu.c | 4 +++- > > 1 file changed, 3 insertions(+), 1 deletion(-) > > > >

[Mesa-dev] [PATCH 19/22] intel/compiler: lower 16-bit fmod

--- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 6480dbefbf6..36a870ece0d 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@

[Mesa-dev] [PATCH 21/22] intel/compiler: lower 16-bit flrp

--- src/intel/compiler/brw_compiler.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/compiler/brw_compiler.c b/src/intel/compiler/brw_compiler.c index 36a870ece0d..250e4695ded 100644 --- a/src/intel/compiler/brw_compiler.c +++ b/src/intel/compiler/brw_compiler.c @@ -33,6 +33,7 @@

[Mesa-dev] [PATCH 20/22] compiler/nir: add lowering for 16-bit flrp

--- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index 59c84bde268..7e4c78cc1b7 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1871,6

[Mesa-dev] [PATCH 22/22] intel/compiler: Extended Math is limited to SIMD8 on half-float

From the Skylake PRM, Extended Math Function: "The execution size must be no more than 8 when half-floats are used in source or destination operand." Earlier generations do not support Extended Math with half-float. --- src/intel/compiler/brw_fs.cpp | 30 +++--- 1

[Mesa-dev] [PATCH 17/22] compiler/spirv: implement 16-bit frexp

--- src/compiler/spirv/vtn_glsl450.c | 48 ++-- 1 file changed, 46 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 738f1ea93f1..88d2dcfb0fd 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 18/22] compiler/nir: add lowering option for 16-bit fmod

--- src/compiler/nir/nir.h| 1 + src/compiler/nir/nir_opt_algebraic.py | 1 + 2 files changed, 2 insertions(+) diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h index a379928cdcd..59c84bde268 100644 --- a/src/compiler/nir/nir.h +++ b/src/compiler/nir/nir.h @@ -1877,6

[Mesa-dev] [PATCH 16/22] compiler/spirv: implement 16-bit hyperbolic trigonometric functions

--- src/compiler/spirv/vtn_glsl450.c | 29 +++-- 1 file changed, 19 insertions(+), 10 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 324e8b5874a..738f1ea93f1 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 14/22] compiler/spirv: implement 16-bit atan2

--- src/compiler/spirv/vtn_glsl450.c | 22 +++--- 1 file changed, 15 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 9e565ef9e5a..70e3eb80c4c 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 13/22] compiler/spirv: implement 16-bit atan

--- src/compiler/spirv/vtn_glsl450.c | 37 + 1 file changed, 25 insertions(+), 12 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 8cbdaad3998..9e565ef9e5a 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 15/22] compiler/spirv: implement 16-bit exp and log

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 70e3eb80c4c..324e8b5874a 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH 12/22] compiler/spirv: implement 16-bit acos

--- src/compiler/spirv/vtn_glsl450.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 845e5a9e517..8cbdaad3998 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++ b/src/compiler/spirv/vtn_glsl450.c @@

[Mesa-dev] [PATCH 10/22] intel/compiler: allow extended math functions with HF operands

The PRM states that half-float operands are supported since gen9. --- src/intel/compiler/brw_eu_emit.c | 6 -- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/intel/compiler/brw_eu_emit.c b/src/intel/compiler/brw_eu_emit.c index ee5a048bcaa..20c3f9fa933 100644 ---

[Mesa-dev] [PATCH 11/22] compiler/spirv: implement 16-bit asin

--- src/compiler/spirv/vtn_glsl450.c | 20 +--- 1 file changed, 13 insertions(+), 7 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index ffe12a71818..845e5a9e517 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 09/22] intel/compiler: implement 16-bit multiply-add

The PRM for MAD states that F, DF and HF are supported, however, then it requires that the instruction includes a 2-bit mask specifying the types of each operand like this: 00: 32-bit float 01: 32-bit signed integer 10: 32-bit unsigned integer 11: 64-bit float So 16-bit float would not be

[Mesa-dev] [PATCH 08/22] intel/compiler: implement 16-bit fsign

--- src/intel/compiler/brw_fs_nir.cpp | 27 +-- 1 file changed, 21 insertions(+), 6 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index fb5ad7a614a..91283ab4911 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 06/22] compiler/nir: support 16-bit float in nir_imm_floatN_t

--- src/compiler/nir/nir_builder.h | 29 - 1 file changed, 16 insertions(+), 13 deletions(-) diff --git a/src/compiler/nir/nir_builder.h b/src/compiler/nir/nir_builder.h index 02a9dbfb040..198c42dd823 100644 --- a/src/compiler/nir/nir_builder.h +++

[Mesa-dev] [PATCH 07/22] compiler/spirv: handle 16-bit float in radians() and degrees()

--- src/compiler/spirv/vtn_glsl450.c | 10 -- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/src/compiler/spirv/vtn_glsl450.c b/src/compiler/spirv/vtn_glsl450.c index 6fa759b1bba..ffe12a71818 100644 --- a/src/compiler/spirv/vtn_glsl450.c +++

[Mesa-dev] [PATCH 04/22] intel/compiler: lower some 16-bit float operations to 32-bit

The hardware doesn't support half-float for these. --- src/intel/compiler/brw_nir.c | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index dfeea73b06a..ff245b59b81 100644 --- a/src/intel/compiler/brw_nir.c +++

[Mesa-dev] [PATCH 03/22] compiler/spirv: fix SpvOpIsInf for 16-bit float

--- src/compiler/spirv/vtn_alu.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 5f9cc97fdfb..62a5149797a 100644 --- a/src/compiler/spirv/vtn_alu.c +++ b/src/compiler/spirv/vtn_alu.c @@ -578,7 +578,9 @@

[Mesa-dev] [PATCH 05/22] intel/compiler: lower 16-bit extended math to 32-bit prior to gen9

Extended math desn't support half-float on these generations. --- src/intel/compiler/brw_nir.c | 13 - 1 file changed, 12 insertions(+), 1 deletion(-) diff --git a/src/intel/compiler/brw_nir.c b/src/intel/compiler/brw_nir.c index ff245b59b81..8337da57585 100644 ---

[Mesa-dev] [PATCH 02/22] i965/fs: Implement float64 to float16 conversion

From: Samuel Iglesias Gonsálvez It is not supported directly in the HW, we need to convert to float32 first as intermediate step. Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 17 + 1 file changed,

[Mesa-dev] [PATCH 01/22] i965/fs: implement conversions from float16 to 64 bits data types

From: Samuel Iglesias Gonsálvez Signed-off-by: Samuel Iglesias Gonsálvez --- src/intel/compiler/brw_fs_nir.cpp | 32 1 file changed, 32 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp

Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

On Wed, 2018-05-16 at 08:44 -0700, Jason Ekstrand wrote: > On Wed, May 16, 2018 at 4:00 AM, Iago Toral <ito...@igalia.com> > wrote: > > On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > > > > > Now that anv uses blorp_ccs_op for everything, we no lon

[Mesa-dev] [PATCH 00/22] spirv/intel: half-float compiler enablement

which we address here. The series contains two patches from Samuel that handle float64/16 conversions, which had been posted in the mailing list some time ago and that are also relevant to this. Iago Toral Quiroga (20): compiler/spirv: fix SpvOpIsInf for 16-bit float intel/compiler: lower some

Re: [Mesa-dev] [PATCH 0/9] intel/blorp: Refactors, cleanups, and fixes

, patches 3-9 are: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> Iago On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > This little series makes a bunch of mostly small changes to > blorp. The end > objective is to get to the point where you just call blorp_cc

Re: [Mesa-dev] [PATCH 8/9] intel/blorp: Handle fast-clear directly in blorp_ccs_op

On Wed, 2018-05-16 at 13:34 +0200, Iago Toral wrote: > On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > > --- > > src/intel/blorp/blorp_clear.c | 199 +++--- > > -- > > -- > > 1 file changed, 88 insertions(+), 111 delet

Re: [Mesa-dev] [PATCH 8/9] intel/blorp: Handle fast-clear directly in blorp_ccs_op

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > --- > src/intel/blorp/blorp_clear.c | 199 +++- > -- > 1 file changed, 88 insertions(+), 111 deletions(-) > > diff --git a/src/intel/blorp/blorp_clear.c > b/src/intel/blorp/blorp_clear.c > index

Re: [Mesa-dev] [PATCH 7/9] i965: Use blorp_ccs_op for CCS fast-clears

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > --- > src/mesa/drivers/dri/i965/brw_blorp.c | 12 +--- > 1 file changed, 9 insertions(+), 3 deletions(-) > > diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c > b/src/mesa/drivers/dri/i965/brw_blorp.c > index dab04f2..b6097f5

Re: [Mesa-dev] [PATCH 6/9] intel/blorp: Make blorp_ccs_ambiguate just an internal helper

On Tue, 2018-05-15 at 15:28 -0700, Jason Ekstrand wrote: > Now that anv uses blorp_ccs_op for everything, we no longer need to > expose the ccs_ambiguate function directly. It's much better tucked > away as an implementation detail. > --- > src/intel/blorp/blorp.h | 5 - >

[Mesa-dev] [PATCH 2/3] intel/compiler: add a region_match() helper

This checks whether two register regions are an exact match. --- src/intel/compiler/brw_ir_fs.h | 13 + 1 file changed, 13 insertions(+) diff --git a/src/intel/compiler/brw_ir_fs.h b/src/intel/compiler/brw_ir_fs.h index f06a33c516d..cad333b6b6d 100644 ---

[Mesa-dev] [PATCH 0/3] intel: implement an optimization pass to clean-up boolean conversions

booleans, losing the possibility to emit native 16-bit boolean instructions where possible. Iago Toral Quiroga (3): intel/compiler: make brw_reg_type_from_bit_size usable from other places intel/compiler: add a region_match() helper intel/compiler: add an optimization pass for booleans src

[Mesa-dev] [PATCH 3/3] intel/compiler: add an optimization pass for booleans

NIR assumes that all booleans are 32-bit but Intel hardware produces booleans of the same size as the operands to the CMP instruction, so we can actually have 8-bit and 16-bit booleans. To work around this mismatch between NIR and the hardware, we emit boolean conversions to 32-bit right after

[Mesa-dev] [PATCH 1/3] intel/compiler: make brw_reg_type_from_bit_size usable from other places

This was private to brw_fs_nir.cpp but we are going to need it soon in brw_fs.cpp, so move it there and make it available to other files as we do for other utility functions. --- src/intel/compiler/brw_fs.cpp | 59 +++ src/intel/compiler/brw_fs.h | 4

[Mesa-dev] [PATCH 2/4] i965/compiler: handle conversion to smaller type in the lowering pass for that

This rollbacks the revert of this same patch introduced in commit 7b9c15628aae8729118b648f5f473e6ac926b99b. --- src/intel/compiler/brw_fs_lower_conversions.cpp | 5 - src/intel/compiler/brw_fs_nir.cpp | 14 +++--- 2 files changed, 7 insertions(+), 12 deletions(-) diff

[Mesa-dev] [PATCH 4/4] anv/device: expose shaderInt16 support in gen8+

This rollbacks the revert of this patch introduced with commit 7cf284f18e6774c810ed6db17b98e597bf96f8a5. --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 0563eae5c1..fd516fb846

[Mesa-dev] [PATCH 1/4] intel/compiler: handle 16-bit to 64-bit conversions in BSW platforms

These are subject to the general restriction that anything that is converted to 64-bit needs to be aligned to 64-bit. We had this already in place for 32-bit to 64-bit conversions, so this patch generalizes the implementation to take effect on any conversion to 64-bit from a source smaller than

[Mesa-dev] [PATCH 3/4] intel/compiler: Fix lower_conversions for 8-bit types.

From: Jose Maria Casanova Crespo For 8-bit types the execution type is word. A byte raw MOV has 16-bit execution type and 8-bit destination and it shouldn't be considered a conversion case. So there is no need to change alignment and enter in lower_conversions for these

[Mesa-dev] [PATCH 0/4] Intel: fixes to regressions caused by shaderInt16

and didn't get any regressions but since I didn't get them when I was testing the original shaderInt16 I'd ask if you can verify the fixes on your end (specially on BSW-like platforms). Iago Iago Toral Quiroga (3): intel/compiler: handle 16-bit to 64-bit conversions in BSW platforms i965

Re: [Mesa-dev] [PATCH v2 00/18] anv: add shaderInt16 support

On Thu, 2018-05-03 at 11:44 -0700, Clayton Craft wrote: > Quoting Iago Toral Quiroga (2018-04-30 07:18:08) > > This version addresses the feedback received to v1, which includes > > moving the > > bit-size lowering pass from intel to core NIR (patch 8) and a > > separa

Re: [Mesa-dev] [PATCH v2 7.5/18] intel/compiler: support negate and abs of half float immediates

On Thu, 2018-05-03 at 08:39 +0200, Iago Toral wrote: > On Wed, 2018-05-02 at 17:57 -0700, Jason Ekstrand wrote: > > Reviewed-by: Jason Ekstrand <ja...@jlekstrand.net> > > > > Have I reviewed everything? Can we land shaderInt16 now? > > Yes, all patches are r

Re: [Mesa-dev] [PATCH v2 7.5/18] intel/compiler: support negate and abs of half float immediates

On Wed, 2018-05-02 at 17:57 -0700, Jason Ekstrand wrote: > Reviewed-by: Jason Ekstrand > > Have I reviewed everything? Can we land shaderInt16 now? Yes, all patches are reviewed now, thanks Jason.I'll send the final set of patches to Jenkins one last time and push them

[Mesa-dev] [PATCH v3] intel/compiler: fix 16-bit comparisons

NIR assumes that booleans are always 32-bit, but Intel hardware produces 16-bit booleans for 16-bit comparisons. This means that we need to convert the 16-bit result to 32-bit. In the future we want to add an optimization pass to clean this up and hopefully remove the conversions. v2 (Jason):

Re: [Mesa-dev] [PATCH v2 10/18] intel/compiler: fix 16-bit comparisons

On Mon, 2018-04-30 at 14:43 -0700, Jason Ekstrand wrote: > On Mon, Apr 30, 2018 at 7:18 AM, Iago Toral Quiroga <ito...@igalia.co > m> wrote: > > NIR assumes that booleans are always 32-bit, but Intel hardware > > produces > > > > 16-bit booleans for 16-bit

[Mesa-dev] [PATCH v2 18/18] anv/device: expose shaderInt16 support in gen8+

Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index b456d3d4c5..d123ae16ec 100644 --- a/src/intel/vulkan/anv_device.c +++

[Mesa-dev] [PATCH v2 17/18] anv/pipeline: support SpvCapabilityInt16 in gen8+

Reviewed-by: Jason Ekstrand --- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index 56bea7bf0d..87788de10a 100644 --- a/src/intel/vulkan/anv_pipeline.c +++

[Mesa-dev] [PATCH v2 14/18] compiler/spirv: implement 16-bit bitcasts

--- src/compiler/spirv/vtn_alu.c | 31 ++- 1 file changed, 22 insertions(+), 9 deletions(-) diff --git a/src/compiler/spirv/vtn_alu.c b/src/compiler/spirv/vtn_alu.c index 3134849ba9..3708a9dc0c 100644 --- a/src/compiler/spirv/vtn_alu.c +++

[Mesa-dev] [PATCH v2 16/18] compiler/spirv: add implementation to check for SpvCapabilityInt16 support

Reviewed-by: Jason Ekstrand --- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index 53a0ef21f6..afc53a8840 100644 ---

[Mesa-dev] [PATCH v2 12/18] nir/lower_64bit_packing: extend the pass to handle packing from / to 16-bit.

With 16-bit support we can now do 32-bit packing, a follow-up patch will rename the pass to something more generic. --- src/compiler/nir/nir_lower_64bit_packing.c | 64 +++--- 1 file changed, 59 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH v2 15/18] intel/compiler: implement 16-bit pack/unpack opcodes

--- src/intel/compiler/brw_fs_nir.cpp | 10 ++ 1 file changed, 10 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index d590a00385..25e85b9b25 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@

[Mesa-dev] [PATCH v2 13/18] compiler/lower_64bit_packing: rename the pass to be more generic

It can do 32-bit packing too now. --- src/amd/vulkan/radv_shader.c| 2 +- src/compiler/Makefile.sources | 2 +- src/compiler/nir/meson.build| 2 +- src/compiler/nir/nir.h

[Mesa-dev] [PATCH v2 11/18] nir: add opcodes for 16-bit packing and unpacking

Noitice that we don't need 'split' versions of the 64-bit to / from 16-bit opcodes which we require during pack lowering to implement these operations. This is because these operations can be expressed as a collection of 32-bit from / to 16-bit and 64-bit to / from 32-bit operations, so we don't

[Mesa-dev] [PATCH v2 09/18] intel/compiler: lower some 16-bit integer operations to 32-bit

These are not supported in hardware for 16-bit integers. We do the lowering pass after the optimization loop to ensure that we lower ALU operations injected by algebraic optimizations too. --- src/intel/compiler/brw_nir.c | 21 + 1 file changed, 21 insertions(+) diff --git

[Mesa-dev] [PATCH v2 07/18] intel/compiler: fix brw_negate_immediate for 16-bit types

From: Jose Maria Casanova Crespo From Intel Skylake PRM, vol 07, "Immediate" section (page 768): "For a word, unsigned word, or half-float immediate data, software must replicate the same 16-bit immediate value to both the lower word and the high word of the 32-bit

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