[Mesa-dev] [PATCH v2 08/18] compiler/nir: add a lowering pass to convert the bit size of ALU operations

Not all bit-sizes may be supported natively in hardware for all operations. This pass allows drivers to lower such operations to a bit-size that is actually supported and then converts the result back to the original bit-size. Compiler backends control which operations and wich bit-sizes require

[Mesa-dev] [PATCH v2 10/18] intel/compiler: fix 16-bit comparisons

NIR assumes that booleans are always 32-bit, but Intel hardware produces 16-bit booleans for 16-bit comparisons. This means that we need to convert the 16-bit result to 32-bit. In the future we want to add an optimization pass to clean this up and hopefully remove the conversions. ---

[Mesa-dev] [PATCH v2 06/18] intel/compiler: fix brw_imm_w for negative 16-bit integers

From: Jose Maria Casanova Crespo 16-bit immediates need to replicate the 16-bit immediate value in both words of the 32-bit value. This needs to be careful to avoid sign-extension, which the previous implementation was not handling properly. For example, with the previous

[Mesa-dev] [PATCH v2 05/18] intel/compiler: implement nir_instr_type_load_const for 16-bit constants

From: Jose Maria Casanova Crespo Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index

[Mesa-dev] [PATCH v2 03/18] intel/compiler: implement conversion between float/int 16-bit types

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 88df51fe11..bb7ab840ef 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH v2 02/18] i965/compiler: handle conversion to smaller type in the lowering pass for that

The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_lower_conversions.cpp | 5 - src/intel/compiler/brw_fs_nir.cpp | 14

[Mesa-dev] [PATCH v2 04/18] intel/compiler: implement conversions from 16-bit int/float to bool

Reviewed-by: Jason Ekstrand --- src/intel/compiler/brw_fs_nir.cpp | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index bb7ab840ef..300884de05 100644 ---

[Mesa-dev] [PATCH v2 00/18] anv: add shaderInt16 support

. A branch with the series is available for testing in the 'itoral/shaderInt16ForReview_v2' branch of the Igalia mesa repository at github: https://github.com/Igalia/mesa/tree/itoral/shaderInt16ForReview_v2 Iago Toral Quiroga (16): intel/compiler: fix isign for 16-bit integers i965/compiler

[Mesa-dev] [PATCH v2 01/18] intel/compiler: fix isign for 16-bit integers

We need to use 16-bit constants with 16-bit instructions, otherwise we get the following validation error: "Destination stride must be equal to the ratio of the sizes of the execution data type to the destination type" Because the execution data type is 4B due to the 32-bit integer constant.

Re: [Mesa-dev] [PATCH 01/11] intel/compiler: lower 16-bit integer extended math instructions

On Wed, 2018-04-25 at 07:05 -0700, Jason Ekstrand wrote: > Some of these comments may be duplicates of ones I made the first > time through. > > On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga <itoral@igalia.c > om> wrote: > > The hardware doesn't support 16-bi

Re: [Mesa-dev] [PATCH] spirv: Don’t check for NaN for most OpFOrd* comparisons

Thanks Neil! Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> Maybe we need other drivers (radv?) to double-check that this doesn't break stuff for them either? Iago On Tue, 2018-04-24 at 16:55 +0200, Neil Roberts wrote: > For all of the OpFOrd* comparisons except OpFOr

Re: [Mesa-dev] [PATCH 03/11] i965/compiler: handle conversion to smaller type in the lowering pass for that

On Tue, 2018-04-24 at 07:58 -0700, Jason Ekstrand wrote: > On Wed, Apr 11, 2018 at 12:20 AM, Iago Toral Quiroga <itoral@igalia.c > om> wrote: > > The lowering pass was specialized to act on 64-bit to 32-bit > > conversions only, > > > > but the imp

Re: [Mesa-dev] [PATCH 01/11] intel/compiler: lower 16-bit integer extended math instructions

gt; > > BR, > -R > > On Tue, Apr 24, 2018 at 9:56 AM, Jason Ekstrand <ja...@jlekstrand.net > > > wrote: > It may be useful to just use nir_algebraic for this. We already do > for > trig > workarounds. It's more painful from a build-system perspective b

Re: [Mesa-dev] 16-bit comparisons in NIR

On Fri, 2018-04-20 at 17:16 -0700, Jason Ekstrand wrote: > On Fri, Apr 20, 2018 at 5:16 AM, Nicolai Hähnle <nhaeh...@gmail.com> > wrote: > > On 20.04.2018 10:21, Iago Toral wrote: > > > > > Hi, > > > > > > > > > > > > while d

[Mesa-dev] 16-bit comparisons in NIR

Hi, while developing support for Vulkan shaderInt16 on Anvil I came across a feature of NIR that was a bit inconvenient: bools are always 32-bit by design, but the Intel hardware produces 16-bit bool results for 16- bit comparisons, so that creates a problem that manifests like this: vec1 32

Re: [Mesa-dev] [PATCH] i965/fs: retype offset_reg to UD at load_ssbo

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2018-04-18 at 22:57 +0200, Jose Maria Casanova Crespo wrote: > All operations with offset_reg at do_vector_read are done > with UD type. So copy propagation was not working through > the generated MOVs: > > mov

Re: [Mesa-dev] [PATCH] mesa: free debug messages when destroying the debug state

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Fri, 2018-04-13 at 15:31 +1000, Timothy Arceri wrote: > Fixes: 04a8baad3721 "mesa: refactor _mesa_PopDebugGroup and > _mesa_free_errors_data" > > Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=

Re: [Mesa-dev] [PATCH v2] getteximage: assume texture image is empty for non defined levels

ning INVALID_VALUE to the caller" > > This fixes arb_get_texture_sub_image piglit tests. > > v2: just return INVALID_VALUE if there isno defined level (Iago) ^ white space Reviewed-by: Iag

Re: [Mesa-dev] [PATCH 3/3] getteximage: assume texture image is empty for non defined levels

On Wed, 2018-04-11 at 19:51 +0200, Juan A. Suarez Romero wrote: > Current code is returning an INVALID_OPERATION when trying to use > getTextureImage() on a level that has not been explicitly defined. > > That is, we define a mipmapped Texture2D with 3 levels, and try to > use > GetTextureImage()

Re: [Mesa-dev] [PATCH 1/3] gettextsubimage: verify zoffset and depth are correct

Patches 1-2 are: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2018-04-11 at 19:51 +0200, Juan A. Suarez Romero wrote: > According to OpenGL 4.6 spec, section 8.11.4 ("Texture Image > Queries"), > relative to errors for GetTextureSubImage() function: >

[Mesa-dev] [PATCH 05/11] intel/compiler: implement conversions from 16-bit int/float to bool

--- src/intel/compiler/brw_fs_nir.cpp | 16 +++- 1 file changed, 11 insertions(+), 5 deletions(-) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5c414e45b61..ad31f7c82dc 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++

[Mesa-dev] [PATCH 11/11] anv/device: expose shaderInt16 support in gen8+

--- src/intel/vulkan/anv_device.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c index 7522b7865c2..306d5beff7d 100644 --- a/src/intel/vulkan/anv_device.c +++ b/src/intel/vulkan/anv_device.c @@ -759,7 +759,7 @@

[Mesa-dev] [PATCH 08/11] intel/compiler: fix brw_negate_immediate for 16-bit types

From: Jose Maria Casanova Crespo 16-bit immediates are replicated in each word of a 32-bit value so we need to negate both. --- src/intel/compiler/brw_shader.cpp | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/intel/compiler/brw_shader.cpp

[Mesa-dev] [PATCH 06/11] nir/constant_folding: support 16-bit constants

From: Jose Maria Casanova Crespo --- src/compiler/nir/nir_opt_constant_folding.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/compiler/nir/nir_opt_constant_folding.c b/src/compiler/nir/nir_opt_constant_folding.c index d6be807b3dc..b63660ea4da 100644 ---

[Mesa-dev] [PATCH 10/11] anv/pipeline: support SpvCapabilityInt16 in gen8+

--- src/intel/vulkan/anv_pipeline.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/intel/vulkan/anv_pipeline.c b/src/intel/vulkan/anv_pipeline.c index e64602d2844..be935363869 100644 --- a/src/intel/vulkan/anv_pipeline.c +++ b/src/intel/vulkan/anv_pipeline.c @@ -144,6 +144,7 @@

[Mesa-dev] [PATCH 09/11] compiler/spirv: add implementation to check for SpvCapabilityInt16 support

--- src/compiler/shader_info.h| 1 + src/compiler/spirv/spirv_to_nir.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h index ababe520b2d..15a8910c597 100644 --- a/src/compiler/shader_info.h +++

[Mesa-dev] [PATCH 02/11] intel/compiler: fix isign for 16-bit integers

We need to use 16-bit constants with 16-bit instructions, otherwise we get the following validation error: "Destination stride must be equal to the ratio of the sizes of the execution data type to the destination type" Because the execution data type is 4B due to the 32-bit integer constant.

[Mesa-dev] [PATCH 00/11] anv: add shaderInt16 support

to the reviewers :) Iago Toral Quiroga (8): intel/compiler: lower 16-bit integer extended math instructions intel/compiler: fix isign for 16-bit integers i965/compiler: handle conversion to smaller type in the lowering pass for that intel/compiler: implement conversion between float/int

[Mesa-dev] [PATCH 01/11] intel/compiler: lower 16-bit integer extended math instructions

The hardware doesn't support 16-bit integer types, so we need to implement these using 32-bit integer instructions and then convert the result back to 16-bit. --- src/intel/Makefile.sources| 1 + src/intel/compiler/brw_nir.c | 2 +

[Mesa-dev] [PATCH 07/11] intel/compiler: implement nir_instr_type_load_const for 16-bit constants

From: Jose Maria Casanova Crespo --- src/intel/compiler/brw_fs_nir.cpp | 5 + 1 file changed, 5 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index ad31f7c82dc..822a1ac4227 100644 ---

[Mesa-dev] [PATCH 04/11] intel/compiler: implement conversion between float/int 16-bit types

--- src/intel/compiler/brw_fs_nir.cpp | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/compiler/brw_fs_nir.cpp b/src/intel/compiler/brw_fs_nir.cpp index 5e0dd37eefd..5c414e45b61 100644 --- a/src/intel/compiler/brw_fs_nir.cpp +++ b/src/intel/compiler/brw_fs_nir.cpp @@ -791,10

[Mesa-dev] [PATCH 03/11] i965/compiler: handle conversion to smaller type in the lowering pass for that

The lowering pass was specialized to act on 64-bit to 32-bit conversions only, but the implementation is valid for other cases. --- src/intel/compiler/brw_fs_lower_conversions.cpp | 5 - src/intel/compiler/brw_fs_nir.cpp | 14 +++--- 2 files changed, 7 insertions(+), 12

Re: [Mesa-dev] [PATCH] i965: Remove brw_bo_alloc_tiled_2d from intel_detect_swizzling.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2018-04-10 at 01:33 -0700, Kenneth Graunke wrote: > I'd like to drop this pre-isl function. This drops one of the two > uses. > --- > src/mesa/drivers/dri/i965/intel_screen.c | 14 -- > 1 file changed

Re: [Mesa-dev] [PATCH] intel: compiler: silence compiler warning

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2018-04-03 at 15:41 +0100, Lionel Landwerlin wrote: > ../src/intel/compiler/brw_reg.h: In function ‘bool > brw_regs_negative_equal(const brw_reg*, const brw_reg*)’: > ../src/intel/compiler/brw_reg.h:305:1: warning: cont

[Mesa-dev] [PATCH v2] compiler/spirv: set is_shadow for depth comparitor sampling opcodes

From the SPIR-V spec, OpTypeImage: "Depth is whether or not this image is a depth image. (Note that whether or not depth comparisons are actually done is a property of the sampling opcode, not of this type declaration.)" The sampling opcodes that specify depth comparisons are

Re: [Mesa-dev] [PATCH] compiler/spirv: set is_shadow for depth comparitor sampling opcodes

On Mon, 2018-04-02 at 09:31 -0700, Jason Ekstrand wrote: > > On April 2, 2018 04:04:49 Iago Toral Quiroga <ito...@igalia.com> > wrote: > > From the SPIR-V spec, OpTypeImage: > > "Depth is whether or not this image is a depth image. (Note that > whether or not

[Mesa-dev] [PATCH] compiler/spirv: set is_shadow for depth comparitor sampling opcodes

From the SPIR-V spec, OpTypeImage: "Depth is whether or not this image is a depth image. (Note that whether or not depth comparisons are actually done is a property of the sampling opcode, not of this type declaration.)" OpImageSample{Proj}Dref{Explicit,Implicit}Lod sampling opcodes always do a

Re: [Mesa-dev] [PATCH 1/2] compiler/nir: add a is_image_sample_dref flag to texture instructions

st fine to do this in general and it saves us from the hassle of adding a new flag. I guess we can always add the new flag if someone hits a case that needs to differentiate both scenarios anyway. I'll send a new patch for review soon if Jenkins doesn't find any issues. Iago > On March 28, 2018 02:33:50 Ia

[Mesa-dev] [PATCH 2/2] compiler/spirv: set is_image_sample_dref when required

Fixes crashes in: dEQP-VK.spirv_assembly.instruction.graphics.image_sampler.depth_property.* --- src/compiler/spirv/spirv_to_nir.c | 4 1 file changed, 4 insertions(+) diff --git a/src/compiler/spirv/spirv_to_nir.c b/src/compiler/spirv/spirv_to_nir.c index 7888e1b746..719e74c386 100644 ---

[Mesa-dev] [PATCH 1/2] compiler/nir: add a is_image_sample_dref flag to texture instructions

So we can recognize image sampling instructions that involve a depth comparison against a reference, such as SPIR-V's OpImageSample{Proj}Dref{Explicit,Implicit}Lod and we can acknowledge that they return a single scalar value instead of a vec4. --- src/compiler/nir/nir.h | 9 +

Re: [Mesa-dev] [PATCH v5 1/2] anv/cmd_buffer: consider multiview masks for tracking pending clear aspects

On Tue, 2018-03-27 at 09:06 -0700, Jason Ekstrand wrote: > I'm sorry I've been so incredibly out-to-lunch on reviewing this. :-( > > On Tue, Mar 27, 2018 at 12:53 AM, Iago Toral Quiroga <itoral@igalia.c > om> wrote: > > When multiview is active a subpass clear

[Mesa-dev] [PATCH v5 1/2] anv/cmd_buffer: consider multiview masks for tracking pending clear aspects

When multiview is active a subpass clear may only clear a subset of the attachment layers. Other subpasses in the same render pass may also clear too and we want to honor those clears as well, however, we need to ensure that we only clear a layer once, on the first subpass that uses a particular

[Mesa-dev] [PATCH v5 2/2] anv/cmd_buffer: honor pending clear views for depth/stencil attachments

v2: rebased on top of subpass rework. v3: rebased v4: - rebased - reset pending clear views in one go rather one bit at a time (Caio) --- src/intel/vulkan/genX_cmd_buffer.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH v4 1/2] anv/cmd_buffer: consider multiview masks for tracking pending clear aspects

Hi Jason, can you have a look at these two? We have some tests failing because of this. Iago On Wed, 2018-03-07 at 10:33 +0100, Iago Toral wrote: > This patches are still waiting for review. > > On Wed, 2018-02-28 at 09:57 +0100, Iago Toral Quiroga wrote: > > When multiview is a

Re: [Mesa-dev] [PATCH 1/2] anv/entrypoints: dispatches to VkQueue are device-level

t; On Mon, Mar 12, 2018 at 1:40 AM, Iago Toral Quiroga <ito...@igalia.co > m> wrote: > > --- > > > > src/intel/vulkan/anv_entrypoints_gen.py | 2 +- > > > > 1 file changed, 1 insertion(+), 1 deletion(-) > > > > > > > > dif

[Mesa-dev] [PATCH v3 2/2] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

af5f2322d0c64 addressed this for extension commands, but the spec mandates this behavior also for core API commands. From the Vulkan spec, Table 2. vkGetDeviceProcAddr behavior: device pnamereturn -- (..)

[Mesa-dev] [PATCH v3 1/2] anv/entrypoints: dispatches to VkQueue are device-level

v2: - Add trampoline functions (Jason) - Add an assertion for unhandled trampoline cases --- src/intel/vulkan/anv_entrypoints_gen.py | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/intel/vulkan/anv_entrypoints_gen.py b/src/intel/vulkan/anv_entrypoints_gen.py

Re: [Mesa-dev] [PATCH 2/2] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

On Mon, 2018-03-12 at 07:37 -0700, Jason Ekstrand wrote: > On Mon, Mar 12, 2018 at 1:40 AM, Iago Toral Quiroga <ito...@igalia.co > m> wrote: > > af5f2322d0c64 addressed this for extension commands, but the spec > > mandates > > > > this behavior also for cor

[Mesa-dev] [PATCH 2/2] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

af5f2322d0c64 addressed this for extension commands, but the spec mandates this behavior also for core API commands. From the Vulkan spec, Table 2. vkGetDeviceProcAddr behavior: device pnamereturn -- (..)

[Mesa-dev] [PATCH 1/2] anv/entrypoints: dispatches to VkQueue are device-level

--- src/intel/vulkan/anv_entrypoints_gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_entrypoints_gen.py b/src/intel/vulkan/anv_entrypoints_gen.py index 485c6cfe8d..27f1aa 100644 --- a/src/intel/vulkan/anv_entrypoints_gen.py +++

Re: [Mesa-dev] [PATCH 00/56] anv: Add support for Vulkan 1.1

o quite a few patches in here to the entrypoints > > generator > > > > and some of the other generators to handle various things required > > for > > > > reporting a Vulkan version higher than 1.0. In particular, we need > > to > > > > handle name alias

Re: [Mesa-dev] [PATCH v4 1/2] anv/cmd_buffer: consider multiview masks for tracking pending clear aspects

This patches are still waiting for review. On Wed, 2018-02-28 at 09:57 +0100, Iago Toral Quiroga wrote: > When multiview is active a subpass clear may only clear a subset of > the > attachment layers. Other subpasses in the same render pass may also > clear too and we want to honor

Re: [Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

I just noticed that I had missed on of your comments: On Mon, 2018-03-05 at 12:11 +, Emil Velikov wrote: (...) > > > EntrypointParam = namedtuple('EntrypointParam', 'type name decl') > > > > +DeviceChildrenList = ['VkDevice', 'VkQueue', 'VkCommandBuffer' ] > > + > > +def

Re: [Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

On Tue, 2018-03-06 at 14:17 +0100, Iago Toral wrote: > On Tue, 2018-03-06 at 13:05 +, Emil Velikov wrote: > > On 6 March 2018 at 12:26, Iago Toral <ito...@igalia.com> wrote: > > > On Tue, 2018-03-06 at 12:16 +, Emil Velikov wrote: > > > > On 6

Re: [Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

On Tue, 2018-03-06 at 13:05 +, Emil Velikov wrote: > On 6 March 2018 at 12:26, Iago Toral <ito...@igalia.com> wrote: > > On Tue, 2018-03-06 at 12:16 +, Emil Velikov wrote: > > > On 6 March 2018 at 12:09, Iago Toral <ito...@igalia.com> wrote: > > > &g

Re: [Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

On Tue, 2018-03-06 at 12:16 +, Emil Velikov wrote: > On 6 March 2018 at 12:09, Iago Toral <ito...@igalia.com> wrote: > > On Tue, 2018-03-06 at 11:21 +, Emil Velikov wrote: > > > On 6 March 2018 at 09:57, Bas Nieuwenhuizen <ba...@chromium.org> > > >

Re: [Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

On Tue, 2018-03-06 at 11:21 +, Emil Velikov wrote: > On 6 March 2018 at 09:57, Bas Nieuwenhuizen <ba...@chromium.org> > wrote: > > > > > > On Tue, Mar 6, 2018 at 8:02 AM, Iago Toral <ito...@igalia.com> > > wrote: > > > > > > On Mo

Re: [Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

ption exactly? Right now we report NULL for these from vkGetDeviceProcAddr which is the right thing to do. > Bas, you might want to port these over? > > On 5 March 2018 at 10:46, Iago Toral Quiroga <ito...@igalia.com> > wrote: > > af5f2322d0c64 addressed this for exten

[Mesa-dev] [PATCH] anv/entrypoints: VkGetDeviceProcAddr returns NULL for core instance commands

af5f2322d0c64 addressed this for extension commands, but the spec mandates this behavior also for core API commands. From the Vulkan spec, Table 2. vkGetDeviceProcAddr behavior: device pnamereturn -- (..)

Re: [Mesa-dev] [PATCH] intel: Drop program size pointer from vec4/fs assembly getters.

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2018-02-28 at 15:11 -0800, Kenneth Graunke wrote: > These days, we're just passing a pointer to a prog_data field, which > we already have access to. We can just use it directly. > > (In the past, it was a pointer t

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

On Wed, 2018-02-28 at 15:39 -0800, Kenneth Graunke wrote: > On Monday, February 26, 2018 11:02:08 PM PST Iago Toral Quiroga > wrote: > > In 16631ca30ea6 we fixed gen9 active components to account for > > padded > > inputs in the URB, which we can have with SSO programs.

[Mesa-dev] [PATCH v4 2/2] anv/cmd_buffer: honor pending clear views for depth/stencil attachments

v2: rebased on top of subpass rework. v3: rebased --- src/intel/vulkan/genX_cmd_buffer.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index c422ec8e1a..cf02c207dc 100644 ---

[Mesa-dev] [PATCH v4 1/2] anv/cmd_buffer: consider multiview masks for tracking pending clear aspects

When multiview is active a subpass clear may only clear a subset of the attachment layers. Other subpasses in the same render pass may also clear too and we want to honor those clears as well, however, we need to ensure that we only clear a layer once, on the first subpass that uses a particular

Re: [Mesa-dev] [RFC 1/2] spirv: add/hookup SpvCapabilityStencilExportEXT

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Sun, 2018-02-11 at 18:26 -0800, Gustavo Lima Chaves wrote: > --- > src/compiler/shader_info.h | 1 + > src/compiler/spirv/spirv_to_nir.c | 4 > src/compiler/spirv/vtn_variables.c | 4 > 3 files

Re: [Mesa-dev] [PATCH v4] anv: enable VK_EXT_shader_stencil_export

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2018-02-27 at 22:34 -0800, Gustavo Lima Chaves wrote: > v2: > An attempt to support SpvExecutionModeStencilRefReplacingEXT's > behavior > also follows, with the interpretation to said mode being we prevent >

Re: [Mesa-dev] [RFC 2/2] anv: enable VK_EXT_shader_viewport_index_layer

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> However, I think we should not push this until we have testing coverage for using gl_Layer from Vertex and TessEval shaders. For now you only submitted a test for gl_ViewportIndex to CTS right? Iago On Fri, 2018-02-23 at 14:09 -0800

Re: [Mesa-dev] [PATCH v3 1/2] spirv: Add SpvCapabilityShaderViewportIndexLayerEXT

This patch is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Fri, 2018-02-23 at 14:09 -0800, Caio Marcelo de Oliveira Filho wrote: > This capability allows gl_ViewportIndex and gl_Layer to also be used > as outputs in Vertex and Tesselation shaders. > > v2

Re: [Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

Can someone review this patch? The bug if fixes is blocking the 18.0 release. Iago On Tue, 2018-02-27 at 08:02 +0100, Iago Toral Quiroga wrote: > In 16631ca30ea6 we fixed gen9 active components to account for padded > inputs in the URB, which we can have with SSO programs. To do that, >

[Mesa-dev] [PATCH v2] i965/sbe: fix number of inputs for active components

In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry.

[Mesa-dev] [PATCH] i965/sbe: fix number of inputs for active components

In 16631ca30ea6 we fixed gen9 active components to account for padded inputs in the URB, which we can have with SSO programs. To do that, instead of going through the bitfield of inputs (which doesn't include padding information), we compute the number of inputs from the size of the URB entry.

Re: [Mesa-dev] [PATCH v3] anv: enable VK_EXT_shader_stencil_export

On Thu, 2018-02-22 at 11:22 -0800, Gustavo Lima Chaves wrote: > v2: > An attempt to support SpvExecutionModeStencilRefReplacingEXT's > behavior > also follows, with the interpretation to said mode being we prevent > writes to the built-in FragStencilRefEXT variable when the execution > mode isn't

Re: [Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

On Wed, 2018-02-21 at 09:33 -0800, Matt Turner wrote: > On Wed, Feb 21, 2018 at 2:05 AM, Iago Toral <ito...@igalia.com> > wrote: > > On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote: > > > Gen11 does not support DF, Q, UQ types in hardware. As a result, > >

Re: [Mesa-dev] [PATCH v4] anv/blorp: multisample resolve all attachment layers

On Wed, 2018-02-21 at 09:58 -0800, Nanley Chery wrote: > On Wed, Feb 21, 2018 at 09:18:49AM +0100, Iago Toral Quiroga wrote: > > We were only resolving the first. > > > > v2: > > - Do not require that the number of layers on dst and src are an > > exact matc

Re: [Mesa-dev] [PATCH] nir: remove old assert

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Wed, 2018-02-21 at 14:42 +1100, Timothy Arceri wrote: > This was originally intended to make sure the remap location > was not -1. However the code has changed alot since then, > the location is now never set to -1 and

Re: [Mesa-dev] [PATCH 03/17] intel: Disable 64-bit extensions on platforms without 64-bit types

On Tue, 2018-02-20 at 21:15 -0800, Matt Turner wrote: > Gen11 does not support DF, Q, UQ types in hardware. As a result, we > have > to disable some GL extensions until they can be reimplemented. > --- > src/intel/common/gen_device_info.c | 3 +++ > src/intel/common/gen_device_info.h

[Mesa-dev] [PATCH v3 2/2] anv/cmd_buffer: honor pending clear views for depth/stencil attachments

v2: - rebased on top of subpass rework. --- src/intel/vulkan/genX_cmd_buffer.c | 22 +- 1 file changed, 21 insertions(+), 1 deletion(-) diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c index a9e5b2e78c..010b52c10a 100644 ---

[Mesa-dev] [PATCH v3 1/2] anv/cmd_buffer: consider multiview masks for tracking pending clear aspects

When multiview is active a subpass clear may only clear a subset of the attachment layers. Other subpasses in the same render pass may also clear too and we want to honor those clears as well, however, we need to ensure that we only clear a layer once, on the first subpass that uses a particular

[Mesa-dev] [PATCH v4] anv/blorp: multisample resolve all attachment layers

We were only resolving the first. v2: - Do not require that the number of layers on dst and src are an exact match, it is okay if the dst has more layers so long as it has at least the same that we are going to resolve. - Do not always resolve array_len layers, we should resolve

Re: [Mesa-dev] [PATCH] i965/vec4: use a temp register to compute offsets for pull loads

Yes, I agree, thanks for bringing it up. Iago On Tue, 2018-02-20 at 16:38 +0200, Andres Gomez wrote: > Iago, this looks like a good candidate to nominate for inclusion in > the > 17.3 stable queue. > > What do you think? > > On Wed, 2017-11-29 at 11:49 +0100, Iago Toral

Re: [Mesa-dev] [PATCH v3] anv/blorp: multisample resolve all attachment layers

100, Iago Toral Quiroga wrote: > > We were only resolving the first. > > > > v2: > > - Do not require that the number of layers on dst and src are an > > exact match, it is okay if the dst has more layers so long as > > it has at least the same t

Re: [Mesa-dev] [PATCH 1/7] nir: add bindless to nir data

This patch is: Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Tue, 2018-02-20 at 14:42 +1100, Timothy Arceri wrote: > --- > src/compiler/glsl/glsl_to_nir.cpp | 1 + > src/compiler/nir/nir.h| 6 ++ > 2 files changed, 7 insertions(+) > > diff -

Re: [Mesa-dev] [PATCH] glsl: Parse 'layout' as a token with advanced blending or bindless

Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> On Mon, 2018-02-19 at 21:28 -0800, Kenneth Graunke wrote: > Both KHR_blend_equation_advanced and ARB_bindless_texture provide > layout qualifiers, and are exposed in compatibility contexts. We > need to parse the layout quali

[Mesa-dev] [PATCH] anv/entrypoints: make vkGetDeviceProcAddr return NULL for instance commands

The Vulkan working group has recently clarified that this is the intended behavior and accepted spec language changes to make this clear. --- src/intel/vulkan/anv_entrypoints_gen.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/vulkan/anv_entrypoints_gen.py

Re: [Mesa-dev] [PATCH v3 00/18] Rework subpass clears and transitions

Hi Jason, I have just noticed that this series also conflicts with the new version of the multiview clearing series I have just sent, I guess we should wait until this lands first? Iago On Wed, 2018-02-14 at 12:16 -0800, Jason Ekstrand wrote: > This is another version of my patch series to

[Mesa-dev] [PATCH v2 2/3] anv/blorp: honor pending clear views in clear_depth_stencil_attachment

We can call this for both subpass load clears and VkCmdClearAttachments. In the former case, when multiview is active, we need to honor the mask of pending clear views so we don't clear layers that have already been cleared by a previous subpass, just like we do for subpass load color clears. ---

[Mesa-dev] [PATCH v2 3/3] anv/blorp: do not clear with hiz if we have more than one layer

blorp_gen8_hiz_clear_attachments only clears the first layer. v2: - do this in all cases, not just when multiview is involved. - rebased on top of fast-clear rework. --- src/intel/vulkan/anv_blorp.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/intel/vulkan/anv_blorp.c

[Mesa-dev] [PATCH v2 1/3] anv/blorp: consider multiview and view masks for tracking pending clear aspects

When multiview is active a subpass clear may only clear a subset of the attachment layers. Other subpasses in the same render pass may also clear too and we want to honor those clears as well, however, we need to ensure that we only clear a layer once, on the first subpass that uses a particular

[Mesa-dev] [PATCH v3] anv/blorp: multisample resolve all attachment layers

We were only resolving the first. v2: - Do not require that the number of layers on dst and src are an exact match, it is okay if the dst has more layers so long as it has at least the same that we are going to resolve. - Do not always resolve array_len layers, we should resolve

Re: [Mesa-dev] [PATCH v2] anv/blorp: multisample resolve all attachment layers

On Thu, 2018-02-15 at 09:24 +0100, Iago Toral Quiroga wrote: > We were only resolving the first. > > v2: > - Do not require that the number of layers on dst and src are an > exact match, it is okay if the dst has more layers so long as > it has at least the same

[Mesa-dev] [PATCH v2] anv/blorp: multisample resolve all attachment layers

We were only resolving the first. v2: - Do not require that the number of layers on dst and src are an exact match, it is okay if the dst has more layers so long as it has at least the same that we are going to resolve. - Do not always resolve array_len layers, we should resolve

[Mesa-dev] [PATCH] anv/blorp: multisample resolve all attachment layers

We were only resolving the first. Fixes new CTS tests for multisampled layered rendering: dEQP-VK.renderpass.multisample_resolve.layers_* --- src/intel/vulkan/anv_blorp.c | 29 ++--- 1 file changed, 18 insertions(+), 11 deletions(-) diff --git

Re: [Mesa-dev] [PATCH 1/2] spirv: Add SpvCapabilityShaderViewportIndexLayerEXT

On Fri, 2018-02-09 at 09:08 +0100, Iago Toral wrote: > On Sat, 2018-01-27 at 18:58 -0800, Caio Marcelo de Oliveira Filho > wrote: > > --- > > > > In the last chunk of the diff, should accepting stage of vertex > > shader > > should be conditioned on shader_vi

Re: [Mesa-dev] [PATCH 1/2] spirv: Add SpvCapabilityShaderViewportIndexLayerEXT

ort_index_layer is supported, but looking at the code, if we make it conditional on shader_viewport_index_layer it should suffice, since in that case if the implementation doesn't support it we will hit the vtn_fail fallback and report the error. With that change, this patch is: Reviewed-by: Iago Tor

Re: [Mesa-dev] [PATCH] i965/nir: do int64 lowering before optimization

On Sun, 2018-02-04 at 14:40 -0500, Connor Abbott wrote: > On Mon, Dec 11, 2017 at 11:01 AM, Jason Ekstrand <ja...@jlekstrand.ne > t> wrote: > > On Mon, Dec 11, 2017 at 12:55 AM, Iago Toral <ito...@igalia.com> > > wrote: > > > > > > This didn't get

Re: [Mesa-dev] [PATCH] i965/nir: do int64 lowering before optimization

On Sun, 2018-02-04 at 10:58 -0800, Matt Turner wrote: > On Wed, Dec 13, 2017 at 11:21 PM, Iago Toral <ito...@igalia.com> > wrote: > > On Tue, 2017-12-12 at 08:20 +0100, Iago Toral wrote: > > > > On Mon, 2017-12-11 at 08:01 -0800, Jason Ekstrand wrote: > >

[Mesa-dev] [PATCH v2] i965/nir: do int64 lowering before optimization

Otherwise loop unrolling will fail to see the actual cost of the unrolling operations when the loop body contains 64-bit integer instructions, and very specially when the divmod64 lowering applies, since its lowering is quite expensive. Without this change, some in-development CTS tests for int64

[Mesa-dev] [PATCH] anv/device: initialize the list of enabled extensions properly

The loop goes through the list of enabled extensions marking them as enabled in the list, but this relies on every other extension being initialized to false by default. This bug would make us, for example, advertise certain device extension entry points as available even when the corresponding

Re: [Mesa-dev] [PATCH] spirv: split constant initializers on in/out structs

This is still unreviewed. Jason, since you reviewed the other patch I sent related to output initializers, could you have a look at this one too? Iago On Tue, 2018-01-23 at 14:11 +0100, Iago Toral Quiroga wrote: > The SPIR-V parser splits in/out struct variables and creates > a se

Re: [Mesa-dev] [PATCH 1/2] intel/compiler: fix first_component for 64-bit types on vertex inputs

This series is still waiting for a review, any takers? On Fri, 2018-01-19 at 09:17 +0100, Iago Toral Quiroga wrote: > Divide it by two as we do for other stages. This is because the > component layout qualifier is always in 32-bit units. > > Fixes issues in a new CTS test (still WIP)

Re: [Mesa-dev] [PATCH] anv/cmd_buffer: Re-emit the pipeline at every subpass

r since apps need to bind a new pipeline at each subpass anyway and that will dirty this state. It would be redundant for most cases but I guess it does't hurt. Reviewed-by: Iago Toral Quiroga <ito...@igalia.com> Iago > /* Perform transitions to the subpass layout before any writes &

<    1   2   3   4   5   6   7   8   9   10   >