[Mesa-dev] [PATCH] anv/cmd_buffer: Reuse gen8 Cmd{Set, Reset}Event on gen7

From: Ville Syrjälä Modern DXVK requires event support [1], but looks like it only uses vkCmdSetEvent() + vkGetEventStatus(). So we can just borrow the relevant code from gen8, leaving CmdWaitEvents still unimplemented. [1]

[Mesa-dev] [PATCH] meson: Fix build for egl platform_x11 with dri3

From: Ville Syrjälä platform_x11 with dri3 needs inc_loader. In file included from ../src/egl/drivers/dri2/platform_x11_dri3.c:35:0: ../src/egl/drivers/dri2/egl_dri2.h:41:32: fatal error: loader_dri3_helper.h: No such file or directory In file included from

[Mesa-dev] [PATCH 2/2] meson: Build i915

From: Ville Syrjälä Build i915 with meson. More or less copied from i965, with all the unneeded cruft removed, and the libdrm_intel dependency added. Cc: Dylan Baker Cc: Eric Anholt Signed-off-by: Ville Syrjälä

[Mesa-dev] [PATCH 1/2] meson: Fix xf86vm dep

From: Ville Syrjälä The pkg-config file is called xxf86vm.pc not xf86vm.pc. Cc: Dylan Baker Cc: Eric Anholt Signed-off-by: Ville Syrjälä --- meson.build | 2 +- 1 file changed, 1

[Mesa-dev] [PATCH] meta: Fix BlitFramebuffer temp texture setup

From: Ville Syrjälä Pass the correct src coordinates to CopyTexSubImage() when creating the temporary texture, and also take care to adjust flipX/Y if the original src coordinates were flipped compared to the new temporary texture src coordinates. This fixes all

[Mesa-dev] [PATCH] i915: Fix gl_Fragcoord interpolation

From: Ville Syrjälä gl_FragCoord contains the window coordinates so it seems to me that we should not use perspective correct interpolation for it. At least now I get similar output as i965/swrast/llvmpipe produce. This fixes

[Mesa-dev] [PATCH] i915: Always emit W on gen3

From: Ville Syrjälä Unlike the older gen2 hardware, gen3 performs perspective correct interpolation even for the primary/secondary colors. To do that it naturally needs us to emit W for the vertices. Currently we emit W only when at least one texture coordinate

[Mesa-dev] [PATCH] i915: Fix wpos_tex vs. -1 comparison

From: Ville Syrjälä wpos_tex used to be a GLuint so assinging -1 to it and later comparing with -1 worked correctly, but commit c349031c27b7 ("i915: Fix texcoord vs. varying collision in fragment programs") changed wpos_tex to uint8_t and hence broke the

[Mesa-dev] [PATCH] configure.ac: Refuse to build Vulkan without DRI3

From: Ville Syrjälä Trying to build the Vulkan WSI code results in a failure without DRI3. Make configure check that DRI3 is available before trying to build the Vulkan drivers. Signed-off-by: Ville Syrjälä --- configure.ac | 4

[Mesa-dev] [PATCH] anv: Prefer in-tree headers to out-of-tree headers

From: Ville Syrjälä Set the include paths to consider in-tree headers before out-of-tree headers. Avoids the build failing due to stale headers being present in $prefix. Previosuly 'make -ki install' or something similar was required to update the out-of-tree

[Mesa-dev] [PATCH] anv/formats: Fix build on gcc-4 and earlier

From: Ville Syrjälä gcc-4 and earlier don't allow compound literals where a constant is required in -std=c99/gnu99 mode, so we can't use ISL_SWIZZLE() when populating the anv_formats[] array. There are a few ways around it: First one would be -std=c89/gnu89, but

[Mesa-dev] [PATCH 2/2] i965: Actually enable L3 caching for everything on CHV

From: Ville Syrjälä ville.syrj...@linux.intel.com Looks like CHV MOCS behaves a bit differently than BDW MOCS. On BDW the target cache bits can be used to enable L3 caching regardless if how the other bits are set up to select the UC/WT/WB caching mode for LLC/eLLC. On CHV however it appears that

[Mesa-dev] [PATCH 1/2] i965: House MOCS settings in brw_context/brw_device_info

From: Ville Syrjälä ville.syrj...@linux.intel.com The layout of the MOCS bits has kept changing for each new platform. Instead of adding platform checks all over the place just store the MOCS settings in the device info and context. Currently MOCS is only ever set up in two ways: either let the

[Mesa-dev] [PATCH] i965: Add marketing names for CHV

From: Ville Syrjälä ville.syrj...@linux.intel.com All CHV devices will be branded as Intel(r) HD Graphics. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- include/pci_ids/i965_pci_ids.h | 8 1 file changed, 4 insertions(+), 4 deletions(-) diff --git

[Mesa-dev] [PATCH] i965/disasm: Print the type after the swizzle also for 3src src operands

From: Ville Syrjälä ville.syrj...@linux.intel.com The disassembly currently has the swizzle after the type for 3src source operands, and the other way around for 2src. Flip the type and swizzle around for 3src so that the output matches 2src. Signed-off-by: Ville Syrjälä

[Mesa-dev] [PATCH 19/20] i915: Fix culling with user fbos on gen2

From: Ville Syrjälä ville.syrj...@linux.intel.com Flip the cull bits when rendering to a user fbo on gen2. This was already done on gen3 (since before git history starts) but was missing from the gen2 code. Fixes rendering of the driver+kart model in supertuxkart kart selection screen.

[Mesa-dev] [PATCH 20/20] i915: Fix texcoord vs. varying collision in fragment programs

From: Ville Syrjälä ville.syrj...@linux.intel.com i915 fragment programs utilize the texture coordinate registers for both texture coordinates and varyings. Unfortunately the code doesn't check if the same index might be in use for both. It just naively uses the index to pick a texture unit,

[Mesa-dev] [PATCH 15/20] i915: Enable intel_render path for points

From: Ville Syrjälä ville.syrj...@linux.intel.com The sub-pixel adjustment for points was killed off in commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c Author: Xiang, Haihao haihao.xi...@intel.com Date: Wed Jan 2 11:38:51 2008 +0800 i915: Needn't adjust pixel centers. fix #12944 so if

[Mesa-dev] [PATCH 14/20] i915: Use COPY_DWORDS for points

From: Ville Syrjälä ville.syrj...@linux.intel.com The sub-pixel adjustment for points was killed off in commit 60d762aa625095a8c1f9597d8530bb5a6fa61b4c Author: Xiang, Haihao haihao.xi...@intel.com Date: Wed Jan 2 11:38:51 2008 +0800 i915: Needn't adjust pixel centers. fix #12944 so we

[Mesa-dev] [PATCH 07/20] t_dd_dmatmp: Make the render_tab[]s const

From: Ville Syrjälä ville.syrj...@linux.intel.com These tables hold function pointers and they never change so make them const. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/tnl_dd/t_dd_dmatmp.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

[Mesa-dev] [PATCH 16/20] i915: Adjust line size limits

From: Ville Syrjälä ville.syrj...@linux.intel.com The hardware can draw lines 0.5 to 7.5 pixels wide. Adjust the limits to 1.0-7.0. The old limits seems to be from the era when i915 and i965 were sharing this code. Not really sure if 1.0-7.0 is correct. Maybe it could be 0.5.7.5 as those are the

[Mesa-dev] [PATCH 18/20] i915: Drop broken front_buffer_reading/drawing optimization

From: Ville Syrjälä ville.syrj...@linux.intel.com Bring the following commit over to i915: commit ec542d74578bbef6b55125dd6aba1dc7f5079e65 Author: Eric Anholt e...@anholt.net Date: Mon Mar 3 10:43:10 2014 -0800 i965: Drop broken front_buffer_reading/drawing optimization. Not sure if it

[Mesa-dev] [PATCH 13/20] i915: Use c99 initializers for primitive arrays

From: Ville Syrjälä ville.syrj...@linux.intel.com Using c99 initializers for the primitive arrays makes things more readable. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i915/intel_render.c | 60

[Mesa-dev] [PATCH 11/20] i915: Use _tnl_RenderClippedPolygon and _tnl_RenderClippedLine

From: Ville Syrjälä ville.syrj...@linux.intel.com _tnl_RenderClippedPolygon and _tnl_RenderClippedLine already do most of what we want so use them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i915/intel_tris.c | 19 ++- 1 file changed, 2

[Mesa-dev] [PATCH 12/20] i915: Make hw_prim[] const

From: Ville Syrjälä ville.syrj...@linux.intel.com The table used to map the GL primitive to the hw primitive never changes so make it const. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i915/intel_render.c | 2 +- 1 file changed, 1 insertion(+), 1

[Mesa-dev] [PATCH 17/20] i915: Remember to call intel_prepare_render() before blitting

From: Ville Syrjälä ville.syrj...@linux.intel.com Bring over the following fix from i965: commit fb3d62fe3d4fc40ba4ad9804d8b6f451316c9ae2 Author: Kenneth Graunke kenn...@whitecape.org Date: Tue Aug 6 14:36:09 2013 -0700 i965: Remember to call intel_prepare_render() before blitting.

[Mesa-dev] [PATCH 04/20] t_dd_dmatmp: Check provoking vertex convention when rendering quads

From: Ville Syrjälä ville.syrj...@linux.intel.com When drawing quads using triangles we need to be careful to make the provoking vertices match when flat shading. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/tnl_dd/t_dd_dmatmp.h | 12 +--- 1 file changed, 9

[Mesa-dev] [PATCH 03/20] t_dd_dmatmp: Disallow flat shading when rendering quad strips via tri strips

From: Ville Syrjälä ville.syrj...@linux.intel.com When rendering quad strips via tri strips we can't get the provoking vertex right, so disallow flat shading. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/tnl_dd/t_dd_dmatmp.h | 4 ++-- 1 file changed, 2 insertions(+),

[Mesa-dev] [PATCH 06/20] t_dd_dmatmp: Fix render_quad_strip_elts

From: Ville Syrjälä ville.syrj...@linux.intel.com Split the tri vs. tristrip paths in render_quad_strip_elts apart and add the appropriate smooth vs. flat shading and provoking vertex checks. Add the same checks to validate_render to make sure we don't end up there under the wrong circumstances.

[Mesa-dev] [PATCH 08/20] i915: Fix collision between I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0)

From: Ville Syrjälä ville.syrj...@linux.intel.com I830_UPLOAD_RASTER_RULES and I830_UPLOAD_TEX(0) are trying to occupy the same bit. Move the texture bits upwards a bit to make room for I830_UPLOAD_RASTER_RULES. Now the driver will actually upload the raster rules which is rather important to

[Mesa-dev] [PATCH 09/20] i915: Handle provoking vertex in intelFastRenderClippedPoly()

From: Ville Syrjälä ville.syrj...@linux.intel.com intelFastRenderClippedPoly() renders the polygon using triangles. For polygons the provoking vertex is always the first one, and currently this function assumes that the provoking vertex for triangles is the last one. In case the user changed the

[Mesa-dev] [PATCH 10/20] i915: Fix t_vb_rendertmp.h's provoking vertex handywork

From: Ville Syrjälä ville.syrj...@linux.intel.com t_vb_rendertmp.h reorder the vertices passed to the driver based on the provoking vertex convention. The last vertex passed is always the provoking vertex. For us however that's a bit bad since the hardware itself handles the provoking vertex.

[Mesa-dev] [PATCH 02/20] t_dd_dmatmp: Allow flat shaded polygons with tri fans

From: Ville Syrjälä ville.syrj...@linux.intel.com We can allow rendering flat shaded polygons using tri fans if we check the provoking vertex convention. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/tnl_dd/t_dd_dmatmp.h | 12 +--- 1 file changed, 9

[Mesa-dev] [PATCH 05/20] t_dd_dmatmp: Call render_tri_fan_elts from render_poly_elts

From: Ville Syrjälä ville.syrj...@linux.intel.com Calling render_tri_fan_verts() from render_poly_elts() doesn't seem sane. I presume the intention was to call render_tri_fan_elts() instead. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/tnl_dd/t_dd_dmatmp.h | 2 +- 1

[Mesa-dev] [PATCH 01/20] t_dd_dmatmp: Kill the paths rendering quads/quad strips via indexed vertices

From: Ville Syrjälä ville.syrj...@linux.intel.com No driver supports elts currently, and these make the validate_render code a bit hard to follow. Just kill them. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/tnl_dd/t_dd_dmatmp.h | 133

[Mesa-dev] [PATCH 00/20] i915: Pile of fixes and cleanups

From: Ville Syrjälä ville.syrj...@linux.intel.com I've had some of these i915 patches lying around for half a year or more, so I figured it's time to post them. This series fixes rendering problems in glxgears and supertuxkart. It also fixes a few piglit tests (provoking vertex, and a few

[Mesa-dev] [PATCH] mesa: Fix build errors on x86+sse

From: Ville Syrjälä ville.syrj...@linux.intel.com tnl/t_vertex_sse.c: In function ‘build_vertex_emit’: tnl/t_vertex_sse.c:500:6: error: implicit declaration of function ‘printf’ [-Werror=implicit-function-declaration] printf(Can't emit 1ub %x %x %d\n, a-vertoffset, a[-1].vertoffset,

[Mesa-dev] [PATCH] i965: Fix URB size for CHV

From: Ville Syrjälä ville.syrj...@linux.intel.com Increase the device info .urb.size for CHV to match the default URB size (192kB). Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_device_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

[Mesa-dev] [PATCH 1/3] i965: Fix max_wm_threads for gen8

From: Ville Syrjälä ville.syrj...@linux.intel.com max_wm_threads depends on the GT SKU on gen8. Update the values to match the spec. The max number of threads in 3DSTATE_PS is always programmed to 64 and the hardware internally scales that depending on the GT SKU. So this doesn't change the max

[Mesa-dev] [PATCH 2/3] i965: Fix min_vs_entries for CHV

From: Ville Syrjälä ville.syrj...@linux.intel.com According to BSpec the correct number for min_vs_entries is 34 for CHV. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i965/brw_device_info.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[Mesa-dev] [PATCH 3/3] i965: Fix URB size for gen8

From: Ville Syrjälä ville.syrj...@linux.intel.com Increase the device info .urb.size for BDW GT3 and CHV to match the default URB size for each. Also add all missing platforms (BYT,BDW,CHV) to the comment describing the default URB size in gen7_urb.c. Signed-off-by: Ville Syrjälä

[Mesa-dev] [PATCH] i915: Fix texcoord vs. varying collision in fragment programs

From: Ville Syrjälä ville.syrj...@linux.intel.com i915 fragment programs utilize the texture coordinate registers for both texture coordinates and varyings. Unfortunately the code doesn't check if the same index might be in use for both. It just naively uses the index to pick a texture unit,

[Mesa-dev] [PATCH] kms_flip: Improve the accuracy of out frame time calculation

From: Ville Syrjälä ville.syrj...@linux.intel.com Don't use the rounded vrefresh info to predict the frame duration. Instead calculate if from the clock. --- tests/kms_flip.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/tests/kms_flip.c b/tests/kms_flip.c index

[Mesa-dev] [PATCH 2/2] Use floating point for VTotal when calculating refresh rate

From: Foo Bar f...@bar.com Interlaced modes generally have an odd VTotal, so we lose half a line from VTotal when we divide by two. That causes the final refresh rate to be slightly off. Make VTotal a double to avoid the problem. Signed-off-by: Foo Bar f...@bar.com --- xrandr.c | 2 +- 1 file

[Mesa-dev] [PATCH 1/2] Use more decimal places when printing various rates

From: Foo Bar f...@bar.com Using just one decimal place for dotclock and refresh rates loses quite a bit of information. When dealing with 60Hz and 59.94Hz modes for example it's useful to see at least two decimal places. Also for the dotclock in the same cases three decimal places seems quite a

[Mesa-dev] [PATCH v2 3/9] i915: Use L8A8 instead of I8 to simulate A8 on gen2

From: Ville Syrjälä ville.syrj...@linux.intel.com Gen2 doesn't support the A8 texture format. Currently the driver substitutes it with I8, but that results in incorrect RGB values. Use A8L8 instead. We end up wasting a bit of memory, but at least we should get the correct results. v2: Handle the

[Mesa-dev] [PATCH 0/9] i915: Gen2 texturing fixes and a few random patches

From: Ville Syrjälä ville.syrj...@linux.intel.com I had a few rainy days during my summer vacation so I decided to fix a chromnium-bsu texturing problem that was nagging me for a while now. I ended up fixing a few other things too that I spotted mostly from reading the code. The aniso vs. mip

[Mesa-dev] [PATCH 3/9] i915: Use L8A8 instead of I8 to simulate A8 on gen2

From: Ville Syrjälä ville.syrj...@linux.intel.com Gen2 doesn't support the A8 texture format. Currently the driver substitutes it with I8, but that results in incorrect RGB values. Use A8L8 instead. We end up wasting a bit of memory, but at least we should get the correct results. Bugzilla:

[Mesa-dev] [PATCH 1/9] i915: Only use TEXCOORDTYPE_VECTOR with cube maps on gen2

From: Ville Syrjälä ville.syrj...@linux.intel.com Check that the target is GL_TEXTURE_CUBE_MAP before emitting TEXCOORDTYPE_VECTOR texture coordinates. I'm not sure if the hardware would like CARTESIAN coordinates with cube maps, and as I'm too lazy to find out just emit the VECTOR coordinates

[Mesa-dev] [PATCH 6/9] i915: Kill intel_context::hw_stencil

From: Ville Syrjälä ville.syrj...@linux.intel.com ctx.hw_stencil is not used anywhere so kill it. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i915/intel_context.c | 1 - src/mesa/drivers/dri/i915/intel_context.h | 1 - 2 files changed, 2 deletions(-)

[Mesa-dev] [PATCH 5/9] i915: Accept GL_DEPTH_STENCIL GL_DEPTH_COMPONENT formats for renderbuffers

From: Ville Syrjälä ville.syrj...@linux.intel.com Gen2 doesn't support depth/stencil textures, and since commit c1d4d4999303f9167b20f4e0674b9436e6295cf7 Author: Ville Syrjälä ville.syrj...@linux.intel.com Date: Thu Apr 24 14:11:43 2014 +0300 i915: Don't advertise Z formats in

[Mesa-dev] [PATCH 9/9] i915: Emit 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE

From: Ville Syrjälä ville.syrj...@linux.intel.com According to gen2 BSpec the pipeline must be flushed at least up to the windower before changing the scissor rect enable field. Emitting the 3DSTATE_SCISSOR_RECTANGLE_0 before 3DSTATE_SCISSOR_ENABLE is sufficient to do that. gen3 BSpec no longer

[Mesa-dev] [PATCH 8/9] i915: Don't call _mesa_meta_glsl_Clear() on gen2

From: Ville Syrjälä ville.syrj...@linux.intel.com Gen2 doesn't have fragmnts shaders so we shouldn't be calling _mesa_meta_glsl_Clear() on gen2. Restore the appropriate ARB_fragment_shader check to the clear path which was lost in: commit 94f22fbe787214580a1a13a774114d2650c166cb Author: Tapani

[Mesa-dev] [PATCH 7/9] i915: Protect macro argument for TEXTURE_SET()

From: Ville Syrjälä ville.syrj...@linux.intel.com TEXTURE_SET() is the only register macro that forgets to wrap the argument evaluation in parens. Only simple integers are passed to this macro so there's no bug but sitll it seems prudent to add the parens. Signed-off-by: Ville Syrjälä

[Mesa-dev] [PATCH 4/9] i915: Override mip filter to nearest with aniso

From: Ville Syrjälä ville.syrj...@linux.intel.com gen2 doesn't supporte linear mip filter with anisotropic min/mag filtering. The hardware would automagically downgrade the min/mag filters to linear in such cases, which IMO looks worse than forcing the mip filter to nearest. Signed-off-by: Ville

[Mesa-dev] [PATCH 2/9] i915: Fix GL_DOT3_RGBA a bit

From: Ville Syrjälä ville.syrj...@linux.intel.com The spec says using DOT4 for alpha is undefined unless DOT4 is also used for color. It seems to do the right thing anyway, but better safe than sorry. Also override numAlphaArgs to 2 for DOT4 since that's what it wants. This migth fix something

[Mesa-dev] [PATCH] i915: Fix gen2 texblend setup

From: Ville Syrjälä ville.syrj...@linux.intel.com Fix an off by one in the texture unit walk during texblend setup on gen2. This caused the last enabled texunit to be skipped resulting in totally messed up texturing. This is a regression introduced here: commit

[Mesa-dev] [PATCH 2/3] i915: Don't advertise Z formats in TextureFormatSupported on gen2

From: Ville Syrjälä ville.syrj...@linux.intel.com Gen2 doesn't support texturing from Z formats, so state as much. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com --- src/mesa/drivers/dri/i915/i915_context.c | 28 +++- 1 file changed, 15 insertions(+), 13

[Mesa-dev] [PATCH 0/3] i915/i965: Depth buffer format fixes

From: Ville Syrjälä ville.syrj...@linux.intel.com I was a bit annoyed when chromium-bsu stopped rendering the spinning title text on my gen2 machine. So I bisected it down and found the problem with the renderbuffer code overwriting the selected depth buffer format. This series fixes that

[Mesa-dev] [PATCH 1/3] i915: Fix format of private renderbuffers

From: Ville Syrjälä ville.syrj...@linux.intel.com intel_alloc_renderbuffer_storage() will clobber rb-Format which was already set up by intel_create_renderbuffer(). This causes the driver to potentially create the depth buffer in the wrong format. Long time ago things worked by accident because

[Mesa-dev] [PATCH 3/3] i965: Fix format of private renderbuffers

From: Ville Syrjälä ville.syrj...@linux.intel.com intel_alloc_renderbuffer_storage() will clobber rb-Format which was already set up by intel_create_renderbuffer(). This causes the driver to potentially create the depth buffer in the wrong format. In practice this makes the depth buffer Z24 even

[Mesa-dev] [PATCH] swrast: Fix vertex color in _swsetup_Translate()

From: nick n...@fuel7.com Straightforward fix to properly load dest-color with color data, as opposed to position data as previously implemented. [vsyrjala: I noticed the patch languishing in bugzilla. It looks correct to me so I refreshed it for master. Looks like it's a regression

[Mesa-dev] [PATCH 2/3] i965/gen7: Set MOCS L3 cacheability for IVB/BYT

From: Ville Syrjälä ville.syrj...@linux.intel.com IVB/BYT also has the same L3 cacheability control in MOCS as HSW, so let's make use of it. pts/xonotic and pts/reaction @ 1920x1080 gain ~4% on my IVB GT2. Most other things show less gains/no regressions, except furmark which loses some 10

[Mesa-dev] [PATCH 1/3] i965/hsw: Populate MOCS for STATE_BASE_ADDRESS

From: Ville Syrjälä ville.syrj...@linux.intel.com Juse spotted these unpopulated MOCS fields when comparing the code against BSpec. No idea if this makes any difference anywhere, or if it even makes any sense. Signed-off-by: Ville Syrjälä ville.syrj...@linux.intel.com ---

[Mesa-dev] [PATCH 3/3] i965/gen7: Don't use L3$ for render targets

From: Ville Syrjälä ville.syrj...@linux.intel.com According to HSW Bspec L3$ evictions may land in LLC regardless of LLC MOCS/PTE settings. That means we shouldn't set scanout buffers as L3 cacheable when writing to them. So far I've been unable to observe this phenomenon on my IVB, but better