[Mesa-dev] [PATCH 1/3] egl: Allow creation of per surface out fence

2017-09-15 Thread yogesh . marathe
gzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101655 Signed-off-by: Zhongmin Wu <zhongmin...@intel.com> Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> Reviewed-by: Emil Velikov <emil.veli...@collabora.com> Reviewed-by: Tomasz Figa <tf...@chromium.org> --- s

[Mesa-dev] [PATCH 2/3] egl: Wrap dri3 surface primitive around dri2 egl surface

2017-09-15 Thread yogesh . marathe
From: Yogesh Marathe <yogesh.mara...@intel.com> Originally dri3 egl surface was wrapped around _EGLSurface. To support explicit sync, new variables (e.g. enable_out_fence) were added to dri2_egl_surface. As we reference these new variables we write on to dri3 loader bits. These get toggled

[Mesa-dev] [PATCH 3/3] egl: dri3 changes to support surface primitive wrap around dri2

2017-09-15 Thread yogesh . marathe
From: Yogesh Marathe <yogesh.mara...@intel.com> As base is moved one level down corresponding implementation in dri3 needs a change. Tested with Intel Mesa CI Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> --- src/egl/drivers/dri2/platform_x11_dri3.c | 18 +-

[Mesa-dev] [PATCH v6.2] egl: Allow creation of per surface out fence

2017-08-23 Thread yogesh . marathe
gzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101655 Signed-off-by: Zhongmin Wu <zhongmin...@intel.com> Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> Reviewed-by: Emil Velikov <emil.veli...@collabora.com> Reviewed-by: Tomasz Figa <tf...@chromium.org> --- s

[Mesa-dev] [PATCH v6.2] egl: Allow creation of per surface out fence

2017-08-23 Thread yogesh . marathe
o fini Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101655 Signed-off-by: Zhongmin Wu <zhongmin...@intel.com> Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> Reviewed-by: Emil Velikov <emil.veli...@collabora.com> Reviewed-by: Tomasz Figa <tf...@chromium.org

[Mesa-dev] [PATCH v6.1] egl: Allow creation of per surface out fence

2017-08-18 Thread yogesh . marathe
; Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> --- src/egl/drivers/dri2/egl_dri2.c | 69 + src/egl/drivers/dri2/egl_dri2.h | 9 src/egl/drivers/dri2/platform_android.c | 29 ++-- src/egl/drivers/dri2/platform_

[Mesa-dev] [PATCH v6] egl: Allow creation of per surface out fence

2017-08-08 Thread yogesh . marathe
_fence is set only if fence is supported c) Review comments on function names d) Test with standalone patch, resolves the bug Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101655 Signed-off-by: Zhongmin Wu <zhongmin...@intel.com> Signed-off-by: Yogesh Marathe <yogesh.ma

[Mesa-dev] [PATCH v5 2/2] i965: Queue the buffer with a sync fence for Android OS

2017-08-02 Thread yogesh . marathe
t true or false b) Change get fd to update fd and check for fence c) Commit description updated Signed-off-by: Zhongmin Wu <zhongmin...@intel.com> Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> --- src/egl/drivers/dri2/egl_dri2.c | 57

[Mesa-dev] [PATCH v5 1/2] i965: Return the last fence if the batch buffer is empty

2017-08-02 Thread yogesh . marathe
intel.com> Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> --- src/mesa/drivers/dri/i965/brw_context.c | 5 + src/mesa/drivers/dri/i965/brw_context.h | 1 + src/mesa/drivers/dri/i965/intel_batchbuffer.c | 16 ++-- 3 files changed, 20 insertions(+), 2 deleti

[Mesa-dev] [PATCH V3] i965 : Optimize atom state flag checks

2017-07-20 Thread Yogesh Marathe
it msg corrected Signed-off-by: Aravindan Muthukumar <aravindan.muthuku...@intel.com> Signed-off-by: Yogesh Marathe <yogesh.mara...@intel.com> Tested-by: Asish <as...@intel.com> --- src/mesa/drivers/dri/i965/brw_defines.h | 4 src/mesa/drivers/dri/i965/brw_state_upload.c