Re: [Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

2017-09-30 Thread Marek Olšák
On Sat, Sep 30, 2017 at 4:49 PM, Gert Wollny wrote: > Am Freitag, den 29.09.2017, 16:09 +0200 schrieb Marek Olšák: >> On Fri, Sep 29, 2017 at 3:33 PM, Gert Wollny >> wrote: >> > >> > Am 29.09.2017 14:51 schrieb "Marek Olšák" : >> > >>

Re: [Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

2017-09-30 Thread Gert Wollny
Am Freitag, den 29.09.2017, 16:09 +0200 schrieb Marek Olšák: > On Fri, Sep 29, 2017 at 3:33 PM, Gert Wollny > wrote: > > > > Am 29.09.2017 14:51 schrieb "Marek Olšák" : > > > > > > > > If all requirements are met, UARL isn't emitted and the source > > >

Re: [Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

2017-09-29 Thread Roland Scheidegger
I think it's kind of a pity that there's no "intermediate" step here - I think just about every modern driver doesn't want to see UARL / address reg, but I'd assume not everybody can use _any_ 1d reg for addressing. d3d10 only supports temp registers as addressing operands which looks quite

Re: [Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

2017-09-29 Thread Marek Olšák
On Fri, Sep 29, 2017 at 3:33 PM, Gert Wollny wrote: > > Am 29.09.2017 14:51 schrieb "Marek Olšák" : > >> >> If all requirements are met, UARL isn't emitted and the source operand >> of UARL is folded into the instruction where ADDR would normally be >>

Re: [Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

2017-09-29 Thread Gert Wollny
Am 29.09.2017 14:51 schrieb "Marek Olšák" : > > If all requirements are met, UARL isn't emitted and the source operand > of UARL is folded into the instruction where ADDR would normally be > used. I only skimmed over the patches, but this will need tracking reladdr* in the

[Mesa-dev] [PATCH 00/11] Gallium/RadeonSI: Allow any 1D register as a TGSI address operand

2017-09-29 Thread Marek Olšák
Hi, This series removes the limitation that only ADDR registers are allowed as address operands. Any 1D register can be an address operand (IN, OUT, TEMP, SV, CONST reading from the first buffer slot). Requirements: - The address operand must be integer. - The address operand must be a 1D