From: Kenneth Graunke <kenn...@whitecape.org> Signed-off-by: Chad Versace <c...@chad-versace.us> Signed-off-by: Kenneth Graunke <kenn...@whitecape.org> --- src/mesa/drivers/dri/i965/gen7_clip_state.c | 17 ++++++++++++++ src/mesa/drivers/dri/i965/gen7_misc_state.c | 33 +++++++++++++++++++++----- src/mesa/drivers/dri/i965/gen7_sf_state.c | 13 +++++++++- src/mesa/drivers/dri/i965/gen7_wm_state.c | 26 +++++++++++++++++++++ 4 files changed, 81 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen7_clip_state.c b/src/mesa/drivers/dri/i965/gen7_clip_state.c index c23ba8c..e6c699e 100644 --- a/src/mesa/drivers/dri/i965/gen7_clip_state.c +++ b/src/mesa/drivers/dri/i965/gen7_clip_state.c @@ -36,6 +36,23 @@ upload_clip_state(struct brw_context *brw) uint32_t provoking, userclip; uint32_t dw1 = GEN6_CLIP_STATISTICS_ENABLE; + if (brw->hiz.op) { + /* HiZ operations emit a rectangle primitive, which requires clipping to + * be disabled. From page 10 of the Sandy Bridge PRM Volume 2 Part 1 + * Section 1.3 3D Primitives Overview: + * RECTLIST: + * Either the CLIP unit should be DISABLED, or the CLIP unit's Clip + * Mode should be set to a value other than CLIPMODE_NORMAL. + */ + BEGIN_BATCH(4); + OUT_BATCH(_3DSTATE_CLIP << 16 | (4 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + return; + } + /* _NEW_BUFFERS */ GLboolean render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0; diff --git a/src/mesa/drivers/dri/i965/gen7_misc_state.c b/src/mesa/drivers/dri/i965/gen7_misc_state.c index 7544f96..c045b80 100644 --- a/src/mesa/drivers/dri/i965/gen7_misc_state.c +++ b/src/mesa/drivers/dri/i965/gen7_misc_state.c @@ -66,6 +66,8 @@ static void prepare_depthbuffer(struct brw_context *brw) if (drb) brw_add_validated_bo(brw, drb->region->buffer); + if (drb && drb->region->hiz.region) + brw_add_validated_bo(brw, drb->region->hiz.region->buffer); if (srb) brw_add_validated_bo(brw, srb->region->buffer); } @@ -79,6 +81,7 @@ static void emit_depthbuffer(struct brw_context *brw) /* _NEW_BUFFERS */ struct intel_renderbuffer *drb = intel_get_renderbuffer(fb, BUFFER_DEPTH); struct intel_renderbuffer *srb = intel_get_renderbuffer(fb, BUFFER_STENCIL); + bool has_hiz = intel_framebuffer_has_hiz(fb); /* Gen7 doesn't support packed depth/stencil */ assert(srb == NULL || srb != drb); @@ -122,7 +125,7 @@ static void emit_depthbuffer(struct brw_context *brw) OUT_BATCH(GEN7_3DSTATE_DEPTH_BUFFER << 16 | (7 - 2)); OUT_BATCH(((region->pitch * region->cpp) - 1) | (gen7_depth_format(brw) << 18) | - (0 << 22) /* no HiZ buffer */ | + ((has_hiz & 1) << 22) /* enable HiZ */ | ((srb != NULL && ctx->Stencil.WriteMask != 0) << 27) | ((ctx->Depth.Mask != 0) << 28) | (BRW_SURFACE_2D << 29)); @@ -136,12 +139,28 @@ static void emit_depthbuffer(struct brw_context *brw) ADVANCE_BATCH(); } - BEGIN_BATCH(4); - OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (4 - 2)); - OUT_BATCH(0); - OUT_BATCH(0); - OUT_BATCH(0); - ADVANCE_BATCH(); + if (has_hiz) { + struct intel_hiz_control *hiz = &drb->region->hiz; + assert(hiz->need_resolve != INTEL_HIZ_NEED_HIZ_RESOLVE); + + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH(hiz->region->pitch * hiz->region->cpp - 1); + OUT_RELOC(hiz->region->buffer, + I915_GEM_DOMAIN_RENDER, I915_GEM_DOMAIN_RENDER, + 0); + ADVANCE_BATCH(); + + if (!brw->hiz.op) { + hiz->need_resolve = INTEL_HIZ_NEED_DEPTH_RESOLVE; + } + } else { + BEGIN_BATCH(3); + OUT_BATCH(GEN7_3DSTATE_HIER_DEPTH_BUFFER << 16 | (3 - 2)); + OUT_BATCH(0); + OUT_BATCH(0); + ADVANCE_BATCH(); + } if (srb == NULL) { BEGIN_BATCH(3); diff --git a/src/mesa/drivers/dri/i965/gen7_sf_state.c b/src/mesa/drivers/dri/i965/gen7_sf_state.c index b1bec1a..6505fdb 100644 --- a/src/mesa/drivers/dri/i965/gen7_sf_state.c +++ b/src/mesa/drivers/dri/i965/gen7_sf_state.c @@ -152,7 +152,18 @@ upload_sf_state(struct brw_context *brw) /* _NEW_BUFFERS */ bool render_to_fbo = brw->intel.ctx.DrawBuffer->Name != 0; - dw1 = GEN6_SF_STATISTICS_ENABLE | GEN6_SF_VIEWPORT_TRANSFORM_ENABLE; + dw1 = GEN6_SF_STATISTICS_ENABLE; + + /* Enable viewport transform only if no HiZ operation is progress + * + * From page 11 of the SandyBridge PRM, Volume 2, Part 1, Section 1.3, "3D + * Primitives Overview": + * RECTLIST: Viewport Mapping must be DISABLED (as is typical with the + * use of screen- space coordinates). + */ + if (brw->hiz.op == 0) { + dw1 |= GEN6_SF_VIEWPORT_TRANSFORM_ENABLE; + } /* _NEW_BUFFERS */ dw1 |= (gen7_depth_format(brw) << GEN7_SF_DEPTH_BUFFER_SURFACE_FORMAT_SHIFT); diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c index 55a603e..56858c4 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c @@ -97,6 +97,32 @@ upload_wm_state(struct brw_context *brw) uint32_t dw1; dw1 = 0; + + if (brw->hiz.op != 0) { + switch (brw->hiz.op) { + case BRW_HIZ_OP_NONE: + break; + case BRW_HIZ_OP_DEPTH_CLEAR: + dw1 |= GEN6_WM_DEPTH_CLEAR; + break; + case BRW_HIZ_OP_DEPTH_RESOLVE: + dw1 |= GEN6_WM_DEPTH_RESOLVE; + break; + case BRW_HIZ_OP_HIZ_RESOLVE: + dw1 |= GEN6_WM_HIERARCHICAL_DEPTH_RESOLVE; + break; + default: + assert(!"Should not get here: invalid HiZ operation."); + break; + } + BEGIN_BATCH(3); + OUT_BATCH(_3DSTATE_WM << 16 | (3 - 2)); + OUT_BATCH(dw1); + OUT_BATCH(0); + ADVANCE_BATCH(); + return; + } + dw1 |= GEN7_WM_STATISTICS_ENABLE; dw1 |= GEN7_WM_LINE_AA_WIDTH_1_0; dw1 |= GEN7_WM_LINE_END_CAP_AA_WIDTH_0_5; -- 1.7.6.2 _______________________________________________ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev