On Thu, May 20, 2021 at 01:11:59PM +0200, Christian König wrote:
> Am 19.05.21 um 18:51 schrieb Matthew Brost:
> > On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> > > Oh, yeah we call that gang submit on the AMD side.
> > >
> > > Had already some internal discussions how to
Am 19.05.21 um 18:51 schrieb Matthew Brost:
On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
Oh, yeah we call that gang submit on the AMD side.
Had already some internal discussions how to implement this, but so far
couldn't figure out how to cleanly introduce that into the DRM
On Wed, May 19, 2021 at 01:45:39PM +0200, Christian König wrote:
> Oh, yeah we call that gang submit on the AMD side.
>
> Had already some internal discussions how to implement this, but so far
> couldn't figure out how to cleanly introduce that into the DRM scheduler.
>
> Can you briefly
śr., 19 maj 2021 o 01:41 Matthew Brost napisał(a):
>
> Add entry fpr i915 new parallel submission uAPI plan.
s/fpr/for/
>
> v2:
> (Daniel Vetter):
> - Expand logical order explaination
> - Add dummy header
> - Only allow N BBs in execbuf IOCTL
> - Configure parallel submission per slot
Oh, yeah we call that gang submit on the AMD side.
Had already some internal discussions how to implement this, but so far
couldn't figure out how to cleanly introduce that into the DRM scheduler.
Can you briefly describe in a few words how that is supposed to work on
the Intel side?
Add entry fpr i915 new parallel submission uAPI plan.
v2:
(Daniel Vetter):
- Expand logical order explaination
- Add dummy header
- Only allow N BBs in execbuf IOCTL
- Configure parallel submission per slot not per gem context
Cc: Tvrtko Ursulin
Cc: Tony Ye
CC: Carl Zhang
Cc: Daniel
