https://bugs.freedesktop.org/show_bug.cgi?id=94168
Józef Kucia changed:
What|Removed |Added
CC|
On 31.01.2017 02:37, Marek Olšák wrote:
On Mon, Jan 30, 2017 at 6:29 PM, Nicolai Hähnle wrote:
On 30.01.2017 18:20, Marek Olšák wrote:
On Mon, Jan 30, 2017 at 6:00 PM, Nicolai Hähnle
wrote:
On 27.01.2017 12:02, Marek Olšák wrote:
From: Marek
On 01/27/2017 11:32 PM, Timothy Arceri wrote:
> On Fri, 2017-01-27 at 17:42 +0100, Eduardo Lima Mitev wrote:
>> From GLSL 4.5 spec, section "7.1 Built-In Language Variables", page
>> 130 of
>> the PDF states:
>>
>> "If multiple shaders using members of a built-in block belonging
>> to
>>
On Monday, 2017-01-30 21:55:49 +0100, Bartosz Tomczyk wrote:
> Found by ASAN. There is no need to add +1 to strlen, we have already add
> +1 to str_end.
The change is mathematically correct, but the commit message need
rewording:
The `end+1` skips the ']', whereas the `strlen+1` includes the
On Tue, 2017-01-31 at 10:28 +0100, Eduardo Lima Mitev wrote:
> On 01/27/2017 11:32 PM, Timothy Arceri wrote:
> > On Fri, 2017-01-27 at 17:42 +0100, Eduardo Lima Mitev wrote:
> > > From GLSL 4.5 spec, section "7.1 Built-In Language Variables",
> > > page
> > > 130 of
> > > the PDF states:
> > >
>
On 30.01.2017 19:09, Ilia Mirkin wrote:
On Mon, Jan 30, 2017 at 1:06 PM, Ilia Mirkin wrote:
On Mon, Jan 30, 2017 at 12:26 PM, Nicolai Hähnle wrote:
On 30.01.2017 18:23, Ilia Mirkin wrote:
On Mon, Jan 30, 2017 at 4:36 AM, Ilia Mirkin
https://bugs.freedesktop.org/show_bug.cgi?id=99116
Józef Kucia changed:
What|Removed |Added
CC|
On 01/31/2017 11:15 AM, Timothy Arceri wrote:
> On Tue, 2017-01-31 at 10:28 +0100, Eduardo Lima Mitev wrote:
>> On 01/27/2017 11:32 PM, Timothy Arceri wrote:
>>> On Fri, 2017-01-27 at 17:42 +0100, Eduardo Lima Mitev wrote:
From GLSL 4.5 spec, section "7.1 Built-In Language Variables",
Hello Michel,
as this is for radeon, do you think this could/should fix
the wrong reported VRAM size with Unigine_Heaven/-Valley, too?
Maybe speed things up? ;-)
Unigine_Valley-1.0
GPU: Unknown GPU x1
System memory: 24102 MB
Video memory: 256 MB
Sync threads: 7
Async threads: 8
I'll try
On Mon, 2017-01-30 at 14:37 -0800, Nanley Chery wrote:
> Commit 2852efcda40274acf3272611c6a3b7731523a72d moved the location of
> the depth input attachment surface state from the render pass to the
> image view, but failed to update the surface state location used when
> emitting the binding
Thanks for fixing this Michel.
Reviewed-by: Samuel Pitoiset
On 01/31/2017 07:54 AM, Michel Dänzer wrote:
From: Michel Dänzer
The kernel driver reports correct values now.
Signed-off-by: Michel Dänzer
---
The `end+1` skips the ']', whereas the `strlen+1` includes the final
'\0' in the move to terminate the string.
---
src/compiler/glsl/link_uniforms.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/compiler/glsl/link_uniforms.cpp
b/src/compiler/glsl/link_uniforms.cpp
Am 31.01.2017 um 07:54 schrieb Michel Dänzer:
From: Michel Dänzer
vram_size is supposed to be the total amount of VRAM that can be used by
userspace, which corresponds to the TTM VRAM manager size (which is
normally the full amount of VRAM, but can be just the visible
On Tue, 2017-01-31 at 11:39 +0100, Eduardo Lima Mitev wrote:
> On 01/31/2017 11:15 AM, Timothy Arceri wrote:
> > On Tue, 2017-01-31 at 10:28 +0100, Eduardo Lima Mitev wrote:
> > > On 01/27/2017 11:32 PM, Timothy Arceri wrote:
> > > > On Fri, 2017-01-27 at 17:42 +0100, Eduardo Lima Mitev wrote:
> >
From: Dave Airlie
The CTS tests at least are using this, and we were totally
ignoring it.
This hopefully fixes the bouncing multisample CTS tests.
v2: get family mask in ignored case from command buffer.
Signed-off-by: Dave Airlie
---
From: Dave Airlie
Otherwise we were writing these as 4 components, and things went bad.
Fixes (the remaining):
dEQP-VK.clipping.user_defined.*.vert_geom.*
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 18 ++
1 file
From: Dave Airlie
This fixes clip distance fetches as they are single item loads
with a const_index like float[1].
Fixes:
dEQP-VK.clipping.user_defined.*.vert_geom.[0-6]
Signed-off-by: Dave Airlie
---
src/amd/common/ac_nir_to_llvm.c | 2 +-
1 file
https://bugs.freedesktop.org/show_bug.cgi?id=91556
Jan Vesely changed:
What|Removed |Added
Blocks||99553
Patches 1&2 are,
Reviewed-by: Edward O'Callaghan
On 02/01/2017 12:12 PM, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes clip distance fetches as they are single item loads
> with a const_index like float[1].
>
> Fixes:
>
On Fri, Jan 20, 2017 at 11:25 AM, Jason Ekstrand
wrote:
> On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <
> topi.pohjolai...@gmail.com> wrote:
>
>> Hardware state setup only needs offset and pitch and ignores the
>> rest.
>>
>
> True... But it seems a a bit sketchy to
Patches 1,2&3 are,
Reviewed-by: Edward O'Callaghan
On 02/01/2017 11:58 AM, Timothy Arceri wrote:
> From: Timothy Arceri
>
> ---
> src/mesa/state_tracker/st_atom_shader.c | 4 +---
> 1 file changed, 1 insertion(+), 3 deletions(-)
>
> diff
From: Dave Airlie
This code should be used in radv, so move it to a shared location
in advance of doing that.
Signed-off-by: Dave Airlie
---
src/amd/common/ac_llvm_util.c| 71 ++
src/amd/common/ac_llvm_util.h
On Tue, Jan 31, 2017 at 4:44 PM, Jason Ekstrand
wrote:
> On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <
> topi.pohjolai...@gmail.com> wrote:
>
>> This is kept on purpose in i965. It can be moved to ISL if it
>> is needed in vulkan.
>>
>> Pointers to miptrees are given
Tested-by: Mark Janes
Tom Stellard writes:
> This was broken by: e0cc0a614c96011958bc3a1b84da9168e0e1ccbb
>
> v2:
> - Use preprocessor macro
> ---
> src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 6 --
> 1 file changed, 4
On Tue, Jan 31, 2017 at 7:00 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 43 ++
> +++-
> src/intel/vulkan/genX_pipeline.c | 25
On Wed, Feb 1, 2017, at 00:48, Dave Airlie wrote:
> From: Dave Airlie
>
> The CTS tests at least are using this, and we were totally
> ignoring it.
>
> This hopefully fixes the bouncing multisample CTS tests.
>
> v2: get family mask in ignored case from command buffer.
>
On Tue, Jan 31, 2017 at 4:20 PM, Matt Turner wrote:
> Previously if you used MESA_GL_VERSION_OVERRIDE=3.3COMPAT, Mesa exposed
> an OpenGL 3.3 compatibility profile context (with various unimplemented
> features and bugs), but still refused to compile shaders with
>
>
---
src/intel/isl/isl_surface_state.c | 32
1 file changed, 32 insertions(+)
diff --git a/src/intel/isl/isl_surface_state.c
b/src/intel/isl/isl_surface_state.c
index b735478..c7b220b 100644
--- a/src/intel/isl/isl_surface_state.c
+++
Looks really good! I made a comment earlier about how it would be good to
add a couple more #defines for these magic vertex buffer handles. Also,
now that things are working, I'd like to re-confirm whether or not vertex
buffer 33 works. If it does, we should use it. If it doesn't, then I'm
On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> This series is a step towards using ISL instead of current
> intel_mipnap_tree/brw_tex_layout logic in i965. First 11 patches
> simplify the workspace for the rest and more functional changes.
>
> Next seven
This series is,
Reviewed-by: Edward O'Callaghan
On 02/01/2017 07:42 AM, Bas Nieuwenhuizen wrote:
> A basic implementation of VK_KHR_shader_draw_parameters. I haven't
> bothered with optimizing it away in the case the shader doesn't
> use it, but the impact seems low
On Tue, Jan 31, 2017 at 7:00 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/intel/vulkan/genX_cmd_buffer.c | 2 +-
> src/intel/vulkan/genX_pipeline.c | 2 +-
> 2 files changed, 2 insertions(+), 2
Did we actually end up needing this? After you got your gl_DrawId issues
sorted, were you ever able to get element 33 to work? The Sky Lake docs
say it should...
On Tue, Jan 31, 2017 at 7:00 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:
> Signed-off-by: Lionel Landwerlin
Look good to me,
For the series:
Reviewed-by: Dave Airlie
On 1 February 2017 at 06:42, Bas Nieuwenhuizen wrote:
> A basic implementation of VK_KHR_shader_draw_parameters. I haven't
> bothered with optimizing it away in the case the shader doesn't
This was broken by: e0cc0a614c96011958bc3a1b84da9168e0e1ccbb
v2:
- Use preprocessor macro
---
src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/si_shader_tgsi_setup.c
On Tue, Jan 31, 2017 at 2:55 PM, Antía Puentes wrote:
> On mar, 2017-01-31 at 12:09 +0100, Nicolai Hähnle wrote:
>> On 30.01.2017 19:09, Ilia Mirkin wrote:
>> >
>> > On Mon, Jan 30, 2017 at 1:06 PM, Ilia Mirkin wrote:
>> > >
>> > > On Mon, Jan 30, 2017
On Tue, Jan 31, 2017 at 7:11 PM, Jason Ekstrand
wrote:
> Looks really good! I made a comment earlier about how it would be good to
> add a couple more #defines for these magic vertex buffer handles. Also,
> now that things are working, I'd like to re-confirm whether or
Previously if you used MESA_GL_VERSION_OVERRIDE=3.3COMPAT, Mesa exposed
an OpenGL 3.3 compatibility profile context (with various unimplemented
features and bugs), but still refused to compile shaders with
#version 330 compatibility
This patch simply adds a small bit of plumbing to let that
From: Timothy Arceri
In the past I've gotten this function confused with the one in
ir_to_mesa.cpp of the same name. Now that the affected flag setting
has move into a helper it makes sense just to inline this remaining
code.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp
From: Timothy Arceri
This will be used when restoring tgsi from the on-disk shader
cache.
---
src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 217 +++--
1 file changed, 111 insertions(+), 106 deletions(-)
diff --git
From: Timothy Arceri
---
src/mesa/state_tracker/st_atom_shader.c | 4 +---
1 file changed, 1 insertion(+), 3 deletions(-)
diff --git a/src/mesa/state_tracker/st_atom_shader.c
b/src/mesa/state_tracker/st_atom_shader.c
index 8c10ac9..f79afe0 100644
---
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, January 31, 2017 1:54 AM
> To: amd-...@lists.freedesktop.org; mesa-dev@lists.freedesktop.org
> Subject: [PATCH] winsys/radeon: Allow visible VRAM size > 256MB
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Michel Dänzer
> Sent: Tuesday, January 31, 2017 1:54 AM
> To: amd-...@lists.freedesktop.org; mesa-dev@lists.freedesktop.org
> Subject: [PATCH] drm/radeon: Fix vram_size/visible values in
>
> -Original Message-
> From: amd-gfx [mailto:amd-gfx-boun...@lists.freedesktop.org] On Behalf
> Of Dieter Nützel
> Sent: Tuesday, January 31, 2017 6:25 AM
> To: Michel Dänzer
> Cc: Alex Deucher; mesa-dev@lists.freedesktop.org; amd-
> g...@lists.freedesktop.org
> Subject: Re: [Mesa-dev]
On Tue, Jan 31, 2017 at 7:00 AM, Lionel Landwerlin
wrote:
> Enables 10 tests from:
>
>dEQP-VK.draw.shader_draw_parameters.*
and I assume they all pass with this series.
>
> Signed-off-by: Lionel Landwerlin
> ---
>
From: Dave Airlie
The CTS tests at least are using this, and we were totally
ignoring it.
This hopefully fixes the bouncing multisample CTS tests.
v2: get family mask in ignored case from command buffer.
v3: only change things in one place, use logic from Bas.
On Mon, Jan 16, 2017 at 1:13 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> This is kept on purpose in i965. It can be moved to ISL if it
> is needed in vulkan.
>
> Pointers to miptrees are given solely for verification purposes.
> These will be dropped in following patches.
>
>
I wonder if it'd be beneficial to adjust the
_mesa_glsl_process_extension logic to force api = API_OPENGL_COMPAT
when compat_shader is set. For now, ctx->API has to match, so it
should never matter, but perhaps in the future, this would be a tricky
little bug to track down.
On Tue, Jan 31, 2017
On Mon, Jan 16, 2017 at 1:14 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Signed-off-by: Topi Pohjolainen
> ---
> src/mesa/drivers/dri/i965/brw_blorp.c | 25
> -
> src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6
On Tue, Jan 31, 2017 at 11:12:31AM -0800, Jason Ekstrand wrote:
>On Tue, Jan 31, 2017 at 10:38 AM, Jason Ekstrand
><[1]ja...@jlekstrand.net> wrote:
>
>On Tue, Jan 31, 2017 at 8:15 AM, Topi Pohjolainen
><[2]topi.pohjolai...@gmail.com> wrote:
>
> Current estimate doesn't
Reviewed-by: Iago Toral Quiroga
On Tue, 2017-01-31 at 15:20 -0500, Robert Foss wrote:
> Add assert checking that num_sources is never larger than 3.
>
> This prevents Coverity from concluding that the unhandled
> cases of num_sources not being 0-3 are relevant.
>
>
Reviewed-by: Bas Nieuwenhuizen
On Wed, Feb 1, 2017, at 01:25, Dave Airlie wrote:
> From: Dave Airlie
>
> The CTS tests at least are using this, and we were totally
> ignoring it.
>
> This hopefully fixes the bouncing multisample CTS tests.
>
>
On Tue, Jan 31, 2017 at 01:37:25PM -0800, Jason Ekstrand wrote:
>On Wed, Jan 25, 2017 at 10:39 AM, Pohjolainen, Topi
><[1]topi.pohjolai...@gmail.com> wrote:
>
> On Mon, Jan 23, 2017 at 10:21:54PM -0800, Ben Widawsky wrote:
> > On Gen9 hardware, the display engine is able to
Patches 1-2 are
Reviewed-by: Bas Nieuwenhuizen
On Wed, Feb 1, 2017, at 02:12, Dave Airlie wrote:
> From: Dave Airlie
>
> This fixes clip distance fetches as they are single item loads
> with a const_index like float[1].
>
> Fixes:
>
Both patches:
Reviewed-by: Nicolai Hähnle
On 31.01.2017 07:54, Michel Dänzer wrote:
From: Michel Dänzer
The kernel driver reports correct values now.
Signed-off-by: Michel Dänzer
---
On 31.01.2017 12:02, Bartosz Tomczyk wrote:
The `end+1` skips the ']', whereas the `strlen+1` includes the final
'\0' in the move to terminate the string.
Thanks! R-b and pushed.
Nicolai
---
src/compiler/glsl/link_uniforms.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
Add assert checking that num_sources is never larger than 3.
This prevents Coverity from concluding that the improperly handled
cases of num_sources not being 0-3 are relevant.
Coverity-Id: 1399480-1399489
Signed-off-by: Robert Foss
---
https://bugs.freedesktop.org/show_bug.cgi?id=99601
Daniel Stone changed:
What|Removed |Added
Status|NEW |RESOLVED
Hi,
This is another iteration at KHR_shader_draw_parameters. As Jason
mentioned looking at one of the commit in the previous version of this
series, we were missing the emission of gl_DrawIDARB. There is an
interesting dependency between the compiler backend and the frontend
API which is
Up to now on Gen8+ we only allocated a vertex element for
gl_InstanceIndex or gl_VertexIndex when a vertex shader uses
gl_BaseInstanceARB or gl_BaseVertexARB. This is because we would
configure the VF_SGVS packet to make the VF unit write the
gl_InstanceIndex & gl_VertexIndex values right behind
Signed-off-by: Lionel Landwerlin
---
src/compiler/spirv/nir_spirv.h | 1 +
src/compiler/spirv/spirv_to_nir.c | 4
src/compiler/spirv/vtn_variables.c | 12
3 files changed, 17 insertions(+)
diff --git a/src/compiler/spirv/nir_spirv.h
Enables 10 tests from:
dEQP-VK.draw.shader_draw_parameters.*
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c | 4
src/intel/vulkan/anv_pipeline.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c
On Tue, Jan 31, 2017 at 06:13:45PM +0200, Topi Pohjolainen wrote:
> v2:
>- Fix return value (s/MESA_FORMAT_NONE/false/) (Anuj)
>- Move _mesa_tex_format_from_format_and_type() just
> in the end avoiding additional if-block (Anuj)
>- Explain better the array alignment restriction
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/anv_device.c| 4 ++--
src/intel/vulkan/anv_private.h | 2 +-
src/intel/vulkan/genX_pipeline.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/intel/vulkan/anv_device.c
Signed-off-by: Lionel Landwerlin
---
src/compiler/shader_enums.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/compiler/shader_enums.c b/src/compiler/shader_enums.c
index 3c5a268687..e704c95a6b 100644
--- a/src/compiler/shader_enums.c
+++
Acked-by: Marek Olšák
Marek
On Tue, Jan 31, 2017 at 12:25 AM, Timothy Arceri wrote:
> ---
> src/mesa/state_tracker/st_program.c | 118
> ++--
> 1 file changed, 58 insertions(+), 60 deletions(-)
>
> diff --git
v2:
- Fix return value (s/MESA_FORMAT_NONE/false/) (Anuj)
- Move _mesa_tex_format_from_format_and_type() just
in the end avoiding additional if-block (Anuj)
- Explain better the array alignment restriction (Anuj)
- Do not bail out in case of gl_pixelstore_attrib::ImageHeight,
Current estimate doesn't consider space needed for surface states
and it only calculates for one shader stage. Each stage can have
its own sampler and surface state configuration.
While this is only matter of runtime dynamics we don't seem to hit
it currently. However, this becomes visible with
Fix issue with index buffers that do not contain 0 index. Use core
BaseVertex functionality to offset index buffer indices, instead of
offsetting vertex buffer to point before the buffer origin.
---
src/gallium/drivers/swr/swr_draw.cpp | 2 +-
src/gallium/drivers/swr/swr_state.cpp | 2 +-
2
Up to now on Gen8+ we only allocated a vertex element for
gl_InstanceIndex or gl_VertexIndex when a vertex shader uses
gl_BaseInstanceARB or gl_BaseVertexARB. This is because we would
configure the VF_SGVS packet to make the VF unit write the
gl_InstanceIndex & gl_VertexIndex values right behind
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/genX_cmd_buffer.c | 2 +-
src/intel/vulkan/genX_pipeline.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/intel/vulkan/genX_cmd_buffer.c
b/src/intel/vulkan/genX_cmd_buffer.c
index
Signed-off-by: Lionel Landwerlin
---
src/intel/vulkan/genX_cmd_buffer.c | 43 +-
src/intel/vulkan/genX_pipeline.c | 25 +-
2 files changed, 62 insertions(+), 6 deletions(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=99618
Bug ID: 99618
Summary: AVX Intrinsics Run in GUI thread only
Product: Mesa
Version: 13.0
Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
Severity:
Here's the current code:
for (UINT i = 0; i < ctx->num_vertex_buffers; i++) {
uint32_t size, pitch, elems, partial_inbounds;
const uint8_t *p_data;
struct pipe_vertex_buffer *vb = >vertex_buffer[i];
pitch = vb->stride;
if (!vb->user_buffer) {
On Tue, Jan 31, 2017 at 6:46 AM, Robert Foss wrote:
> Add assert checking that num_sources is never larger than 3.
>
> This prevents Coverity from concluding that the improperly handled
> cases of num_sources not being 0-3 are relevant.
>
You may change "improperly
What's the problem being fixed exactly? We're passing what is
effectively the zero index to the core, and the core shouldn't ever
access data outside of [min, max] + bias.
That said, what you have is probably a cleaner implementation. However
I'm a bit concerned about how it will function with
Ilia,
The problem is the following: This occurs only with index buffers that do not
contain vertex index 0. The vertex fetcher operates in blocks of 8 vertices.
Consequently, the last batch of 8 could access elements outside the range of
the index buffer. There is a chance that those
On Tue, Jan 31, 2017 at 8:15 AM, Topi Pohjolainen <
topi.pohjolai...@gmail.com> wrote:
> Current estimate doesn't consider space needed for surface states
> and it only calculates for one shader stage. Each stage can have
> its own sampler and surface state configuration.
>
> While this is only
This extension provides a new texture and sampler parameter
(TEXTURE_REDUCTION_MODE_ARB) which allows applications to produce a
filtered texel value by computing a component-wise minimum (MIN) or
maximum (MAX) of the texels that would normally be averaged. The
reduction mode is orthogonal to the
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
> The idea behind modifiers like this is that the user of GBM will have
> some mechanism to query what properties the hardware supports for its BO
> or surface. This information is directly passed in (and stored) so that
>
Thanks,
Good point. I'll send a new version our for review.
George
> -Original Message-
> From: ibmir...@gmail.com [mailto:ibmir...@gmail.com] On Behalf Of Ilia
> Mirkin
> Sent: Tuesday, January 31, 2017 11:50 AM
> To: Kyriazis, George
> Cc:
Add assert checking that num_sources is never larger than 3.
This prevents Coverity from concluding that the unhandled
cases of num_sources not being 0-3 are relevant.
Coverity-Id: 1399480-1399489
Signed-off-by: Robert Foss
Reviewed-by: Anuj Phogat
This looks like it misses the interactions with texture completeness.
- Chris
On Wed, Feb 1, 2017 at 7:53 AM, Plamena Manolova wrote:
> This extension provides a new texture and sampler parameter
> (TEXTURE_REDUCTION_MODE_ARB) which allows applications to produce a
Blorp doesn't use uniform push constants anymore so there's no need to
support them in compile_nir_shader.
Signed-off-by: Jason Ekstrand
---
src/intel/blorp/blorp.c | 23 ---
1 file changed, 23 deletions(-)
diff --git a/src/intel/blorp/blorp.c
While we're at it, we rename it to remove the brw_ prefix
Signed-off-by: Jason Ekstrand
---
src/intel/blorp/blorp.c | 26 +-
src/intel/blorp/blorp_blit.c | 2 +-
src/intel/blorp/blorp_clear.c | 2 +-
src/intel/blorp/blorp_genX_exec.h | 72
On Tue, Jan 31, 2017 at 10:38 AM, Jason Ekstrand
wrote:
>
> On Tue, Jan 31, 2017 at 8:15 AM, Topi Pohjolainen <
> topi.pohjolai...@gmail.com> wrote:
>
>> Current estimate doesn't consider space needed for surface states
>> and it only calculates for one shader stage. Each
On Sun, Jan 29, 2017 at 8:29 PM, Kenneth Graunke wrote:
> On Sunday, January 29, 2017 6:20:10 PM PST Matt Turner wrote:
>> This partially reverts commit 97217a40f97cdeae0304798b607f704deb0c3558.
>> It leaves ES 2.0 support in place per Ian's suggestion, because ES 2.0
>> is
On mar, 2017-01-31 at 12:09 +0100, Nicolai Hähnle wrote:
> On 30.01.2017 19:09, Ilia Mirkin wrote:
> >
> > On Mon, Jan 30, 2017 at 1:06 PM, Ilia Mirkin wrote:
> > >
> > > On Mon, Jan 30, 2017 at 12:26 PM, Nicolai Hähnle wrote:
> > > >
> > > > On 30.01.2017 18:23, Ilia
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
> This patch begins introducing how we'll actually handle the potentially
> many modifiers coming in from the API, how we'll store them, and the
> structure in the code to support it.
>
> Prior to this patch, the Y-tiled
It is not clear from the docs exactly how pipelined STATE_BASE_ADDRESS
actually is. Previously, we knew we needed to flush prior to re-emitting
STATE_BASE_ADDRESS on gen8+ but we had never confirmed it on gen7 so we
left it alone and avoided the flush. Recently, Mark found hangs on gen7
which
On Mon, Jan 23, 2017 at 10:19 PM, Ben Widawsky wrote:
> v2: Preserve legacy behavior when plane is 0 (Jason Ekstrand)
> EINVAL when input plane is greater than total planes (Jason Ekstrand)
> Don't leak the image after fromPlanar (Daniel)
> Move bo->image check below plane
On Mon, Jan 23, 2017 at 10:19 PM, Ben Widawsky wrote:
> Unlike stride, there was no previous offset getter, so it can be right
> on the first try.
>
> v2: Return EINVAL when plane is greater than total planes to make it
> match the similar APIs.
> Avoid leak after fromPlanar
Patches 1 and 2 are
Reviewed-by: Bas Nieuwenhuizen
On Tue, Jan 31, 2017, at 16:00, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin
> ---
> src/compiler/spirv/nir_spirv.h | 1 +
> src/compiler/spirv/spirv_to_nir.c | 4
On Sun, Jan 22, 2017 at 10:42 PM, Kenneth Graunke
wrote:
> Previously we disabled the guardband when the viewport was smaller than
> the framebuffer on Gen6-7.5, to prevent portions of primitives from
> being draw outside of the viewport. On Gen8+, we relied on the
On Tue, Jan 31, 2017 at 1:53 PM, Plamena Manolova
wrote:
> This extension provides a new texture and sampler parameter
> (TEXTURE_REDUCTION_MODE_ARB) which allows applications to produce a
> filtered texel value by computing a component-wise minimum (MIN) or
> maximum
Reviewed-by: Jason Ekstrand
On Sun, Jan 22, 2017 at 10:42 PM, Kenneth Graunke
wrote:
> This reverts commit 0bac2551e40410e2251daf4fd9faf69310ab34ce.
>
> Now that we position the guardband correctly (applying translations
> in addition to scaling)
On Mon, Jan 23, 2017 at 10:21 PM, Ben Widawsky wrote:
> Replace the naive, 'save all the modifiers' with a proper query for just
> the modifier that was selected. To accomplish this, two new query tokens
> are added to the extension:
> __DRI_IMAGE_ATTRIB_MODIFIER_UPPER
>
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_device.c | 4
src/amd/vulkan/radv_pipeline.c | 1 +
2 files changed, 5 insertions(+)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index da67b65ef43..0c8af823263 100644
---
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/vulkan/radv_cmd_buffer.c | 14 +-
1 file changed, 9 insertions(+), 5 deletions(-)
diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 091d970ee0b..97c6b63ce01 100644
---
Signed-off-by: Bas Nieuwenhuizen
---
src/amd/common/ac_nir_to_llvm.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index c622c006cec..132150139c7 100644
---
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