https://bugs.freedesktop.org/show_bug.cgi?id=99553
Bug 99553 depends on bug 91305, which changed state.
Bug 91305 Summary: [clover/kaveri] When running JohnTheRipper OpenCL tests:
radeon :01:00.0: ring 0 stalled for more than ...msec
https://bugs.freedesktop.org/show_bug.cgi?id=91305
https://bugs.freedesktop.org/show_bug.cgi?id=91305
Dennis Schridde changed:
What|Removed |Added
Status|NEW |RESOLVED
Resolution|---
Sorry Marek, I just pushed an identical patch as I had missed this one.
Jose
On 09/09/18 02:02, Marek Olšák wrote:
From: Marek Olšák
Windows doesn't have thrd_current.
---
src/gallium/auxiliary/util/u_helpers.c | 2 ++
1 file changed, 2 insertions(+)
diff --git
Hi,
Il giorno lun 10 set 2018 alle ore 09:58 Tapani Pälli
ha scritto:
>
> Marek sent a similar fix here:
> https://lists.freedesktop.org/archives/mesa-dev/2018-September/204797.html
Thanks a lot!
So the APU L3 cache optimization will be lost for Android
>
> On 09/10/2018 10:52 AM, Mauro Rossi
Build mesa 8844 completed
Commit 52ca32121b by Jose Fonseca on 9/7/2018 12:27 PM:
Require Visual Studio 2015.\n\nWe no longer need or use Visual Studio 2013.\n\nhttps://ci.appveyor.com/project/jrfonseca/mesa/build/52\n\nReviewed-by: Roland Scheidegger
The patches are pushed now.
Thanks for the review!
best
Mathias
On Thursday, 6 September 2018 16:42:51 CEST Brian Paul wrote:
> The series looks good to me.
>
> Reviewed-by: Brian Paul
>
> On 09/06/2018 08:31 AM, mathias.froehl...@gmx.net wrote:
> > From: Mathias Fröhlich
> >
> > Introduce
Hello,
just reminder for case: don't have push-rights...
On Fri, Sep 7, 2018 at 8:05 PM, Dylan Baker wrote:
> Quoting Sergii Romantsov (2018-09-07 02:43:41)
> > Building of 32bit mesa with meson causes linkage issue:
> > "undefined reference to `util_get_process_name'"
> > Fixed by adding
Marek sent a similar fix here:
https://lists.freedesktop.org/archives/mesa-dev/2018-September/204797.html
On 09/10/2018 10:52 AM, Mauro Rossi wrote:
This patch is to tackle with shortcomings in Android bionic libc.
Even if setting cflag -D__USE__GNU and adding include of cpuset macros
may
https://bugs.freedesktop.org/show_bug.cgi?id=101927
Timothy Arceri changed:
What|Removed |Added
Assignee|dri-devel@lists.freedesktop |mesa-dev@lists.freedesktop.
This patch is to tackle with shortcomings in Android bionic libc.
Even if setting cflag -D__USE__GNU and adding include of cpuset
macros
may become available, bionic libc does not support pthread_{g,s}etaffinity_np()
Wrappers to sched_{g,s]etaffinity() were found to here:
On 09/09/18 02:02, Marek Olšák wrote:
From: Marek Olšák
---
src/util/u_thread.h | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/src/util/u_thread.h b/src/util/u_thread.h
index ec0d9a7..0c20ebb 100644
--- a/src/util/u_thread.h
+++ b/src/util/u_thread.h
@@ -29,20
Since commit af3685d14936844f79e6f372b4b258e29375f21b various OpenGL
applications regressed
on the classic mesa radeon driver.
Signed-off-by: Christopher Egert
CC:
---
src/mesa/drivers/dri/r200/r200_state.c | 8
src/mesa/drivers/dri/radeon/radeon_state.c | 8
2 files
Hi,
On Thu, Sep 06, 2018 at 04:31:12PM +0200, mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich
>
> Hi all,
>
> The following two patches introduce a gallium capability
> to feed gl_constants::MaxVertexAttribRelativeOffset.
> Then adapt etnyviv to return what it can really handle.
>
https://bugs.freedesktop.org/show_bug.cgi?id=107878
--- Comment #2 from coolo...@gmail.com ---
to clarify, this also occurs on mesa 18.1.6 and llvm6
--
You are receiving this mail because:
You are the QA Contact for the bug.
You are the assignee for the
Thank you Józef and Ilia for pointing this out!
I believe I have fully understood what's happening here and I'll send a
final version of the fix soon.
On 9/7/18 7:47 PM, Józef Kucia wrote:
On Fri, Sep 7, 2018 at 6:44 PM Ilia Mirkin wrote:
On Fri, Sep 7, 2018 at 12:35 PM, Józef Kucia
Am Freitag, den 07.09.2018, 17:57 -0400 schrieb Marek Olšák:
> RG can't be used to represent intensity, because RG uses swizzle
> RG01, while intensity uses .
I see, and thanks, I guess the mesa side then has to check these sizes
too, so I'll prepare a patch for this.
Best,
Gert
>
>
From: Gert Wollny
Gallium may pick L16A16_FLOAT to represent GL_INTENSITY16F if no intensity
format is provided by the driver. However, when calling
glGetTexLevelParameteriv(..., GL_TEXTURE_INTENSITY_SIZE, ...)
mesa will return a zero size because the actually used format has no
intensity
Reviewed-by: Alejandro Piñeiro
On 10/09/18 12:41, Timothy Arceri wrote:
> ---
> src/mesa/main/matrix.c | 10 +++---
> 1 file changed, 3 insertions(+), 7 deletions(-)
>
> diff --git a/src/mesa/main/matrix.c b/src/mesa/main/matrix.c
> index 83f081e88e5..8065a83705c 100644
> ---
Quoting andrey simiklit (2018-08-21 13:00:57)
> Hi all,
>
> The bug for this issue was created:
> https://bugs.freedesktop.org/show_bug.cgi?id=107626
What about something like
diff --git a/src/mesa/drivers/dri/i965/brw_draw.c
b/src/mesa/drivers/dri/i965/brw_draw.c
index
On Fri, 2018-09-07 at 14:58 +0100, Emil Velikov wrote:
> From: Emil Velikov
>
> The meson requirement was bumped recently to 0.45, which requires
> python 3.5
>
> On travis that is only available on xenial. Additionally we need to pull
> setuptools package otherwise pip fails to install meson.
On Monday, 2018-09-10 14:15:33 +0200, Juan A. Suarez Romero wrote:
> Newer Meson versions require python >=3.5. But in Trusty default python3
> version is 3.4.x.
>
> Install python3.5 and makes it the default version for Meson using
> update-alternatives method.
>
> CC: Jan Vesely
> CC: Andres
https://bugs.freedesktop.org/show_bug.cgi?id=107878
--- Comment #1 from coolo...@gmail.com ---
Created attachment 141504
--> https://bugs.freedesktop.org/attachment.cgi?id=141504=edit
screenshot example
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA
Newer Meson versions require python >=3.5. But in Trusty default python3
version is 3.4.x.
Install python3.5 and makes it the default version for Meson using
update-alternatives method.
CC: Jan Vesely
CC: Andres Gomez
CC: Emil Velikov
CC: Jon Turney
CC: Eric Engestrom
CC: Dylan Baker
---
https://bugs.freedesktop.org/show_bug.cgi?id=10
--- Comment #7 from ilia ---
Created attachment 141506
--> https://bugs.freedesktop.org/attachment.cgi?id=141506=edit
Fullscreen
Pressing alt+tab I eventually got able to see game menu. But it was not
interactable - even mouse hover.
---
src/mesa/main/matrix.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git a/src/mesa/main/matrix.c b/src/mesa/main/matrix.c
index 83f081e88e5..8065a83705c 100644
--- a/src/mesa/main/matrix.c
+++ b/src/mesa/main/matrix.c
@@ -657,20 +657,16 @@ void
https://bugs.freedesktop.org/show_bug.cgi?id=10
--- Comment #6 from ilia ---
Yes, results are the same. Moreover, I attached screenshots specifically for
this case:
1. wine in desktop mode + fullscreen game
https://bugs.freedesktop.org/attachment.cgi?id=141398
2. wine in desktop mode +
From: Andrii Simiklit
If we restore the 'new batch' using 'intel_batchbuffer_reset_to_saved'
function we must restore the default state of the batch using
'brw_new_batch' function because the 'intel_batchbuffer_flush'
function will not do it for the 'new batch' again.
At least the following
Hi,
On Thu, Sep 06, 2018 at 04:31:14PM +0200, mathias.froehl...@gmx.net wrote:
> From: Mathias Fröhlich
>
> Signed-off-by: Mathias Fröhlich
I know it's pushed already but for the record (Just came back form vacation):
Tested-By: Guido Gúnther
> ---
>
Handle all cases in calculation of layers count for isl_view
taking into account texture view and image unit.
st_convert_image was taken as a reference.
When u->Layered is true the whole level is taken with respect to
image view. In other case only one layer is taken.
v3: (Józef Kucia and Ilia
On 2018-09-07 11:35 p.m., Marek Olšák wrote:
> From: Marek Olšák
>
> Tested-by: Dieter Nützel
> ---
> src/gallium/auxiliary/util/u_inlines.h | 9 +
> 1 file changed, 5 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/auxiliary/util/u_inlines.h
>
Noticed while working in this area. Ported from RadeonSI.
v2: fix missing * num_se
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index
Hello,
Thanks for your reply.
Please find my comments below:
On Mon, Sep 10, 2018 at 2:45 PM Chris Wilson
wrote:
> Quoting andrey simiklit (2018-08-21 13:00:57)
> > Hi all,
> >
> > The bug for this issue was created:
> > https://bugs.freedesktop.org/show_bug.cgi?id=107626
>
> What about
On 2018-09-07 9:01 p.m., Marek Olšák wrote:
> On Fri, Sep 7, 2018 at 11:04 AM, Michel Dänzer wrote:
>> On 2018-09-07 4:31 p.m., Marek Olšák wrote:
>>> On Fri, Sep 7, 2018, 4:34 AM Michel Dänzer wrote:
On 2018-09-06 10:56 p.m., Axel Davy wrote:
> I fear if we begin to do the work
On 9/10/18 6:12 PM, Ilia Mirkin wrote:
On Mon, Sep 10, 2018 at 12:03 PM, Samuel Pitoiset
wrote:
Noticed while working in this area. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff
Noticed while working in this area. Ported from RadeonSI.
Signed-off-by: Samuel Pitoiset
---
src/amd/vulkan/radv_pipeline.c | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 1741d5e9047..e362c380453
Quoting Sergii Romantsov (2018-09-09 23:52:04)
> Hello,
> just reminder for case: don't have push-rights...
>
> On Fri, Sep 7, 2018 at 8:05 PM, Dylan Baker wrote:
>
> Quoting Sergii Romantsov (2018-09-07 02:43:41)
> > Building of 32bit mesa with meson causes linkage issue:
> >
I agree that using code from mesa in util is gross, I'm not planning to leave it
like this. I'm in the middle of cleaning up duplication between util and mesa,
and I'll plan on pulling u_cpu_detection down into src/util in that series.
In this case while gross there shouldn't be any compilation
On Mon, Sep 10, 2018 at 12:03 PM, Samuel Pitoiset
wrote:
> Noticed while working in this area. Ported from RadeonSI.
>
> Signed-off-by: Samuel Pitoiset
> ---
> src/amd/vulkan/radv_pipeline.c | 6 +-
> 1 file changed, 5 insertions(+), 1 deletion(-)
>
> diff --git
On 2018-09-07 11:35 p.m., Marek Olšák wrote:
> From: Marek Olšák
>
> +1.2% performance with:
> piglit/drawoverhead - DrawElements (no state changes) on radeonsi
No meaningless number (which is most likely the same order of magnitude,
maybe even smaller than the deviation between test runs)
On 09/09/2018 06:00 PM, Timothy Arceri wrote:
> On 10/09/18 10:40, Ian Romanick wrote:
>> On 09/09/2018 05:00 PM, Timothy Arceri wrote:
>>> Ian made it pretty clear he didn't want a debate and had already made up
>>> his mind.
>>>
>>> "We decided years ago that we were not going to support this
On 09/09/2018 07:00 PM, Timothy Arceri wrote:
> On 10/09/18 11:01, Matt Turner wrote:
>> I think it's evident that we can find a way forward based on past
>> experiences (compatibility profile is supported in Mesa!).
>
> I don't really know what you are trying to say here. I continued what
>
Quoting Mauro Rossi (2018-09-09 01:56:20)
> Hi,
>
> Il giorno gio 6 set 2018 alle ore 18:20 Dylan Baker
> ha scritto:
> >
> > Quoting Rob Herring (2018-09-06 07:16:07)
> > > On Mon, Sep 3, 2018 at 4:27 PM Eric Anholt wrote:
> > > >
> > > > Mauro Rossi writes:
> > > >
> > > > > Fixes the
Acked-by: Bas Nieuwenhuizen
On Mon, Sep 10, 2018 at 7:09 PM Jason Ekstrand wrote:
>
> ---
> include/vulkan/vulkan_core.h | 139 +++--
> src/vulkan/registry/vk.xml | 280 +++
> 2 files changed, 345 insertions(+), 74 deletions(-)
>
> diff --git
Cc: Bas Nieuwenhuizen
---
src/intel/vulkan/anv_device.c | 8
src/intel/vulkan/anv_extensions.py | 2 +-
2 files changed, 9 insertions(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 7ab8543300b..44855dae128 100644
---
---
include/vulkan/vulkan_core.h | 139 +++--
src/vulkan/registry/vk.xml | 280 +++
2 files changed, 345 insertions(+), 74 deletions(-)
diff --git a/include/vulkan/vulkan_core.h b/include/vulkan/vulkan_core.h
index 06c860707b8..fe450142503 100644
---
https://bugs.freedesktop.org/show_bug.cgi?id=107890
Bug ID: 107890
Summary: [bisected] Android build test fails "use of undeclared
identifier 'cpu_set_t'/'cpuset'"
Product: Mesa
Version: git
Hardware: Other
---
src/amd/vulkan/radv_device.c | 7 +++
src/amd/vulkan/radv_extensions.py | 2 +-
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 53f99a8cecd..7917ed7ffe5 100644
--- a/src/amd/vulkan/radv_device.c
+++
https://bugs.freedesktop.org/show_bug.cgi?id=107890
--- Comment #1 from Tapani Pälli ---
Fix here:
https://lists.freedesktop.org/archives/mesa-dev/2018-September/204797.html
--
You are receiving this mail because:
You are the QA Contact for the
---
src/compiler/spirv/spirv.core.grammar.json | 95 --
src/compiler/spirv/spirv.h | 24 ++
2 files changed, 114 insertions(+), 5 deletions(-)
diff --git a/src/compiler/spirv/spirv.core.grammar.json
b/src/compiler/spirv/spirv.core.grammar.json
index
---
include/vulkan/vulkan_core.h | 139 +++--
src/vulkan/registry/vk.xml | 280 +++
2 files changed, 345 insertions(+), 74 deletions(-)
diff --git a/include/vulkan/vulkan_core.h b/include/vulkan/vulkan_core.h
index 06c860707b8..fe450142503 100644
---
The instruction scheduler is re-ordering loads which is causing fence
values to be loaded after the value they're fencing. In particular,
consider the following pseudocode:
void try_use_a_thing(int idx)
{
bool ready = ssbo.arr[idx].ready;
vec4 data = ssbo.arr[idx].data;
---
src/intel/vulkan/anv_device.c | 7 +++
src/intel/vulkan/anv_extensions.py | 1 +
src/intel/vulkan/anv_pipeline.c| 1 +
3 files changed, 9 insertions(+)
diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index 47c6c6e93b4..9b15fc0648b 100644
---
---
src/compiler/shader_info.h| 1 +
src/compiler/spirv/spirv_to_nir.c | 20 ++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/src/compiler/shader_info.h b/src/compiler/shader_info.h
index 65bc0588d67..a19840666ac 100644
--- a/src/compiler/shader_info.h
---
src/compiler/spirv/spirv_to_nir.c | 170 ++
1 file changed, 103 insertions(+), 67 deletions(-)
diff --git a/src/compiler/spirv/spirv_to_nir.c
b/src/compiler/spirv/spirv_to_nir.c
index 96224354057..3378641513c 100644
--- a/src/compiler/spirv/spirv_to_nir.c
+++
This patch series adds support to the Intel Vulkan driver for the
(currently provisional) VK_KHR_vulkan_memory_model extension. The
extension provides a few extra SPIR-V decorations along with some
additional guarantees about memory transaction ordering that aim to make
better analysis and use of
---
src/compiler/spirv/spirv_info.h| 1 +
src/compiler/spirv/spirv_info_c.py | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/compiler/spirv/spirv_info.h b/src/compiler/spirv/spirv_info.h
index 121ffd2febb..9813035e60f 100644
--- a/src/compiler/spirv/spirv_info.h
+++
I tried, but I can't find from your driver what the HW does, so for
this review the same assumption that the CTS tests pass for you.
Reviewed-by: Bas Nieuwenhuizen
On Mon, Sep 10, 2018 at 7:08 PM Jason Ekstrand wrote:
>
> Cc: Bas Nieuwenhuizen
> ---
> src/intel/vulkan/anv_device.c | 8
On Mon, Sep 10, 2018 at 1:43 PM Bas Nieuwenhuizen
wrote:
> I tried, but I can't find from your driver what the HW does, so for
> this review the same assumption that the CTS tests pass for you.
>
Our hardware does the DX thing which is also what the spec says. Yes, we
pass the tests.
Assuming you pass the CTS tests (which I'm pretty sure you do),
Reviewed-by: Jason Ekstrand
Mind reviewing mine?
On Mon, Sep 10, 2018 at 1:35 PM Bas Nieuwenhuizen
wrote:
> ---
> src/amd/vulkan/radv_device.c | 7 +++
> src/amd/vulkan/radv_extensions.py | 2 +-
> 2 files changed, 8
I recommend CCing stable (I just did on mine) so that it goes into 18.2.
On Mon, Sep 10, 2018 at 1:35 PM Bas Nieuwenhuizen
wrote:
> ---
> src/amd/vulkan/radv_device.c | 7 +++
> src/amd/vulkan/radv_extensions.py | 2 +-
> 2 files changed, 8 insertions(+), 1 deletion(-)
>
> diff --git
On Mon, Sep 10, 2018 at 10:45 AM, Michel Dänzer wrote:
> On 2018-09-07 9:01 p.m., Marek Olšák wrote:
>> On Fri, Sep 7, 2018 at 11:04 AM, Michel Dänzer wrote:
>>> On 2018-09-07 4:31 p.m., Marek Olšák wrote:
On Fri, Sep 7, 2018, 4:34 AM Michel Dänzer wrote:
> On 2018-09-06 10:56 p.m.,
From: Josh Pieper
When using Freecad, I was getting intermittent segfaults inside of
mesa. I traced it down to this path in st_cb_drawpixels.c where the
result of pipe_transfer_map wasn't being checked. In my case, it was
returning NULL because nouveau_bo_new returned ENOENT. I'm by no
means
On Mon, Sep 10, 2018 at 2:53 PM Bas Nieuwenhuizen
wrote:
> On Mon, Sep 10, 2018 at 8:59 PM Jason Ekstrand
> wrote:
> >
> > I recommend CCing stable (I just did on mine) so that it goes into 18.2.
>
> You're right, added the CC in the commit when pushing. This has a
> dependency on
v2: Tell B10G10R10X2 and R10G10B10X2 formats for different HW.
Signed-off-by: Leo Liu
---
src/gallium/auxiliary/vl/vl_winsys.h | 5 ++
src/gallium/auxiliary/vl/vl_winsys_dri.c | 69
2 files changed, 64 insertions(+), 10 deletions(-)
diff --git
Forget the Patch 1, will re-send shortly.
It's ming case 24:
+vl_dri2_format_for_depth(struct vl_screen *vscreen, int depth)
+{
+ switch (depth) {
+ case 24:
+ case 30:
Leo
On 09/10/2018 04:27 PM, Leo Liu wrote:
v2: Tell B10G10R10X2 and R10G10B10X2 formats for different HW.
On Mon, Sep 10, 2018 at 11:41 AM, Michel Dänzer wrote:
> On 2018-09-07 11:35 p.m., Marek Olšák wrote:
>> From: Marek Olšák
>>
>> +1.2% performance with:
>> piglit/drawoverhead - DrawElements (no state changes) on radeonsi
>
> No meaningless number (which is most likely the same order of
This should go into 18.2 which means also back-porting the header update
which shouldn't be a big deal. I have a feeling DXVK will add a hard
requirement on v3 fairly shortly so it would be good if it works in
released mesa.
On Mon, Sep 10, 2018 at 1:44 PM Jason Ekstrand wrote:
> On Mon, Sep
On Mon, Sep 10, 2018 at 12:11 PM, Dylan Baker wrote:
> I agree that using code from mesa in util is gross, I'm not planning to leave
> it
> like this. I'm in the middle of cleaning up duplication between util and mesa,
> and I'll plan on pulling u_cpu_detection down into src/util in that series.
I've pushed a series of patches to update the VMware gallium driver.
This adds support for MSAA and a few new extensions. See the
docs/vmware-guest.html file for details.
These features depend on the upcoming releases of VMware Workstation 15
and Fusion 11.
-Brian
When a xfb buffer is explicitely declared on a varying
variable, we shouldn't remove it at link time.
Signed-off-by: Samuel Pitoiset
---
src/compiler/nir/nir_linking_helpers.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/src/compiler/nir/nir_linking_helpers.c
On Mon, Sep 10, 2018 at 4:07 AM, Mauro Rossi wrote:
> Hi,
>
> Il giorno lun 10 set 2018 alle ore 09:58 Tapani Pälli
> ha scritto:
>>
>> Marek sent a similar fix here:
>> https://lists.freedesktop.org/archives/mesa-dev/2018-September/204797.html
>
> Thanks a lot!
> So the APU L3 cache
On Mon, Sep 10, 2018 at 8:59 PM Jason Ekstrand wrote:
>
> I recommend CCing stable (I just did on mine) so that it goes into 18.2.
You're right, added the CC in the commit when pushing. This has a
dependency on 34a17a48d440add1da619efd054b50b210cd869b, which hasn't
been marked though.
>
> On
Hi, thanks for the patch.
I've sent version 2 of the patch with additional fixes to this list.
Marek
On Sun, Sep 9, 2018 at 10:08 PM, Josh Pieper wrote:
> And apparently I am incapable of operating git send-email, so it
> failed to include my context:
>
> When using Freecad, I was getting
Using output buffer with 8 bits video RGB as back buffer
certainly is not working for 30 bits color depth visual.
Signed-off-by: Leo Liu
Reviewed-by: Michel Dänzer
---
src/gallium/state_trackers/vdpau/output.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
Signed-off-by: Leo Liu
---
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 29 +++
1 file changed, 25 insertions(+), 4 deletions(-)
diff --git a/src/gallium/auxiliary/vl/vl_winsys_dri3.c
b/src/gallium/auxiliary/vl/vl_winsys_dri3.c
index 8e3c4a0e04d..30e732e38eb 100644
---
For VDPAU use later
Signed-off-by: Leo Liu
Reviewed-by: Michel Dänzer
---
src/gallium/auxiliary/vl/vl_winsys.h | 1 +
src/gallium/auxiliary/vl/vl_winsys_dri3.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/src/gallium/auxiliary/vl/vl_winsys.h
Reviewed-by: Marek Olšák
Marek
On Mon, Sep 10, 2018 at 6:39 AM, Gert Wollny wrote:
> From: Gert Wollny
>
> Gallium may pick L16A16_FLOAT to represent GL_INTENSITY16F if no intensity
> format is provided by the driver. However, when calling
>
>glGetTexLevelParameteriv(...,
I think you don't have to check luminance. Returning just the alpha
bits should be fine.
Marek
On Mon, Sep 10, 2018 at 4:33 PM, Marek Olšák wrote:
> Reviewed-by: Marek Olšák
>
> Marek
>
> On Mon, Sep 10, 2018 at 6:39 AM, Gert Wollny wrote:
>> From: Gert Wollny
>>
>> Gallium may pick
v2: Tell B10G10R10X2 and R10G10B10X2 formats for different HW.
Signed-off-by: Leo Liu
---
src/gallium/auxiliary/vl/vl_winsys.h | 5 ++
src/gallium/auxiliary/vl/vl_winsys_dri.c | 70
2 files changed, 65 insertions(+), 10 deletions(-)
diff --git
Pushed, thanks for the patch!
Marek
On Sat, Sep 8, 2018 at 11:57 PM, Elie Tournier wrote:
> If you don't mind, can you please push this patch for me?
> I don't have git access.
>
> Thanks a lot,
> Elie
> On Fri, 7 Sep 2018 at 22:49, Marek Olšák wrote:
>>
>> Reviewed-by: Marek Olšák
>>
>>
https://bugs.freedesktop.org/show_bug.cgi?id=107869
Marek Olšák changed:
What|Removed |Added
Resolution|--- |FIXED
Status|NEW
---
src/intel/vulkan/anv_extensions.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/intel/vulkan/anv_extensions.py
b/src/intel/vulkan/anv_extensions.py
index 951505a854e..ea090dc3e5c 100644
--- a/src/intel/vulkan/anv_extensions.py
+++
Bump
On 08/29/2018 10:35 PM, Ian Romanick wrote:
> This is mostly a resend of this series. Several patches, noted with
> "v#", have been updated.
>
> Patches 3 and 4 are new. Right before sending the series, I decided to
> update the shader-db results AND update shader-db. The update to
>
On Mon, Sep 10, 2018 at 5:33 PM Bas Nieuwenhuizen
wrote:
> On Mon, Sep 10, 2018 at 8:05 PM Jason Ekstrand
> wrote:
> >
> > The instruction scheduler is re-ordering loads which is causing fence
> > values to be loaded after the value they're fencing. In particular,
> > consider the following
Bump
On 08/29/2018 11:40 AM, Ian Romanick wrote:
> This is mostly a resend of a series that I originally sent out around
> the end of June. I updated some of the shader-db results, and I dropped
> one patch (i965/fs: Allow Boolean conditions in CSEL generation). I
> decided that I want to try
https://bugs.freedesktop.org/show_bug.cgi?id=107873
--- Comment #4 from Ahmed Elsayed ---
I tried also Mesa 18.3 and I have the same problem.
--
You are receiving this mail because:
You are the assignee for the bug.
You are the QA Contact for the
Different ICL SKUs have different URB sizes.
Signed-off-by: Anuj Phogat
---
src/intel/dev/gen_device_info.c | 43 ++---
1 file changed, 29 insertions(+), 14 deletions(-)
diff --git a/src/intel/dev/gen_device_info.c b/src/intel/dev/gen_device_info.c
index
This series implements a code-generation optimization for sign(x)*y. In
GLSL, sign(x) is defined as:
Returns 1.0 if x > 0, 0.0 if x = 0, or -1.0 if x < 0.
It is silent on the NaN behavior, so I have taken it as "undefined." I
don't think the new implementation will produce different
From: Ian Romanick
These allows us to not support fsign.sat in the Intel compiler backend,
and that will simplify some later changes.
No shader-db changes on any Intel platform.
Signed-off-by: Ian Romanick
---
src/compiler/nir/nir_opt_algebraic.py | 1 +
1 file changed, 1 insertion(+)
diff
From: Ian Romanick
All of the affected shaders are in Mad Max. The inner part of the
pattern is itself an open-coded sign(a). I tried using that as a
pattern, but the results were not good. A bunch of shaders were helped
for instructions, but overall cycles, spill, and fills were hurt.
All
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/compiler/nir/nir.h | 23 +++
1 file changed, 23 insertions(+)
diff --git a/src/compiler/nir/nir.h b/src/compiler/nir/nir.h
index bf4bd916d27..69ca1215644 100644
--- a/src/compiler/nir/nir.h
+++ b/src/compiler/nir/nir.h
From: Ian Romanick
Signed-off-by: Ian Romanick
---
src/intel/compiler/brw_fs.h | 1 +
src/intel/compiler/brw_fs_nir.cpp | 154 +-
2 files changed, 103 insertions(+), 52 deletions(-)
diff --git a/src/intel/compiler/brw_fs.h
From: Ian Romanick
shader-db results:
Broadwell and Skylake had similar results. (Skylake shown)
total instructions in shared programs: 15105981 -> 15090997 (-0.10%)
instructions in affected programs: 977852 -> 962868 (-1.53%)
helped: 4531
HURT: 0
helped stats (abs) min: 1 max: 221 x̄: 3.31 x̃:
From: Ian Romanick
Normally fsign generates -1, 0, or +1. The new scale factor, S, causes
fsign to generate -S, 0, or +S.
Signed-off-by: Ian Romanick
---
src/intel/compiler/brw_fs.h | 3 +-
src/intel/compiler/brw_fs_nir.cpp | 61 +++
2 files
From: Ian Romanick
I don't intend to push this. The results are pretty horrifying.
Broadwell
total instructions in shared programs: 15387998 -> 15383192 (-0.03%)
instructions in affected programs: 1223940 -> 1219134 (-0.39%)
helped: 700
HURT: 63
helped stats (abs) min: 1 max: 81 x̄: 7.68 x̃: 5
From: Ian Romanick
All of the affected shaders are in Mad Max. I noticed this while
looking at some other things. I tried a couple similar patterns, but
the affect on cycles was general negative. It may be worth revisiting
this later.
All Gen7+ platforms had similar results. (Skylake shown)
From: Ian Romanick
shader-db results:
All Gen7+ platforms had similar results. (Skylake shown)
total instructions in shared programs: 15106023 -> 15105981 (<.01%)
instructions in affected programs: 300 -> 258 (-14.00%)
helped: 6
HURT: 0
helped stats (abs) min: 7 max: 7 x̄: 7.00 x̃: 7
helped
From: Ian Romanick
This simplifies the later patch "i965/fs: Generate better code for fsign
multiplied by a value".
shader-db results:
Broadwell and Skylake had similar results. (Skylake shown)
total cycles in shared programs: 566050075 -> 566053975 (<.01%)
cycles in affected programs: 1342167
From: Ian Romanick
No shader-db or CI changes on any Intel platform.
Signed-off-by: Ian Romanick
---
src/intel/compiler/brw_fs_nir.cpp | 14 +-
src/intel/compiler/brw_vec4_nir.cpp | 12 ++--
2 files changed, 3 insertions(+), 23 deletions(-)
diff --git
On Mon, Sep 10, 2018 at 5:38 PM Ian Romanick wrote:
> On 09/10/2018 11:04 AM, Jason Ekstrand wrote:
> > The instruction scheduler is re-ordering loads which is causing fence
> > values to be loaded after the value they're fencing. In particular,
> > consider the following pseudocode:
> >
> >
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