On Tue, 2013-10-29 at 13:13 -0700, Eric Anholt wrote:
Josh Klint joshkl...@leadwerks.com writes:
Hi,
As I understand it, Mesa is in charge of providing OpenGL drivers for
Intel graphics hardware running on Linux. I'm in the process of
porting our game engine over to Linux, and have
Removes if/endif and if/else/endif.
total instructions in shared programs: 1366420 - 1356988 (-0.69%)
instructions in affected programs: 160818 - 151386 (-5.87%)
---
Split mistakenly squashed patch.
src/mesa/drivers/dri/i965/Makefile.sources | 1 +
Before this patch, the following code would not be optimized even though
the final two instructions were common to the then and else blocks:
(+f0) IF
MOV dst2 ...
MOV dst1 ...
MOV dst0 ...
ELSE
MOV dst3 ...
MOV dst1 ...
MOV dst0 ...
ENDIF
This commit extends the
One of the things I was wondering about for dota2 performance was
whether missing the fast clears was a big performance hit --
particularly with the fips numbers indicating a lot of time spent in
clears. However, applying this patch:
diff --git a/src/mesa/drivers/dri/i965/brw_blorp_clear.cpp
https://bugs.freedesktop.org/show_bug.cgi?id=71042
Priority: medium
Bug ID: 71042
CC: johannesoberm...@gmx.de, olva...@gmail.com
Assignee: mesa-dev@lists.freedesktop.org
Summary: [ilo] fatal error: brw_structs.h: No such file or
https://bugs.freedesktop.org/show_bug.cgi?id=71042
Fabio Pedretti fabio@libero.it changed:
What|Removed |Added
CC||matts...@gmail.com
From: Marek Olšák marek.ol...@amd.com
This also fixes scalar compare instructions which were always eliminated,
because they didn't have a destination of SCC.
Signed-off-by: Marek Olšák marek.ol...@amd.com
---
lib/Target/R600/SIISelLowering.cpp | 30 ++
https://bugs.freedesktop.org/show_bug.cgi?id=71042
Chia-I Wu olva...@gmail.com changed:
What|Removed |Added
Status|NEW |RESOLVED
From: Marek Olšák marek.ol...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 2 +-
src/gallium/drivers/radeonsi/radeonsi_shader.c | 65 +++---
src/gallium/drivers/radeonsi/si_state.c| 2 +-
src/gallium/drivers/radeonsi/si_state.h| 3 +-
4
Reviewed and Tested-by: Aaron Watry awa...@gmail.com
On Tue, Oct 29, 2013 at 11:48 AM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
The ICD loader should be responsible for installing headers.
---
src/gallium/state_trackers/clover/Makefile.am | 21
On 30 October 2013 00:00, Eric Anholt e...@anholt.net wrote:
One of the things I was wondering about for dota2 performance was
whether missing the fast clears was a big performance hit --
particularly with the fips numbers indicating a lot of time spent in
clears. However, applying this
Am 30.10.2013 14:23, schrieb Marek Olšák:
From: Marek Olšák marek.ol...@amd.com
This also fixes scalar compare instructions which were always eliminated,
because they didn't have a destination of SCC.
Uff, that looks like quite a bit of overhead, isn't there a simpler
approach? Like setting
I thought that doing S_CMPK followed by S_CBRANCH has less overhead
than doing a memory read. If we used one of
S_BUFFER_LOAD_DWORDX2,4,8,16, it wouldn't be so bad. I don't know.
Marek
On Wed, Oct 30, 2013 at 2:48 PM, Christian König
deathsim...@vodafone.de wrote:
Am 30.10.2013 14:23, schrieb
On 10/29/2013 07:07 PM, Ian Romanick wrote:
From: Ian Romanick ian.d.roman...@intel.com
These will be used to determine whether to signal a GPU reset after
another context in the share group has observed a reset.
Signed-off-by: Ian Romanick ian.d.roman...@intel.com
---
diff --git a/src/gallium/drivers/r600/evergreen_compute.c
b/src/gallium/drivers/r600/evergreen_compute.c
index ea77f5e..ffdc5c3 100644
--- a/src/gallium/drivers/r600/evergreen_compute.c
+++ b/src/gallium/drivers/r600/evergreen_compute.c
@@ -392,7 +392,6 @@ static void compute_emit_cs(struct
diff --git a/src/egl/wayland/wayland-drm/wayland-drm.c
b/src/egl/wayland/wayland-drm/wayland-drm.c
index 2f5acb2..e9c6e0a 100644
--- a/src/egl/wayland/wayland-drm/wayland-drm.c
+++ b/src/egl/wayland/wayland-drm/wayland-drm.c
@@ -247,8 +247,6 @@ bind_drm(struct wl_client *client, void *data,
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
index b52d646..2ae5818 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_gs.c
+++ b/src/mesa/drivers/dri/i965/brw_vec4_gs.c
@@ -283,9 +283,7 @@ brw_upload_gs_prog(struct brw_context *brw)
if
On Wed, Oct 30, 2013 at 2:43 PM, Paul Berry stereotype...@gmail.com wrote:
- What percentage of clears are affected by this patch? Even with this
patch, some clears still won't take the fast path (e.g. stencil clears, MSAA
color clears, and scissored clears).
When I was doing my Wine tweaks
Mhm, I'm assumed that having NumRecord zero is actually something quite
unusual. E.g. a shader that accesses a not defined constant buffer or
something like that. So I would rather optimize for the common use case.
Anyway branch instructions are quite expensive, you can issue something
On 10/30/2013 06:43 AM, Paul Berry wrote:
On 30 October 2013 00:00, Eric Anholt e...@anholt.net wrote:
One of the things I was wondering about for dota2 performance was
whether missing the fast clears was a big performance hit --
particularly with the fips numbers indicating a lot of time
All the patches look fine.
I think they are ready for merging (there are few trailing whitespace
errors when applying, but nothing bad).
We want these patches for Wayland Prime support, and it should be useful
too for X Dri3.
Axel Davy
___
Hi Tom
On Tue, Oct 29, 2013 at 9:00 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
DRM_IOCTL_VERSION is not currently a legal ioctl for render nodes, so we
need to hard code the drm version when drmGetVersion() returns NULL.
---
Hi Tom
On Tue, Oct 29, 2013 at 9:00 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
You can use the --enable-pipe-loader-render-nodes configure flag to
make the pipe-loader use render nodes for talking with the device.
---
configure.ac
Please send patches using git-send-email and no other means. Patches
sent as attachments can't get in-line review comments. That said...
NAK this patch. Putting the function call in the assert means that the
function won't get called in non-debug builds. That will break
everything. Maybe
R600/R700 implementation of tex buffer fetch requires the result of the VFETCH
instruction to be ANDed with R600_BUFFER_INFO_CONST_BUFFER, and the last channel
to be ORed with the same const buffer.
---
src/gallium/drivers/r600/r600_llvm.c | 29 +
1 file changed, 29
On R600/R700 hw the data are stored from the channel 2 of the second dword.
---
src/gallium/drivers/r600/r600_llvm.c | 15 ++-
1 file changed, 14 insertions(+), 1 deletion(-)
diff --git a/src/gallium/drivers/r600/r600_llvm.c
b/src/gallium/drivers/r600/r600_llvm.c
index
On 29 October 2013 17:23, Matt Turner matts...@gmail.com wrote:
On Tue, Oct 29, 2013 at 2:32 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Mon, Oct 28, 2013 at 11:31:32AM -0700, Matt Turner wrote:
---
src/mesa/drivers/dri/i965/brw_fs.cpp | 30
++
Yeah, it's unusual.
What if S_BUFFER_LOAD is also used by something else, like texture
buffers, or OpenCL? Will we have to fix that as well?
Marek
On Wed, Oct 30, 2013 at 3:32 PM, Christian König
deathsim...@vodafone.de wrote:
Mhm, I'm assumed that having NumRecord zero is actually something
On Wed, Oct 30, 2013 at 8:59 AM, Paul Berry stereotype...@gmail.com wrote:
On 29 October 2013 17:23, Matt Turner matts...@gmail.com wrote:
On Tue, Oct 29, 2013 at 2:32 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Mon, Oct 28, 2013 at 11:31:32AM -0700, Matt Turner wrote:
---
Off hand I don't know any use case exept constant buffers where we use
S_BUFFER_LOAD, but anybody who uses it should be aware how to use it.
What are the symptoms of issuing a S_BUFFER_LOAD with NumRecords=0?
Hangs or just undefined behaviour?
Christian.
Am 30.10.2013 17:00, schrieb Marek
The symptom is a VM protection fault with the address of 0 (probably
because the whole descriptor contains zeros), which
should be harmless, but it spams dmesg.
Marek
On Wed, Oct 30, 2013 at 5:19 PM, Christian König
deathsim...@vodafone.de wrote:
Off hand I don't know any use case exept
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
fs_visitor::try_replace_with_sel optimizes only if statements whose
then and else bodies contain a single MOV instruction. It also did
could not handle constant arguments, since they cause an extra MOV
s/did could not/could not/
https://bugs.freedesktop.org/show_bug.cgi?id=69874
--- Comment #6 from Shriram V shri...@yahoo.com ---
bin_PROGRAMS = abc
abc_SOURCES = sub/main.c sub/abc.c
When you set subdir-objects, it always creates object files in the same dir as
the source file. E.g: sub/main.o, sub/abc.o
So, its
https://bugs.freedesktop.org/show_bug.cgi?id=71042
Matt Turner matts...@gmail.com changed:
What|Removed |Added
CC|matts...@gmail.com |
--
You are receiving
Hi Vincent,
It turns out that it's not possible to correctly schedule uses and defs
of the OQAP register without proper alias analysis in the MachineScheduler. See
the explanation in the lds-output-queue.ll test case.
Here is an updated patch that fixes all the outstanding LDS scheduling
bugs
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
fs_visitor::try_replace_with_sel optimizes only if statements whose
then and else bodies contain a single MOV instruction. It also did
could not handle constant arguments, since they cause an extra MOV
immediate to be generated
On Wed, Oct 30, 2013 at 9:30 AM, Paul Berry stereotype...@gmail.com wrote:
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
fs_visitor::try_replace_with_sel optimizes only if statements whose
then and else bodies contain a single MOV instruction. It also did
could not handle
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
total instructions in shared programs: 1287488 - 1287457 (-0.00%)
instructions in affected programs: 1745 - 1714 (-1.78%)
---
src/mesa/drivers/dri/i965/brw_fs_sel_peephole.cpp | 38
+--
1 file changed,
On Wed, Oct 30, 2013 at 10:06 AM, Paul Berry stereotype...@gmail.com wrote:
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
fs_visitor::try_replace_with_sel optimizes only if statements whose
then and else bodies contain a single MOV instruction. It also did
could not handle
On 30 October 2013 10:10, Matt Turner matts...@gmail.com wrote:
On Wed, Oct 30, 2013 at 9:30 AM, Paul Berry stereotype...@gmail.com
wrote:
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
fs_visitor::try_replace_with_sel optimizes only if statements whose
then and else
On Wed, Oct 30, 2013 at 08:15:43AM +0100, David Herrmann wrote:
Hi Tom
On Tue, Oct 29, 2013 at 9:00 PM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
You can use the --enable-pipe-loader-render-nodes configure flag to
make the pipe-loader use render
On 29 October 2013 23:37, Matt Turner matts...@gmail.com wrote:
Before this patch, the following code would not be optimized even though
the final two instructions were common to the then and else blocks:
(+f0) IF
MOV dst2 ...
MOV dst1 ...
MOV dst0 ...
ELSE
MOV dst3 ...
On 30 October 2013 10:23, Paul Berry stereotype...@gmail.com wrote:
On 30 October 2013 10:10, Matt Turner matts...@gmail.com wrote:
On Wed, Oct 30, 2013 at 9:30 AM, Paul Berry stereotype...@gmail.com
wrote:
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
On 28 October 2013 11:31, Matt Turner matts...@gmail.com wrote:
The pass previously searched only backward from an ENDIF (and ELSE) to
find MOVs with the same destination. This commit extends the pass to
also search forward from the IF (and ELSE) to find matching MOVs which
it can replace
On 28 October 2013 11:33, Matt Turner matts...@gmail.com wrote:
The first six patches have been on the list previously, but it got
confusing when they changed order and some were dropped.
The last nine patches implement a new SEL-generating peephole, a dead
flow control elimination pass, and
https://bugs.freedesktop.org/show_bug.cgi?id=69874
--- Comment #7 from Emil Velikov emil.l.veli...@gmail.com ---
(In reply to comment #6)
bin_PROGRAMS = abc
abc_SOURCES = sub/main.c sub/abc.c
When you set subdir-objects, it always creates object files in the same dir
as the source file.
On Tue, Oct 29, 2013 at 10:04 PM, Paul Berry stereotype...@gmail.com wrote:
On 29 October 2013 19:22, Anuj Phogat anuj.pho...@gmail.com wrote:
On Mon, Oct 28, 2013 at 5:10 PM, Paul Berry stereotype...@gmail.com
wrote:
On 25 October 2013 16:45, Anuj Phogat anuj.pho...@gmail.com wrote:
On 28 October 2013 14:19, Eric Anholt e...@anholt.net wrote:
This only operates on constant/uniform values for now, because otherwise
I'd
have to deal with killing my available CSE entries when assignments happen,
and getting even this working in the tree ir was painful enough.
As is, it
Fredrik Höglund fred...@kde.org writes:
This extension decouples the vertex attributes from the vertex buffer
bindings, making it possible to change buffers without having to
respecify the formats. The mapping between attributes and vertex
buffer bindings also becomes configurable.
Patch 5
Hello all,
I've got some questions and I would appreciate if anyone could help me out.
Here goes:
I've been digging through brw_try_draw_prims(), and trying to figure out what
it is doing, so far this is what I see:
1) it is essentially called each time a non-degenerate real drawing
On 28 October 2013 15:34, Eric Anholt e...@anholt.net wrote:
When faced with a million instructions that all became candidates at the
same time (none of which individually reduce register pressure), the ones
on the critical path are more likely to be the ones that will free up some
candidates
On 29 October 2013 13:28, Eric Anholt e...@anholt.net wrote:
I believe this will never happen in SIMD8 mode, but it could for SIMD16
when we fix it.
---
src/mesa/drivers/dri/i965/brw_fs.h| 1 +
src/mesa/drivers/dri/i965/brw_fs_reg_allocate.cpp | 23
+++
On 29 October 2013 13:28, Eric Anholt e...@anholt.net wrote:
This is a resend of the series after updates for Paul's review feedback.
This time I've done a full piglit run with spilling forced on and no
regressions were found. It can also be found at gen7-scratch-read of my
tree.
I
On 30 October 2013 12:15, Paul Berry stereotype...@gmail.com wrote:
On 29 October 2013 13:28, Eric Anholt e...@anholt.net wrote:
This is a resend of the series after updates for Paul's review feedback.
This time I've done a full piglit run with spilling forced on and no
regressions were
On 30 October 2013 11:55, Rogovin, Kevin kevin.rogo...@intel.com wrote:
Hello all,
I've got some questions and I would appreciate if anyone could help me
out. Here goes:
I've been digging through brw_try_draw_prims(), and trying to figure out
what it is doing, so far this is what I see:
Vedran,
Just to add a bit more context -- programming a strange viewport
causes us to turn off guardband clipping. I haven't measured the
impact on dota2, but when it was initially enabled it was a nice win
for some other games.
-- Chris
On Thu, Oct 31, 2013 at 3:38 AM, Chad Versace
From: Marek Olšák marek.ol...@amd.com
---
The UBO series continues here.
This is an alternative solution to scalar-memory-read hw bug.
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 22 ++
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 1 +
Please disregard this patch. I've implemented the workaround in Mesa
as Christian suggested.
Marek
On Wed, Oct 30, 2013 at 5:19 PM, Christian König
deathsim...@vodafone.de wrote:
Off hand I don't know any use case exept constant buffers where we use
S_BUFFER_LOAD, but anybody who uses it
Thanks, patch is committed.
___
mesa-dev mailing list
mesa-dev@lists.freedesktop.org
http://lists.freedesktop.org/mailman/listinfo/mesa-dev
For the sake of git-describe, I propose we tag the 10.0 fork
point on master as 'mesa-10.0-fork', 'mesa-10.0-base', or
something similair. How do people feel about that?
It's been a long time since git-describe has given useful
info. It's reported snb-magic for a long time.
$
On 10/30/2013 01:01 PM, Chad Versace wrote:
For the sake of git-describe, I propose we tag the 10.0 fork
point on master as 'mesa-10.0-fork', 'mesa-10.0-base', or
something similair. How do people feel about that?
I support this idea.
To avoid confusion with tags on the branch, I think the
On 30 October 2013 14:13, Ian Romanick i...@freedesktop.org wrote:
On 10/30/2013 01:01 PM, Chad Versace wrote:
For the sake of git-describe, I propose we tag the 10.0 fork
point on master as 'mesa-10.0-fork', 'mesa-10.0-base', or
something similair. How do people feel about that?
I
https://bugs.freedesktop.org/show_bug.cgi?id=71022
--- Comment #9 from Rob Clark robcl...@freedesktop.org ---
fwiw, this would be nice to push.. it would at least fix my tinderbox:
http://tinderbox.x.org/builds/2013-10-30-0017/logs/libGL/#configure
--
You are receiving this mail because:
You
fix: intel_screen.c:1320:4: warning: initialization from
incompatible pointer type [enabled by default]
---
src/mesa/drivers/dri/i965/brw_context.c | 2 +-
src/mesa/drivers/dri/i965/brw_context.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git
https://bugs.freedesktop.org/show_bug.cgi?id=71022
Emil Velikov emil.l.veli...@gmail.com changed:
What|Removed |Added
Status|NEW |RESOLVED
Previously, the write of each 32-bit half might land in separate batch
buffers, which is insane.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/drivers/dri/i965/gen6_queryobj.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git
Previously, when doing intrastage and interstage interface block
linking, we only checked the interface type; this prevented us from
catching some link errors.
We now check the following additional constraints:
- For intrastage linking, the presence/absence of interface names must
match.
-
On Tue, Oct 29, 2013 at 08:34:16PM +0100, Kai Wasserb??ch wrote:
Tom Stellard schrieb am 29.10.2013 17:48:
On Sun, Oct 27, 2013 at 07:36:07PM +0100, Kai Wasserb??ch wrote:
Fixes a boat load of Piglit tests for me, which crashed like fdo#70913
before.
Thanks to Michel D??nzer for the
On Wed, Oct 30, 2013 at 08:38:37AM -0500, Aaron Watry wrote:
Reviewed and Tested-by: Aaron Watry awa...@gmail.com
I have pushed this patch, thanks for testing.
On Tue, Oct 29, 2013 at 11:48 AM, Tom Stellard t...@stellard.net wrote:
From: Tom Stellard thomas.stell...@amd.com
The ICD
On Mon, Oct 28, 2013 at 11:59:51AM -0500, Aaron Watry wrote:
I just ran a quick.tests run on evergreen without any regressions.
Patch looks good to me, and doesn't seem to cause any regressions on
the hardware I have available to test with.
I have pushed this patch, thanks for testing.
That is indeed insane :)
Reviewed-by: Chris Forbes chr...@ijw.co.nz
On Thu, Oct 31, 2013 at 12:17 PM, Kenneth Graunke kenn...@whitecape.org wrote:
Previously, the write of each 32-bit half might land in separate batch
buffers, which is insane.
Signed-off-by: Kenneth Graunke
Previously, when packing geometry shader input varyings like this:
in float foo[3];
in float bar[3];
lower_packed_varyings would declare a packed varying like this:
(declare (shader_in flat) (array ivec4 3) packed:foo[0],bar[0])
That's confusing, since the packed varying acutally
Kenneth Graunke kenn...@whitecape.org writes:
Would you mind adding the mesa: prefix to the commit title?
I wouldn't mind at all. Thanks for the reminder. Only, I did happen to
push out that commit before I got your message. :-P
-ASSERT(!q-Active); /* should be caught earlier */
Prior to the GLSL CSE pass, all of our testing happened to have a freshly
computed temporary in op[1], from the multiply by 16 to get a byte offset.
As of CSE you'll get var_refs of a reused value when you've got multiple
loads from the same offset.
Make a proper temporary for computing our
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