Kenneth Graunke kenn...@whitecape.org writes:
On Friday, March 27, 2015 01:54:32 PM Eric Anholt wrote:
This will be used by the VC4 driver for doing device-independent
optimization, and hopefully eventually replacing its whole IR. It also
may be useful to other drivers for the same reason.
From: Dave Airlie airl...@redhat.com
At the moment to get an EGL image to a dma-buf file descriptor,
you have to use EGL_MESA_drm_image, and then use libdrm to
convert this to a file descriptor.
This extension just provides an API modelled on EGL_MESA_drm_image,
to return a dma-buf file
Kenneth Graunke kenn...@whitecape.org writes:
Mostly a proof of concept that it works; we free the memory shortly
afterwards anyway, so it's kind of dumb to do this.
The plan is to instead build nir_shaders at link time, rather than when
compiling each shader specialization, and delete the
Hi, Emil:
On 25 March 2015 at 08:05, Xiong Zhang xiong.y.zh...@intel.com wrote:
GLX_ARB_create_context spec says:
If either draw or read are not a valid GLX drawable, a
GLXBadDrawable error is generated, unless draw and read are both
None and the OpenGL version supported by ctx is
Hello +Laura, +Brian,
I will like you to register on melange with X.org so as to mentor me on
the Porting Glean tests to piglit project for GSoC 2015. The Mentor +Martin
Peres requested I inform you to register.
Thanks,
Juliet
___
mesa-dev
On 30/03/15 02:05, Eric Anholt wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
The header was added with commit 2a135c470e3(nir: Add an ALU op builder
kind of like ir_builder.h) but did not made it into to the sources list,
and its dependency of nir_builder_opcodes.h was missing.
On 29/03/15 00:56, Emil Velikov wrote:
Both of which were removed with commit 69db422218b(scons: Don't build
osmesa.)
Cc: Jose Fonseca jfons...@vmware.com
Signed-off-by: Emil Velikov emil.l.veli...@gmail.com
---
src/mesa/drivers/osmesa/Makefile.am | 2 --
1 file changed, 2 deletions(-)
diff
On 30/03/15 07:10, Zhang, Xiong Y wrote:
Hi, Emil:
On 25 March 2015 at 08:05, Xiong Zhang xiong.y.zh...@intel.com wrote:
GLX_ARB_create_context spec says:
If either draw or read are not a valid GLX drawable, a
GLXBadDrawable error is generated, unless draw and read are both
None and the
https://bugs.freedesktop.org/show_bug.cgi?id=89823
Bug ID: 89823
Summary: [swrast] driver loads but complains then fails to work
in Piglit which shows GLSL message
Product: Mesa
Version: git
Hardware: Other
https://bugs.freedesktop.org/show_bug.cgi?id=89818
Luke lukebe...@hotmail.com changed:
What|Removed |Added
URL||https://www.khronos.org/reg
This mutex is used to make sure the shared context does not change
while some shared code is looking into it.
Calling BindRenderbufferEXT BindRenderbuffer with a gles context
would not take the mutex before allocating an entry. Commit a34669b
then moved out the allocation out of bind_renderbuffer
On 27/03/15 17:40, Ilia Mirkin wrote:
On Fri, Mar 27, 2015 at 4:19 AM, Martin Peres
martin.pe...@linux.intel.com wrote:
On 27/03/15 07:13, Ilia Mirkin wrote:
On Fri, Mar 27, 2015 at 1:06 AM, Vinson Lee v...@freedesktop.org wrote:
On Mon, Feb 16, 2015 at 6:14 AM, Martin Peres
The issue has been detected by coverty.
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
---
src/mesa/main/fbobject.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
index 072e1a8..5f9a6db 100644
---
It is hard finding a statement or direct quote from Thomas
on the licensing of his algorithm.
I tried the 6 shift algorithm Bob suggests this morning before work.
It seems Thomas' algorithm inlines very nicely, giving the boost.
Bob's version probably gives more collisions, as the time spent
in
On 30/03/15 01:12, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
Just announce support for 4 components.
While here also increase the max/min texel offsets (the limit is completely
artificial, was chosen because that's what other hardware did, however there's
other
On 28/03/15 19:53, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
This has got a bit out of control with more and more parameters added.
Worse, whenever something in there changes all callees have to be updated
for that, even though they don't really do much with any
Iago Toral Quiroga ito...@igalia.com writes:
This is a problem when we have IR like this:
(array_ref (var_ref temps) (swiz x (expression ivec4 bitcast_f2i
(swiz (array_ref (var_ref temps) (constant int (2)) ) )) )) ) )
where we are indexing an array with the result of an expression
On 03/29/2015 06:11 PM, Martin Peres wrote:
On 29/03/2015 17:56, Samuel Pitoiset wrote:
On 03/28/2015 09:43 PM, Martin Peres wrote:
On 22/03/2015 17:35, Samuel Pitoiset wrote:
From: Christoph Bumiller e0425...@student.tuwien.ac.at
This is based on the original patch of Christoph Bumiller.
On 27 March 2015 at 01:05, Michel Dänzer mic...@daenzer.net wrote:
From: Michel Dänzer michel.daen...@amd.com
Fixes a crash in genymotion with several threads compiling shaders
concurrently.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89746
Cc: 10.5
https://bugs.freedesktop.org/show_bug.cgi?id=89823
Kai k...@dev.carbon-project.org changed:
What|Removed |Added
Keywords||regression
--- Comment
On Friday 27 March 2015 20:46:38 Ben Widawsky wrote:
On Thu, Dec 11, 2014 at 11:34:12PM +0100, Eduardo Lima Mitev wrote:
From: Samuel Iglesias Gonsalvez sigles...@igalia.com
When a vec has more elements than row components in a matrix, the
code could end up failing an assert inside
On 03/30/2015 02:25 AM, Martin Peres wrote:
The issue has been detected by coverty.
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
---
src/mesa/main/fbobject.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/mesa/main/fbobject.c b/src/mesa/main/fbobject.c
On 30/03/15 18:00, Brian Paul wrote:
On 03/30/2015 02:25 AM, Martin Peres wrote:
The issue has been detected by coverty.
Signed-off-by: Martin Peres martin.pe...@linux.intel.com
---
src/mesa/main/fbobject.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On 03/30/2015 02:25 AM, Martin Peres wrote:
This mutex is used to make sure the shared context does not change
while some shared code is looking into it.
Calling BindRenderbufferEXT BindRenderbuffer with a gles context
would not take the mutex before allocating an entry. Commit a34669b
then
Perhaps mention that llvmpipe now supports ARB_texture_gather in
GL3.txt and relnotes/10.6.0.html?
On Sun, Mar 29, 2015 at 8:12 PM, srol...@vmware.com wrote:
From: Roland Scheidegger srol...@vmware.com
Just announce support for 4 components.
While here also increase the max/min texel offsets
On Mon, Mar 30, 2015 at 9:49 AM, Eric Anholt e...@anholt.net wrote:
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI-NIR and NIR-TGSI.
Otherwise, we had to pull in all of mtypes.h.
This doesn't cover all of the enums we
On Mon, Mar 30, 2015 at 9:58 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 30 March 2015 at 17:37, Eric Anholt e...@anholt.net wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
On 30/03/15 02:05, Eric Anholt wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
...
diff --git
I'm going to look over this but it may not happen until later in the week.
We should also get at least an ack from Eric.
--Jason
On Mar 29, 2015 1:06 PM, Thomas Helland thomashellan...@gmail.com wrote:
Here's the latest round of fixup on the hash-table patches.
I think I've gotten all the
v2:
- Don't use _errs map
Cc: 10.5 10.4 mesa-sta...@lists.freedesktop.org
---
src/gallium/state_trackers/clover/core/program.cpp | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/gallium/state_trackers/clover/core/program.cpp
b/src/gallium/state_trackers/clover/core/program.cpp
index
More will be added to this structure in a later commit. The main
purpose of this struct is to enable more efficient parsing of llvm modules.
It will allow us to collect all kernel information for each function
with only one pass through the module's metadata. OpenCL metadata for
kernels is
This patch enables clover to return the correct value for
CL_KERNEL_COMPILE_WORK_GROUP_SIZE and also verify that the correct
local_work_size is used when enqueuing kernels with this attribute.
v2:
- Store the work group size as part of the symbol rather than as a
kernel argument.
---
Emil Velikov emil.l.veli...@gmail.com writes:
On 30/03/15 02:05, Eric Anholt wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
The header was added with commit 2a135c470e3(nir: Add an ALU op builder
kind of like ir_builder.h) but did not made it into to the sources list,
and its
This consolidates signalled checks into the same place.
---
src/gallium/state_trackers/clover/core/event.cpp | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/state_trackers/clover/core/event.cpp
b/src/gallium/state_trackers/clover/core/event.cpp
index
On 30 March 2015 at 18:10, Matt Turner matts...@gmail.com wrote:
On Mon, Mar 30, 2015 at 9:58 AM, Emil Velikov emil.l.veli...@gmail.com
wrote:
On 30 March 2015 at 17:37, Eric Anholt e...@anholt.net wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
On 30/03/15 02:05, Eric Anholt wrote:
On Mon, Mar 30, 2015 at 10:23 AM, Emil Velikov emil.l.veli...@gmail.com wrote:
On 30 March 2015 at 18:10, Matt Turner matts...@gmail.com wrote:
No, it doesn't make sense. Presumably you added it because it fixed a
build error? Maybe if you showed what the error was it would make
sense.
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI-NIR and NIR-TGSI.
Otherwise, we had to pull in all of mtypes.h.
This doesn't cover all of the enums we might want from a shared compiler
core (like varying slots or vert attribs),
On 30 March 2015 at 17:37, Eric Anholt e...@anholt.net wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
On 30/03/15 02:05, Eric Anholt wrote:
Emil Velikov emil.l.veli...@gmail.com writes:
...
diff --git a/src/glsl/Makefile.am b/src/glsl/Makefile.am
index ed90366..58af166 100644
---
Series is
Reviewed-by: Connor Abbott cwabbo...@gmail.com
On Mon, Mar 30, 2015 at 1:12 PM, Eric Anholt e...@anholt.net wrote:
Since we have patterns based on b2f, generate them if we see the b2f
equivalent using an iand. This is common when generating NIR from TGSI.
---
Since we have patterns based on b2f, generate them if we see the b2f
equivalent using an iand. This is common when generating NIR from TGSI.
---
src/glsl/nir/nir_opt_algebraic.py | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/glsl/nir/nir_opt_algebraic.py
TGSI's conditional discards take float arg and negate it, so GLSL to TGSI
generates a b2f and negates that value. Only, in NIR we want a proper
bool once again, so we compare with 0. This is a lot of pointless extra
instructions.
total instructions in shared programs: 39735 - 39702 (-0.08%)
It was possible for some events never to get triggered if one thread
was creating events and another threads was waiting for them.
This patch consolidates soft_event::wait() and hard_event::wait()
into event::wait() so that hard_event objects will now wait for
all their dependencies to be
v2:
- Only call notification for build errors
- Fix clCompileProgram()
Cc: 10.5 10.4 mesa-sta...@lists.freedesktop.org
---
src/gallium/state_trackers/clover/api/program.cpp | 16 ++--
1 file changed, 14 insertions(+), 2 deletions(-)
diff --git
On 03/30/2015 10:49 AM, Eric Anholt wrote:
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI-NIR and NIR-TGSI.
Otherwise, we had to pull in all of mtypes.h.
This doesn't cover all of the enums we might want from a shared
On 30 March 2015 at 18:34, Matt Turner matts...@gmail.com wrote:
On Mon, Mar 30, 2015 at 10:23 AM, Emil Velikov emil.l.veli...@gmail.com
wrote:
On 30 March 2015 at 18:10, Matt Turner matts...@gmail.com wrote:
No, it doesn't make sense. Presumably you added it because it fixed a
build error?
On Monday, March 30, 2015 11:44:19 AM Eric Anholt wrote:
Brian Paul bri...@vmware.com writes:
On 03/30/2015 10:49 AM, Eric Anholt wrote:
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI-NIR and NIR-TGSI.
Otherwise, we
Brian Paul bri...@vmware.com writes:
On 03/30/2015 10:49 AM, Eric Anholt wrote:
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI-NIR and NIR-TGSI.
Otherwise, we had to pull in all of mtypes.h.
This doesn't cover all of the
Matt Turner matts...@gmail.com writes:
On Mon, Mar 30, 2015 at 9:49 AM, Eric Anholt e...@anholt.net wrote:
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use them from TGSI-NIR and NIR-TGSI.
Otherwise, we had to pull in all of mtypes.h.
On Sat, Mar 28, 2015 at 11:03 AM, Jason Ekstrand ja...@jlekstrand.net wrote:
On Fri, Mar 27, 2015 at 9:22 PM, Matt Turner matts...@gmail.com wrote:
The typical case of mat4*mat4*vec4 is 80 scalar multiplications, but
mat4*(mat4*vec4) is only 32.
On HSW (with vec4 vertex shaders):
The framerate will be used for video usability info support by VCE driver
Signed-off-by: Leo Liu leo@amd.com
---
src/gallium/state_trackers/omx/vid_enc.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/src/gallium/state_trackers/omx/vid_enc.c
This will help encoding VUI into the bitstream
Signed-off-by: Leo Liu leo@amd.com
---
src/gallium/drivers/radeon/radeon_vce.c| 1 +
src/gallium/drivers/radeon/radeon_vce.h| 1 +
src/gallium/drivers/radeon/radeon_vce_40_2_2.c | 52 ++
3 files changed,
You can add a flag to each driver query identifying what kind of query
it is (a hw perf counter or a CPU-only query). Then you can enumerate
all queries and see if there's at least one perf counter and if so,
advertise the extension.
Or add a CAP and let drivers decide if they want the extension
On 03/30/2015 03:46 PM, Eric Anholt wrote:
Kenneth Graunke kenn...@whitecape.org writes:
On Monday, March 30, 2015 11:44:19 AM Eric Anholt wrote:
Brian Paul bri...@vmware.com writes:
On 03/30/2015 10:49 AM, Eric Anholt wrote:
NIR uses these enums/#defines in nir_variables and associated
On Mon, Mar 30, 2015 at 2:04 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
This series enables skl+ to read/write data to YF/YF tiled
surfaces. Many piglit tests for texture/buffer data read/write
pass with the new tiling formats. I'm currently debugging an
issue about incorrect data getting
This series enables skl+ to read/write data to YF/YF tiled
surfaces. Many piglit tests for texture/buffer data read/write
pass with the new tiling formats. I'm currently debugging an
issue about incorrect data getting uploaded to miplevels 0.
I thought it'll useful to get some review comments
This will allow Skylake to use _mesa_meta_pbo_GetTexSubImage() for reading YF/YS
tiled surfaces.
V2: Make changes suggested by Neil.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
Cc: Neil Roberts n...@linux.intel.com
---
src/mesa/drivers/common/meta.h | 1 +
From: Anuj phogat anuj.pho...@gmail.com
Patch continues code refactoring.
Signed-off-by: Anuj phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 105 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 104 -
From: Anuj phogat anuj.pho...@gmail.com
and some more code refactoring. No functional changes in this patch.
Signed-off-by: Anuj phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 89 --
1 file changed, 48 insertions(+), 41 deletions(-)
Note: Buffer size condition used in this patch to choose between
YF / YS tiling is just a place holder. I need some suggestions
here.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 79 ++
1 file changed, 79
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 28
1 file changed, 20 insertions(+), 8 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c
b/src/mesa/drivers/dri/i965/intel_tex_image.c
index
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 18 --
1 file changed, 8 insertions(+), 10 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 1c9f2fe..499c2dc
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 7 ---
src/mesa/drivers/dri/i965/intel_tex_image.c | 15 ---
2 files changed, 22 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c
Currently, that's the only path that supports reading data from these buffers.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git
From: Anuj phogat anuj.pho...@gmail.com
Patch sets the alignments for texture and renderbuffer surfaces.
Signed-off-by: Anuj phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 28 ++
1 file changed, 24 insertions(+), 4 deletions(-)
diff
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
b/src/mesa/drivers/dri/i965/gen8_surface_state.c
index 7f82f53..97f9422 100644
---
This fixed the buffer corruption happening in a FBO which use YF/YS
tiled renderbuffer or texture as color attachment.
BSpec recommends disabling mip tails for non-mip-mapped surfaces.
But, with this enabled I couldn't get correct data out of YF/YS
tiled surface.
With this disabled, miplevel 0
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 39fb3b1..c4fd3a2 100644
---
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_blit.c | 293 +++
src/mesa/drivers/dri/i965/intel_blit.h | 3 +
src/mesa/drivers/dri/i965/intel_copy_image.c | 3 +
src/mesa/drivers/dri/i965/intel_reg.h| 33 +++
Conditions modified allow skl+ to use blitter:
- for all tiling formats
- to write data to YF/YS tiled surfaces
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 14 +++---
1 file changed, 11 insertions(+), 3 deletions(-)
diff --git
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 80 ++
1 file changed, 80 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index eab3884..39fb3b1
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 2 ++
src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 6 ++
2 files changed, 8 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
No other path currently supports uploading data to these surfaces.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_tex_image.c | 24 ++--
1 file changed, 22 insertions(+), 2 deletions(-)
diff --git
From: Anuj phogat anuj.pho...@gmail.com
This refactoring is required by later patches in this series.
Signed-off-by: Anuj phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 13 -
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 23 ++-
This function will be utilised in later patches.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_context.h| 4
src/mesa/drivers/dri/i965/brw_tex_layout.c | 10 +-
2 files changed, 9 insertions(+), 5 deletions(-)
diff --git
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 75 ++
1 file changed, 75 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index c4fd3a2..b3d7c1b
From: Anuj phogat anuj.pho...@gmail.com
This patch sets the tiled resource mode for texture and renderbuffer
surfaces.
Signed-off-by: Anuj phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/brw_defines.h| 8
src/mesa/drivers/dri/i965/gen8_surface_state.c | 22
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index fac7b8e..ef6ff11
Makes no functional changes in the code.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/gen8_surface_state.c | 13 -
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/gen8_surface_state.c
Kenneth Graunke kenn...@whitecape.org writes:
On Monday, March 30, 2015 11:44:19 AM Eric Anholt wrote:
Brian Paul bri...@vmware.com writes:
On 03/30/2015 10:49 AM, Eric Anholt wrote:
NIR uses these enums/#defines in nir_variables and associated intrinsics,
but I want to be able to use
https://bugs.freedesktop.org/show_bug.cgi?id=89823
--- Comment #3 from Dan Sebald daniel.seb...@ieee.org ---
[@ mesa]$ LIBGL_DEBUG=verbose glxinfo | grep direct
libGL: OpenDriver: trying /usr/lib64/dri/nouveau_dri.so
libGL error: dlopen /usr/lib64/dri/nouveau_dri.so failed
On Mon, Mar 30, 2015 at 2:42 PM, Matt Turner matts...@gmail.com wrote:
On Mon, Mar 30, 2015 at 2:04 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
This series enables skl+ to read/write data to YF/YF tiled
surfaces. Many piglit tests for texture/buffer data read/write
pass with the new tiling
https://bugs.freedesktop.org/show_bug.cgi?id=89823
--- Comment #2 from Timothy Arceri t_arc...@yahoo.com.au ---
Looks like no driver is loaded. Try using LIBGL_DEBUG=verbose it should tell
you where your system is looking to load them from.
For example:
$ LIBGL_DEBUG=verbose glxinfo | grep
V2: Make relevant changes in intelTexSubImage().
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_pixel_read.c | 7 ---
src/mesa/drivers/dri/i965/intel_tex_image.c| 15 ---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 7 ---
3
Both are
Reviewed-by: Matt Turner matts...@gmail.com
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On 30.03.2015 22:28, Emil Velikov wrote:
On 27 March 2015 at 01:05, Michel Dänzer mic...@daenzer.net wrote:
From: Michel Dänzer michel.daen...@amd.com
Fixes a crash in genymotion with several threads compiling shaders
concurrently.
Bugzilla:
ptn_move_dest and nir_fadd already take care of replicating the last
channel out, so we can just use a scalar and skip splatting it.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/program/prog_to_nir.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git
InputsRead is a 64-bit bitfield. Using _mesa_fls would silently
truncate off the high bits, claiming inputs 32..56 (VARYING_SLOT_MAX)
were never read.
Using = here was a hack I threw in at the last minute to fix programs
which happened to use input slot 32. Switch back to using now that
the
This is _mesa_fls() for 64-bit values.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
---
src/mesa/main/imports.h | 24
1 file changed, 24 insertions(+)
diff --git a/src/mesa/main/imports.h b/src/mesa/main/imports.h
index 29f2499..c4d917e 100644
---
Kenneth Graunke kenn...@whitecape.org writes:
ptn_move_dest and nir_fadd already take care of replicating the last
channel out, so we can just use a scalar and skip splatting it.
Signed-off-by: Kenneth Graunke kenn...@whitecape.org
Reviewed-by: Eric Anholt e...@anholt.net
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Thomas Helland thomashellan...@gmail.com writes:
This should give better cache locality, less memory consumption,
less code, and should also be faster since we avoid a modulo operation.
Also change table size to be power of two.
This gives better performance as we can do bitmasking instead of
No other path currently supports uploading data to these surfaces.
Fixes the incorrect rendering in miplevels 0 with YF/YS tiling.
Signed-off-by: Anuj Phogat anuj.pho...@gmail.com
---
src/mesa/drivers/dri/i965/intel_tex_subimage.c | 23 +--
1 file changed, 21 insertions(+),
On Wed, Feb 11, 2015 at 9:05 PM, Laura Ekstrand la...@jlekstrand.net wrote:
for (i = 0; i n; i++) {
- _mesa_HashInsert(ctx-Shared-BufferObjects, first + i,
- DummyBufferObject);
- buffer[i] = first + i;
+ buffers[i] = first + i;
+ if (dsa) {
+
From: Dave Airlie airl...@redhat.com
This code to handle absolute values on op3 srcs was a bit too simple,
it really needs a temp reg per src, not one per channel, make it
easier and let sb clean up the mess.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=89831
Signed-off-by: Dave
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