Re: [Mesa-dev] [PATCH 1/2] util: move brw_env_var_as_boolean() to util

Hi Rob, On 18.11.2015 23:20, Rob Clark wrote: From: Rob Clark Kind of a handy function. And I'll what it available outside of i965 for common nir-pass helpers. Signed-off-by: Rob Clark --- src/mesa/drivers/dri/i965/brw_context.c | 5

[Mesa-dev] [PATCH 3/3] glsl: don't eliminate unused inputs to SSO

From: Timothy Arceri We do however allow unused builtins to be removed. Cc: Ian Romanick Cc: Gregory Hainaut https://bugs.freedesktop.org/show_bug.cgi?id=79783 --- src/glsl/glsl_parser_extras.cpp|

[Mesa-dev] [PATCH 1/3] glsl: don't eliminate unused outputs in SSO

From: Timothy Arceri Cc: Ian Romanick Cc: Gregory Hainaut --- src/glsl/linker.cpp | 19 +++ 1 file changed, 11 insertions(+), 8 deletions(-) diff --git a/src/glsl/linker.cpp

[Mesa-dev] [PATCH 2/3] glsl: assign location for all outputs of SSO

From: Timothy Arceri We can have multistage separate programs so assign locations for outputs even when a consumer is available for SSO. Cc: Ian Romanick Cc: Gregory Hainaut --- src/glsl/link_varyings.cpp | 2

[Mesa-dev] [PATCH 2/2] nv50: allow using inline vertex data submit when gl_VertexID is used

The hardware can actually generates vertexid when vertices come from a client-side buffer like when glDrawElements is used. This doesn't fix (or break) any piglit tests but it improves the previous attempt of Ilia (c830d19 "nv50: avoid using inline vertex data submit when gl_VertexID is used")

[Mesa-dev] [PATCH 8/9] nir/builder: only read meaningful channels in nir_swizzle()

From: Connor Abbott This way the caller doesn't have to initialize all 4 channels when they aren't using them. v2: Fix signed/unsigned comparison warning (Iago) Reviewed-by: Iago Toral Quiroga --- src/glsl/nir/nir_builder.h | 2 +- 1 file

[Mesa-dev] [PATCH 9/9] nir: s/nir_type_unsigned/nir_type_uint

From: Jason Ekstrand v2: do the same in tgsi_to_nir (Samuel) v3: added missing cases after rebase (Iago) Reviewed-by: Iago Toral Quiroga --- src/gallium/auxiliary/nir/tgsi_to_nir.c| 2 +- src/glsl/nir/glsl_to_nir.cpp | 2 +-

[Mesa-dev] [PATCH 6/9] i965/fs: add stride restrictions for copy propagation

From: Connor Abbott There are various restrictions on what the hstride can be that depend on the Gen, and now that we're using hstride == 2 for packing/unpacking doubles, we're going to run into these restrictions a lot more often. Pull them out into a separate

[Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

From: Connor Abbott It appears that not only math instructions, but also MOV_BYTES or any instruction that uses Align1 mode cannot be in the middle of a dependency control sequence or the GPU will hang (at least on my BDW). This fixes GPU hangs in some fp64 tests.

[Mesa-dev] [PATCH 0/9] Early fp64 fixes

These patches are fixes extracted from Connor's fp64 branch that I would like to review and land ahead of the rest. They are independent of the rest of the series, some of them are even general fixes unrelated to fp64 that could fix issues in master, others are fairly trivial and we can easily

[Mesa-dev] [PATCH 1/9] i965/fs: print non-1 strides when dumping instructions

From: Connor Abbott v2: - Simplify code (Iago) Reviewed-by: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs.cpp | 12 1 file changed, 12 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp

[Mesa-dev] [PATCH 4/9] i965/fs: respect force_sechalf/force_writemask_all in CSE

From: Connor Abbott Reviewed-by: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs_cse.cpp | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs_cse.cpp b/src/mesa/drivers/dri/i965/brw_fs_cse.cpp index

[Mesa-dev] [PATCH 5/9] i965/fs: don't propagate cmod when the exec sizes differ

From: Connor Abbott This can happen when the source of the compare was split by the SIMD lowering pass. Potentially, we could allow the case where the exec size of scan_inst is larger, and scan_inst has the right quarter selected, but doing that seems a little more

[Mesa-dev] [PATCH 2/9] i965/fs: print writemask_all when it's enabled

From: Connor Abbott Reviewed-by: Iago Toral Quiroga --- src/mesa/drivers/dri/i965/brw_fs.cpp | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index 2d4ed6a..63dcba7

[Mesa-dev] [PATCH 1/2] nv50: add NV84_3D macro

Signed-off-by: Samuel Pitoiset --- src/gallium/drivers/nouveau/nv50/nv50_screen.c | 2 +- src/gallium/drivers/nouveau/nv50/nv50_vbo.c| 4 ++-- src/gallium/drivers/nouveau/nv50/nv50_winsys.h | 1 + 3 files changed, 4 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 3/4] st/va: properly set max number of reference frames

It fixes asserts like assert(templ->max_references <= 2) in nvc0_video.c::nvc0_create_decodier This patch also post-update the correct value for the number of reference frames in the h264 case, see below. In VA-API the max num ref is retrieved later in handlePictureParameterBuffer. Unfortunately

[Mesa-dev] [PATCH 0/4] st/va: fixes h264

This patches make working the pending series: "[PATCH v4 0/6] nouveau: add support for vaapi" When comparing bsp_bo nouveau_bo content between vaapi and vdpau I found that the h264 case was completely missing parsing of reference frames info in st/va. Note that for patch 3/4 I am not sure for

[Mesa-dev] [PATCH 4/4] st/va: also retrieve reference frames info for h264

st/va was completely missing parsing of: VAPictureParameterBufferH264.ReferenceFrames[16] Signed-off-by: Julien Isorce --- src/gallium/state_trackers/va/picture.c | 76 + 1 file changed, 76 insertions(+) diff --git

[Mesa-dev] [PATCH 2/4] st/va: add missing profiles in PipeToProfile's switch.

Otherwise assert is raised from vlVaQueryConfigProfiles's for loop. Signed-off-by: Julien Isorce --- src/gallium/state_trackers/va/va_private.h | 7 +++ 1 file changed, 7 insertions(+) diff --git a/src/gallium/state_trackers/va/va_private.h

[Mesa-dev] [PATCH 1/4] nouveau: move interlaced assert down in nouveau_vp3_video_buffer_create

templat->interlaced is 0 if not NV12 which is the case currently when using VPP. Signed-off-by: Julien Isorce --- src/gallium/drivers/nouveau/nouveau_vp3_video.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

Re: [Mesa-dev] [PATCH] radeon/llvm: Use llvm.AMDIL.exp intrinsic again for now

On 19.11.2015 03:55, Tom Stellard wrote: On Thu, Nov 19, 2015 at 11:31:55AM +0900, Michel Dänzer wrote: From: Michel Dänzer llvm.exp2.f32 doesn't work in some cases yet. Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=92709 Signed-off-by: Michel Dänzer

Re: [Mesa-dev] [PATCH v2 10/42] i965: Calculate appropriate L3 partition weights for the current pipeline state.

On Thu, Nov 19, 2015 at 4:24 AM, Francisco Jerez wrote: > Kristian Høgsberg writes: > >> On Tue, Nov 17, 2015 at 9:54 PM, Jordan Justen >> wrote: >>> From: Francisco Jerez >>> >>> This calculates a

Re: [Mesa-dev] [RFCv2 03/13] nir: allow pre-resolved sampler uniform locations

On Mon, Nov 9, 2015 at 4:08 PM, Timothy Arceri wrote: > On Mon, 2015-11-09 at 07:43 -0500, Rob Clark wrote: >> On Sun, Nov 8, 2015 at 7:58 PM, Timothy Arceri >> wrote: >> > On Sun, 2015-11-08 at 15:12 -0500, Rob Clark wrote: >> > > From: Rob Clark

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

On Thu, Nov 19, 2015 at 7:31 AM, Connor Abbott wrote: > On Thu, Nov 19, 2015 at 6:40 AM, Matt Turner wrote: >> On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga >> wrote: >>> From: Connor Abbott >>> >>>

Re: [Mesa-dev] [PATCH v2 19/42] glsl ubo/ssbo: Move common code into lower_buffer_access::setup_buffer_access

On 2015-11-18 00:00:08, Iago Toral wrote: > On Tue, 2015-11-17 at 21:54 -0800, Jordan Justen wrote: > > This code will also be usable by the pass to lower shared variables. > > > > Note, that *const_offset is adjusted by setup_buffer_access so it must > > be initialized before calling

Re: [Mesa-dev] [RFCv2 03/13] nir: allow pre-resolved sampler uniform locations

On Thu, Nov 19, 2015 at 2:54 PM, Rob Clark wrote: > On Mon, Nov 9, 2015 at 4:08 PM, Timothy Arceri wrote: >> On Mon, 2015-11-09 at 07:43 -0500, Rob Clark wrote: >>> On Sun, Nov 8, 2015 at 7:58 PM, Timothy Arceri >>> wrote: >>> >

Re: [Mesa-dev] [PATCH 1.9/2] i965: Add brw_imm_uv().

On Thu, Nov 19, 2015 at 9:53 AM, Matt Turner wrote: > On Thu, Nov 19, 2015 at 8:00 AM, Jason Ekstrand wrote: >> On Wed, Nov 18, 2015 at 2:25 PM, Matt Turner wrote: >>> --- >>> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +++

Re: [Mesa-dev] [PATCH 1.9/2] i965: Add brw_imm_uv().

On Thu, Nov 19, 2015 at 8:00 AM, Jason Ekstrand wrote: > On Wed, Nov 18, 2015 at 2:25 PM, Matt Turner wrote: >> --- >> src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +++ >> src/mesa/drivers/dri/i965/brw_reg.h| 9 + >> 2 files

[Mesa-dev] [PATCH] mesa: Add test for sorted extension table

From: Nanley Chery Enable developers to know if the table's alphabetical sorting is maintained or lost. v2: Move "*" next to pointer name (Matt) Include extensions_table.h instead of extensions.h (Ian) Remove extra " *" in comment (Ian) Signed-off-by: Nanley

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

On Thu, Nov 19, 2015 at 1:54 PM, Matt Turner wrote: > On Thu, Nov 19, 2015 at 7:31 AM, Connor Abbott wrote: >> On Thu, Nov 19, 2015 at 6:40 AM, Matt Turner wrote: >>> On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga

Re: [Mesa-dev] [PATCH 1.9/2] i965: Add brw_imm_uv().

On Wed, Nov 18, 2015 at 2:25 PM, Matt Turner wrote: > --- > src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 3 +++ > src/mesa/drivers/dri/i965/brw_reg.h| 9 + > 2 files changed, 12 insertions(+) > > diff --git

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

On Thu, Nov 19, 2015 at 2:07 PM, Connor Abbott wrote: > On Thu, Nov 19, 2015 at 1:54 PM, Matt Turner wrote: >> On Thu, Nov 19, 2015 at 7:31 AM, Connor Abbott wrote: >>> On Thu, Nov 19, 2015 at 6:40 AM, Matt Turner

Re: [Mesa-dev] [PATCH 3/9] i965: fix 64-bit immediates in brw_inst(_set)_bits

On Thu, Nov 19, 2015 at 11:24 AM, Matt Turner wrote: > On Thu, Nov 19, 2015 at 9:30 AM, Kristian Høgsberg wrote: >> On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga >> wrote: >>> From: Connor Abbott >>>

Re: [Mesa-dev] MESA_EXTENSION_OVERRIDE problem

On 11/19/2015 01:19 PM, Ilia Mirkin wrote: On Thu, Nov 19, 2015 at 3:13 PM, Brian Paul wrote: Hi Nanley, Maybe you can fix an issue I have with the new extension code. Previously, I could do something like export MESA_EXTENSION_OVERRIDE="-ARB_clear_buffer_object" and I

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values

On Wed, Nov 18, 2015 at 05:43:31PM +, Emil Velikov wrote: > Hi Tom, > > Please flip the order of the patches and drop the now patch 1/2 from > the stable queue. > I'm confused about why I need to flip the order of the patches. -Tom > On 16 November 2015 at 20:03, Tom Stellard

Re: [Mesa-dev] MESA_EXTENSION_OVERRIDE problem

On 11/19/2015 12:30 PM, Ilia Mirkin wrote: > On Thu, Nov 19, 2015 at 3:25 PM, Brian Paul wrote: >> On 11/19/2015 01:19 PM, Ilia Mirkin wrote: >>> On Thu, Nov 19, 2015 at 3:13 PM, Brian Paul wrote: Hi Nanley, Maybe you can fix an issue I

[Mesa-dev] [PATCH] i965: Add src/dst interference for certain instructions with hazards.

From: Kenneth Graunke When working on tessellation shaders, I created some vec4 virtual opcodes for creating message headers through a sequence like: mov(8) g7<1>UD 0xUD{ align1 WE_all 1Q compacted }; mov(1) g7.5<1>UD0x0100UD{ align1

Re: [Mesa-dev] [PATCH 2/5] i965/gen8: Allow rendering to B8G8R8X8

On Thu, Nov 19, 2015 at 04:25:18PM +0100, Neil Roberts wrote: > Since Gen8 this is allowed as a rendering target so we don't need to > override it to B8G8R8A8. This is helpful on Gen9+ where using this > override causes fast clears not to work. > --- >

Re: [Mesa-dev] [PATCH 5/5] i965/gen9: Don't allow the RGBX formats for texturing/rendering

On Thu, Nov 19, 2015 at 04:25:21PM +0100, Neil Roberts wrote: > The RGBX surface formats aren't renderable so we internally remap them > to RGBA when rendering. They are retained as RGBX when used as > textures. However since the previous patch fast clears are disabled > for surfaces that use a

Re: [Mesa-dev] [RFC 3/4] glsl: avoid linker and user varying location to overlap

On Sun, 2015-10-25 at 15:01 +0100, Gregory Hainaut wrote: > Current behavior on the interface matching: > > layout (location = 0) out0; // Assigned to VARYING_SLOT_VAR0 by user > out1; // Assigned to VARYING_SLOT_VAR0 by the linker > > New behavior on the interface matching: > > layout

Re: [Mesa-dev] MESA_EXTENSION_OVERRIDE problem

On Thu, Nov 19, 2015 at 12:13 PM, Brian Paul wrote: > Hi Nanley, > > Hi Brian, > Maybe you can fix an issue I have with the new extension code. > > Previously, I could do something like export > MESA_EXTENSION_OVERRIDE="-ARB_clear_buffer_object" and I would no longer > see

Re: [Mesa-dev] [PATCH 1/5] i965/gen9: Don't disallow fast clear for MSRT formats matching render

On Thu, Nov 19, 2015 at 04:25:17PM +0100, Neil Roberts wrote: > Previously fast clear was disallowed on Gen9 for MSRTs with the claim > that some formats don't work but we didn't understand why. On further > investigation it seems the formats that don't work are the ones where > the render surface

Re: [Mesa-dev] [PATCH 3/5] i965: Check base format to determine whether to use tiled memcpy

On Thu, Nov 19, 2015 at 04:25:19PM +0100, Neil Roberts wrote: > The tiled memcpy doesn't work for copying from RGBX to RGBA because it > doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added > a check to disable it for RGBX formats by looking at the TexFormat. > However a lot of

Re: [Mesa-dev] MESA_EXTENSION_OVERRIDE problem

On 11/19/2015 05:40 PM, Nanley Chery wrote: > > On Thu, Nov 19, 2015 at 12:13 PM, Brian Paul > wrote: > > Hi Nanley, > > > Hi Brian, > > > Maybe you can fix an issue I have with the new extension code. > > Previously, I could do

Re: [Mesa-dev] [PATCH 4/4] automake: loader: don't create an empty dri3 helper

Patches 1, 3, and 4 are Reviewed-by: Matt Turner (I gave an Ack on 2 since I didn't review the list of functions) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 2/4] automake: egl: add symbols test

Seems like a good plan. I haven't reviewed the list, so have an Acked-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] mesa: Add test for sorted extension table

On 11/19/2015 10:44 AM, Nanley Chery wrote: > From: Nanley Chery > > Enable developers to know if the table's alphabetical sorting > is maintained or lost. > > v2: Move "*" next to pointer name (Matt) > Include extensions_table.h instead of extensions.h (Ian) That

Re: [Mesa-dev] [PATCH 3/9] i965: fix 64-bit immediates in brw_inst(_set)_bits

On Thu, Nov 19, 2015 at 11:35 AM, Kristian Høgsberg wrote: > On Thu, Nov 19, 2015 at 11:24 AM, Matt Turner wrote: >> On Thu, Nov 19, 2015 at 9:30 AM, Kristian Høgsberg >> wrote: >>> On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga

[Mesa-dev] MESA_EXTENSION_OVERRIDE problem

Hi Nanley, Maybe you can fix an issue I have with the new extension code. Previously, I could do something like export MESA_EXTENSION_OVERRIDE="-ARB_clear_buffer_object" and I would no longer see it in the GL_EXTENSIONS string, even if it was an "always on" extension. Now when I try that I

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

On Thu, Nov 19, 2015 at 11:35 AM, Connor Abbott wrote: > On Thu, Nov 19, 2015 at 2:07 PM, Connor Abbott wrote: >> On Thu, Nov 19, 2015 at 1:54 PM, Matt Turner wrote: >>> On Thu, Nov 19, 2015 at 7:31 AM, Connor Abbott

Re: [Mesa-dev] MESA_EXTENSION_OVERRIDE problem

On Thu, Nov 19, 2015 at 3:25 PM, Brian Paul wrote: > On 11/19/2015 01:19 PM, Ilia Mirkin wrote: >> >> On Thu, Nov 19, 2015 at 3:13 PM, Brian Paul wrote: >>> >>> Hi Nanley, >>> >>> Maybe you can fix an issue I have with the new extension code. >>> >>>

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values

On 19 November 2015 at 20:37, Tom Stellard wrote: > On Wed, Nov 18, 2015 at 05:43:31PM +, Emil Velikov wrote: >> Hi Tom, >> >> Please flip the order of the patches and drop the now patch 1/2 from >> the stable queue. >> > > I'm confused about why I need to flip the order of

Re: [Mesa-dev] [PATCH] egl/x11/dri3: do not expose the preserved swap behavior (to be squashed)

Martin Graesslin writes: > On Thursday, November 19, 2015 1:54:22 PM CET Martin Peres wrote: >> On 11/11/15 00:44, Eric Anholt wrote: >> > Martin Peres writes: >> >> The preserved swap behavior is currently untested in piglit and not >> >>

Re: [Mesa-dev] [PATCH] mesa: Add test for sorted extension table

On Thu, Nov 19, 2015 at 10:44 AM, Nanley Chery wrote: > From: Nanley Chery > > Enable developers to know if the table's alphabetical sorting > is maintained or lost. > > v2: Move "*" next to pointer name (Matt) > Include extensions_table.h

Re: [Mesa-dev] [PATCH 3/9] i965: fix 64-bit immediates in brw_inst(_set)_bits

On Thu, Nov 19, 2015 at 9:30 AM, Kristian Høgsberg wrote: > On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga wrote: >> From: Connor Abbott >> >> If we tried to get/set something that was exactly 64 bits, we would >> try to do

Re: [Mesa-dev] [PATCH 0/9] Early fp64 fixes

For the next patches you send from Connor, please use --suppress-cc=author so that every reply doesn't generate a bounce message about his disabled @intel email. :) ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH 8/8 v2] i965: Enable EXT_shader_samples_identical

On 11/19/2015 09:34 AM, Neil Roberts wrote: > Jason Ekstrand writes: > >> On Nov 18, 2015 6:38 PM, "Ian Romanick" wrote: >>> >>> From: Ian Romanick >>> >>> v2: Handle immediate value for MCS smarter. Rebase on changes to

Re: [Mesa-dev] [PATCH 0/8] Implement EXT_shader_samples_identical

Series (with the v2 changes) is: Reviewed-by: Chris Forbes On Thu, Nov 19, 2015 at 12:46 PM, Ian Romanick wrote: > This patch series implements a new GL extension, > EXT_shader_samples_identical. This extension allows shaders to > determine when all of

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

On Thu, Nov 19, 2015 at 3:11 PM, Matt Turner wrote: > On Thu, Nov 19, 2015 at 11:35 AM, Connor Abbott wrote: >> On Thu, Nov 19, 2015 at 2:07 PM, Connor Abbott wrote: >>> On Thu, Nov 19, 2015 at 1:54 PM, Matt Turner

Re: [Mesa-dev] MESA_EXTENSION_OVERRIDE problem

On Thu, Nov 19, 2015 at 3:13 PM, Brian Paul wrote: > Hi Nanley, > > Maybe you can fix an issue I have with the new extension code. > > Previously, I could do something like export > MESA_EXTENSION_OVERRIDE="-ARB_clear_buffer_object" and I would no longer see > it in the

Re: [Mesa-dev] [PATCH 1.9/2] i965: Add brw_imm_uv().

On Thu, Nov 19, 2015 at 11:33 AM, Matt Turner wrote: > On Thu, Nov 19, 2015 at 9:53 AM, Matt Turner wrote: >> On Thu, Nov 19, 2015 at 8:00 AM, Jason Ekstrand wrote: >>> On Wed, Nov 18, 2015 at 2:25 PM, Matt Turner

Re: [Mesa-dev] [PATCH 8/8 v2] i965: Enable EXT_shader_samples_identical

Ian Romanick writes: > Am I correct that nothing special is needed in the vec4 backend? It > seems like mcs should know the register size, and the CMP with 0 > should just do the right thing. I think you probably will have to do something for the vec4 backend. Currently it

Re: [Mesa-dev] [PATCH] i965: Fix JIP to properly skip over unrelated control flow.

On Thu, Nov 19, 2015 at 2:05 PM, Kenneth Graunke wrote: > We've apparently always been botching JIP for sequences such as: Wrong since Dec 1 2015! Nice find. > >do >cmp.f0.0 ... >(+f0.0) break >... >if > ... >else >

Re: [Mesa-dev] [PATCH 8/8] i965: Enable EXT_shader_samples_identical

On Wed, Nov 18, 2015 at 9:29 PM, Jason Ekstrand wrote: > > On Nov 18, 2015 5:02 PM, "Jason Ekstrand" wrote: >> >> On Wed, Nov 18, 2015 at 4:06 PM, Kenneth Graunke >> wrote: >> > On Wednesday, November 18, 2015 03:46:54 PM Ian

[Mesa-dev] [PATCH] i965: Fix JIP to properly skip over unrelated control flow.

We've apparently always been botching JIP for sequences such as: do cmp.f0.0 ... (+f0.0) break ... if ... else ... endif ... while Normally, UIP is supposed to point to the final destination of the jump, while in nested

Re: [Mesa-dev] [PATCH 8/8] i965: Enable EXT_shader_samples_identical

Jason Ekstrand writes: > Something else that came out of that conversation is that, for 2x > MSAA, we may get bogus data in all but the bottom 4 bits. In other > words, just blindly checking for zero is probably a bad idea. It'll > work because the extension spec lets us

Re: [Mesa-dev] [PATCH 2/5] i965/gen8: Allow rendering to B8G8R8X8

On Thu, Nov 19, 2015 at 7:25 AM, Neil Roberts wrote: > Since Gen8 this is allowed as a rendering target so we don't need to > override it to B8G8R8A8. This is helpful on Gen9+ where using this > override causes fast clears not to work. > --- >

[Mesa-dev] [Bug 92706] glBlitFramebuffer refuses to blit RGBA to RGB with MSAA

https://bugs.freedesktop.org/show_bug.cgi?id=92706 --- Comment #7 from EoD --- OpenGL renderer string: Gallium 0.4 on AMD BARTS (DRM 2.43.0, LLVM 3.7.0) OpenGL core profile version string: 3.3 (Core Profile) Mesa 11.1.0-devel (git-0cfc130) After applying both patches, the patched

Re: [Mesa-dev] [RFC 0/4] V4: Improve GLSL support of GL_ARB_separate_shader_objects

Hi Gregory, My apologies I only just found this series, when you said your Mesa patchs I thought you meant the ones in the bug comments. It seems we have taken very different appoaches to the problem with inputs, I do think my change here is simpler and my series also address outputs being

Re: [Mesa-dev] [PATCH 7/9] i965/vec4: avoid dependency control around Align1 instructions

On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga wrote: > From: Connor Abbott > > It appears that not only math instructions, but also MOV_BYTES or > any instruction that uses Align1 mode cannot be in the middle > of a dependency control sequence

Re: [Mesa-dev] [PATCH 5/9] i965/fs: don't propagate cmod when the exec sizes differ

On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga wrote: > From: Connor Abbott > > This can happen when the source of the compare was split by the SIMD > lowering pass. Potentially, we could allow the case where the exec size > of scan_inst is

Re: [Mesa-dev] [PATCH 3/9] i965: fix 64-bit immediates in brw_inst(_set)_bits

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 6/9] i965/fs: add stride restrictions for copy propagation

On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga wrote: > From: Connor Abbott > > There are various restrictions on what the hstride can be that depend on > the Gen, and now that we're using hstride == 2 for packing/unpacking > doubles, we're

Re: [Mesa-dev] [PATCH] egl/x11/dri3: do not expose the preserved swap behavior (to be squashed)

On 11/11/15 00:44, Eric Anholt wrote: Martin Peres writes: The preserved swap behavior is currently untested in piglit and not supported on the GLX side. Before working on implementing it for EGL/DRI3, let's disable it until support comes. This patch is trivial

Re: [Mesa-dev] [PATCH 3/4] st/va: properly set max number of reference frames

On 19.11.2015 10:37, Julien Isorce wrote: It fixes asserts like assert(templ->max_references <= 2) in nvc0_video.c::nvc0_create_decodier This patch also post-update the correct value for the number of reference frames in the h264 case, see below. In VA-API the max num ref is retrieved later in

[Mesa-dev] [PATCH] glsl: handle case where index is array deref in optimize_split_arrays

Previously pass did not traverse to those array dereferences which were used as indices to arrays. This fixes Synmark2 Gl42CSCloth application issues. Signed-off-by: Tapani Pälli --- src/glsl/opt_array_splitting.cpp | 4 1 file changed, 4 insertions(+) diff --git

Re: [Mesa-dev] [PATCH 1/9] i965/fs: print non-1 strides when dumping instructions

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 4/9] i965/fs: respect force_sechalf/force_writemask_all in CSE

On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga wrote: > From: Connor Abbott > > Reviewed-by: Iago Toral Quiroga > --- In fact, I think Ken ran into this very bug last week. Reviewed-by: Matt Turner

Re: [Mesa-dev] [PATCH 2/9] i965/fs: print writemask_all when it's enabled

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH 9/9] nir: s/nir_type_unsigned/nir_type_uint

On Thu, Nov 19, 2015 at 2:05 AM, Iago Toral Quiroga wrote: > From: Jason Ekstrand > > v2: do the same in tgsi_to_nir (Samuel) > > v3: added missing cases after rebase (Iago) > > Reviewed-by: Iago Toral Quiroga > --- >

Re: [Mesa-dev] [PATCH 8/9] nir/builder: only read meaningful channels in nir_swizzle()

Reviewed-by: Matt Turner ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH] egl/x11/dri3: do not expose the preserved swap behavior (to be squashed)

On Thursday, November 19, 2015 1:54:22 PM CET Martin Peres wrote: > On 11/11/15 00:44, Eric Anholt wrote: > > Martin Peres writes: > >> The preserved swap behavior is currently untested in piglit and not > >> supported on the GLX side. Before working on implementing

Re: [Mesa-dev] [PATCH] egl/x11/dri3: do not expose the preserved swap behavior (to be squashed)

On 19/11/15 14:06, Martin Graesslin wrote: On Thursday, November 19, 2015 1:54:22 PM CET Martin Peres wrote: On 11/11/15 00:44, Eric Anholt wrote: Martin Peres writes: The preserved swap behavior is currently untested in piglit and not supported on the GLX side.

Re: [Mesa-dev] [PATCH v2 10/42] i965: Calculate appropriate L3 partition weights for the current pipeline state.

Kristian Høgsberg writes: > On Tue, Nov 17, 2015 at 9:54 PM, Jordan Justen > wrote: >> From: Francisco Jerez >> >> This calculates a rather conservative partitioning of the L3 cache >> based on the shaders currently bound to

Re: [Mesa-dev] [PATCH 1/8] Import current draft of EXT_shader_samples_identical spec

On 19.11.2015 00:46, Ian Romanick wrote: From: Ian Romanick Signed-off-by: Ian Romanick Cc: "Chris Forbes" --- docs/specs/EXT_shader_samples_identical.txt | 174 1 file changed, 174

[Mesa-dev] SSO fixes

Before implementing ARB_enhanced_layouts it makes sense to fix up some bugs in SSO first. This is the first of two fixes I intend to send, the other fix will be for shaders with mixed explicit and non explicit locations for inputs and outputs. This series fixes glsl bugs where inputs and

Re: [Mesa-dev] [PATCH 0/8] Implement EXT_shader_samples_identical

On 19 November 2015 at 14:53, Ilia Mirkin wrote: > On Thu, Nov 19, 2015 at 9:47 AM, Emil Velikov > wrote: >> Hi Ian, >> >> Attempting to high-jack the thread :-P >> >> On 18 November 2015 at 23:46, Ian Romanick wrote: >> >>>

Re: [Mesa-dev] [PATCH 2/9] i965/fs: print writemask_all when it's enabled

I think Ken already pushed a similar patch so we can drop this. On Thu, Nov 19, 2015 at 5:05 AM, Iago Toral Quiroga wrote: > From: Connor Abbott > > Reviewed-by: Iago Toral Quiroga > --- > src/mesa/drivers/dri/i965/brw_fs.cpp |

[Mesa-dev] [PATCH 1/5] i965/gen9: Don't disallow fast clear for MSRT formats matching render

Previously fast clear was disallowed on Gen9 for MSRTs with the claim that some formats don't work but we didn't understand why. On further investigation it seems the formats that don't work are the ones where the render surface format is being overriden to a different format than the one used for

[Mesa-dev] [PATCH 2/5] i965/gen8: Allow rendering to B8G8R8X8

Since Gen8 this is allowed as a rendering target so we don't need to override it to B8G8R8A8. This is helpful on Gen9+ where using this override causes fast clears not to work. --- src/mesa/drivers/dri/i965/brw_surface_formats.c | 9 + 1 file changed, 5 insertions(+), 4 deletions(-) diff

[Mesa-dev] [PATCH 3/5] i965: Check base format to determine whether to use tiled memcpy

The tiled memcpy doesn't work for copying from RGBX to RGBA because it doesn't override the alpha component to 1.0. Commit 2cebaac479d4 added a check to disable it for RGBX formats by looking at the TexFormat. However a lot of the rest of the code base is written with the assumption that an RGBA

[Mesa-dev] [PATCH 5/5] i965/gen9: Don't allow the RGBX formats for texturing/rendering

The RGBX surface formats aren't renderable so we internally remap them to RGBA when rendering. They are retained as RGBX when used as textures. However since the previous patch fast clears are disabled for surfaces that use a different format for rendering than for texturing. To avoid this

[Mesa-dev] [PATCH 4/5] blit: Don't take into account the Mesa format when checking MSRT blit

According to the GLES3 spec, blitting between multisample FBOs with different internal formats should not be allowed. The compatible_resolve_formats function implements this check. Previously it had a shortcut where if the Mesa formats of the two renderbuffers were the same then it would assume

Re: [Mesa-dev] [PATCH] radeon/llvm: Use llvm.AMDIL.exp intrinsic again for now

On 20.11.2015 02:11, Nicolai Hähnle wrote: > On 19.11.2015 17:37, Tom Stellard wrote: >> On Thu, Nov 19, 2015 at 11:17:12AM +0100, Nicolai Hähnle wrote: >>> On 19.11.2015 03:55, Tom Stellard wrote: On Thu, Nov 19, 2015 at 11:31:55AM +0900, Michel Dänzer wrote: > From: Michel Dänzer

Re: [Mesa-dev] [PATCH 0/8] Implement EXT_shader_samples_identical

On 11/19/2015 06:47 AM, Emil Velikov wrote: > Hi Ian, > > Attempting to high-jack the thread :-P > > On 18 November 2015 at 23:46, Ian Romanick wrote: > >> I really wanted to get this in the next Mesa release. For some reason, >> I thought the branch point was after

Re: [Mesa-dev] [PATCH v3 13/14] glsl: add subroutine index qualifier support

Hi Dave/Tapani, This is the last patch in this series unreviewed is either of you able to review is as you guys implemented the respective extensions. Thanks, Tim ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH v3 13/14] glsl: add subroutine index qualifier support

On Fri, 2015-11-20 at 14:25 +1100, Timothy Arceri wrote: > Hi Dave/Tapani, > > This is the last patch in this series unreviewed is either of you able to > review is as you guys implemented the respective extensions. Forgot to say that there are piglit compile tests in master under

Re: [Mesa-dev] [PATCH 8/8 v2] i965: Enable EXT_shader_samples_identical

On 11/19/2015 02:13 PM, Neil Roberts wrote: > Ian Romanick writes: > >> Am I correct that nothing special is needed in the vec4 backend? It >> seems like mcs should know the register size, and the CMP with 0 >> should just do the right thing. > > I think you probably will

Re: [Mesa-dev] [Mesa-stable] [PATCH 2/2] radeonsi/compute: Use the compiler's COMPUTE_PGM_RSRC* register values

On 20.11.2015 05:53, Emil Velikov wrote: > On 19 November 2015 at 20:37, Tom Stellard wrote: >> On Wed, Nov 18, 2015 at 05:43:31PM +, Emil Velikov wrote: >>> Hi Tom, >>> >>> Please flip the order of the patches and drop the now patch 1/2 from >>> the stable queue. >>> >> >>

Re: [Mesa-dev] [PATCH 4/4] automake: loader: don't create an empty dri3 helper

On Thu, Nov 19, 2015 at 9:36 PM, Vinson Lee wrote: > On Thu, Nov 19, 2015 at 8:32 AM, Emil Velikov > wrote: >> On 19 November 2015 at 16:33, Emil Velikov wrote: >>> From: Emil Velikov >>> >>>

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