[Mesa-dev] [PATCH] mesa: stop assigning unused storage for opaque types

The storage was once used by get_sampler_uniform_value() but that was fixed long ago to use the uniform storage assigned by the linker. By not assigning storage for images/samplers the constant buffer for gallium drivers will be reduced which could result in small perf improvements. --- This

Re: [Mesa-dev] [PATCH] gallium/u_threaded: replace pipe_resource_reference with atomic_inc

On 14/06/17 07:36 AM, Marek Olšák wrote: > On Tue, Jun 13, 2017 at 5:18 AM, Michel Dänzer wrote: >> On 13/06/17 01:31 AM, Marek Olšák wrote: >>> From: Marek Olšák >>> >>> --- >>> src/gallium/auxiliary/util/u_threaded_context.c | 9 +++-- >>> 1 file

Re: [Mesa-dev] [PATCH] gallium/util: Allow pipe_resource_reference to be inlined again

On 13/06/17 08:08 PM, Gustaw Smolarczyk wrote: > 2017-06-13 12:07 GMT+02:00 Michel Dänzer : >> On 13/06/17 06:51 PM, Timothy Arceri wrote: >>> On 13/06/17 19:22, Michel Dänzer wrote: From: Michel Dänzer It calling itself recursively

[Mesa-dev] [PATCH v3] gallium/util: Break recursion in pipe_resource_reference

From: Michel Dänzer It calling itself recursively prevented it from being inlined, resulting in a copy being generated in every compilation unit referencing it. This bloated the text segment of the Gallium mega-driver *_dri.so by ~4%, and might also have impacted

Re: [Mesa-dev] [PATCH 3/3] i965/gen4: Add support for single layer in alignment workaround

On Fri, Jun 9, 2017 at 7:04 AM, Topi Pohjolainen wrote: > On gen < 6 one doesn't have level or layer specifiers available > for render and depth targets. In order to support rendering to > specific level/layer, driver needs to manually offset the surface > to the

[Mesa-dev] [PATCH] st/mesa: don't update MSAA states for GL_FRAMEBUFFER_SRGB

From: Marek Olšák --- src/mesa/state_tracker/st_context.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mesa/state_tracker/st_context.c b/src/mesa/state_tracker/st_context.c index b99a53b..0d376e4 100644 --- a/src/mesa/state_tracker/st_context.c

Re: [Mesa-dev] [PATCH 06/15] i965: Prepare slice validator for isl based miptrees

On Tue, Jun 13, 2017 at 05:50:04PM +0300, Topi Pohjolainen wrote: > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 8 +++- > 1 file changed, 7 insertions(+), 1 deletion(-) > > diff --git

Re: [Mesa-dev] [PATCH 3/3] i965/gen4: Add support for single layer in alignment workaround

On Tue, Jun 13, 2017 at 4:54 PM, Jason Ekstrand wrote: > Looking through your code, I believe it is correct. I'm a bit concerned, > however, because we're now copying back to the main surface on every draw > call. If an app ever happens to hit this path, it will be

Re: [Mesa-dev] [PATCH 3/3] i965/gen4: Add support for single layer in alignment workaround

Looking through your code, I believe it is correct. I'm a bit concerned, however, because we're now copying back to the main surface on every draw call. If an app ever happens to hit this path, it will be correct, but it's performance will tank. Unfortunately, a better implementation would be a

Re: [Mesa-dev] i965: Represent aux surfaces (hiz, ccs, mcs) using isl

That was fun to read through... So much code just goes away. :-) I made a couple of fairly minor suggestions. The one semi-major concern I have is that I don't see where you convert CCS over. Am I just missing it or is it in another patch series? --Jason On Tue, Jun 13, 2017 at 7:53 AM, Topi

Re: [Mesa-dev] [PATCH 01/15] i965/miptree: Refactor mapping table alloc

On Tue, Jun 13, 2017 at 05:49:59PM +0300, Topi Pohjolainen wrote: > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 > +-- > 1 file changed, 27 insertions(+), 2 deletions(-) > > diff --git

Re: [Mesa-dev] [PATCH 16/17] ac: enable the AMDGPU asm parser

For patches 10-16: Reviewed-by: Marek Olšák Marek On Sat, Jun 10, 2017 at 1:50 AM, Connor Abbott wrote: > From: Connor Abbott > > Ported from radeonsi. Needed for emitting optimization barriers, which > contain inline asm.

Re: [Mesa-dev] [PATCH 5/8] i965/miptree: Drop MIPTREE_LAYOUT_ACCELERATED_UPLOAD in mcs init

I think I agree with the content of this patch but it needs a new commit message. :-) On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > because buffers get unconditionally initialised by cpu writing. > > Reviewed-by: Jason Ekstrand >

Re: [Mesa-dev] [PATCH 4/8] i965/miptree: Use isl for mcs layouts

On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > Reviewed-by: Jason Ekstrand > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/brw_blorp.c| 2 + >

Re: [Mesa-dev] [PATCH 3/8] i965/miptree: Refactor aux surface allocation

On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > Reviewed-by: Jason Ekstrand (v1) > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 64 > +--

Re: [Mesa-dev] [PATCH 2/8] i965/gen6: Use isl for hiz

On Tue, Jun 13, 2017 at 4:14 PM, Jason Ekstrand wrote: > On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen < > topi.pohjolai...@gmail.com> wrote: > >> Signed-off-by: Topi Pohjolainen >> --- >> src/mesa/drivers/dri/i965/brw_blorp.c | 9

[Mesa-dev] [PATCH 3/3] i965/miptree: Use the new simple alloc_tiled for CCS buffers

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 ++--- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index f24b0b5..7991f81 100644 ---

[Mesa-dev] [PATCH 1/3] i965/bufmgr: Rename bo_alloc_tiled to bo_alloc_tiled_2d

--- src/mesa/drivers/dri/i965/brw_bufmgr.c| 6 ++-- src/mesa/drivers/dri/i965/brw_bufmgr.h| 12 +++ src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 46 +-- src/mesa/drivers/dri/i965/intel_screen.c | 24 +++--- 4 files changed, 44

[Mesa-dev] [PATCH 2/3] i965/bufmgr: Add a new, simpler, bo_alloc_tiled

ISL already has all of the complexity required to figure out the correct surface pitch and size taking tile alignment into account. When we get a surface out of ISL, the pitch and size are already correct and using brw_bo_alloc_tiled_2d doesn't actually gain us anything other than extra asserts

Re: [Mesa-dev] [PATCH 2/8] i965/gen6: Use isl for hiz

On Tue, Jun 13, 2017 at 7:53 AM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/brw_blorp.c | 9 +++-- > src/mesa/drivers/dri/i965/gen6_depth_state.c | 12 +++ >

Re: [Mesa-dev] [PATCH] radeonsi: use the correct LLVMTargetMachineRef in si_build_shader_variant

On Mon, Jun 12, 2017 at 11:26 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > si_build_shader_variant can actually be called directly from one of > normal-priority compiler threads. In that case, the thread_index is > only valid for the normal tm

Re: [Mesa-dev] [PATCH 01/15] i965: Prepare blit engine for isl based miptrees

On Tue, Jun 13, 2017 at 12:10 PM, Topi Pohjolainen < topi.pohjolai...@gmail.com> wrote: > Signed-off-by: Topi Pohjolainen > --- > src/mesa/drivers/dri/i965/intel_blit.c | 62 > ++ > 1 file changed, 48 insertions(+), 14 deletions(-) > >

Re: [Mesa-dev] [Mesa-stable] [PATCH] st/glsl_to_tgsi: use correct writemask when converting generic intrinsics

Reviewed-by: Marek Olšák Marek On Mon, Jun 12, 2017 at 9:45 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > This fixes a bug when lowering ballotARB: previously, using writemask 0xf, > emit_asm would create

Re: [Mesa-dev] glmark2 segfault on imx6

Hi Lucas, On Tue, Jun 13, 2017 at 7:20 PM, Fabio Estevam wrote: > Excellent! This fixes the segfault. Thanks a lot! Got a different segfault now. Please see below. Thanks [ideas] speed=duration:[ 218.073898] etnaviv-gpu 13.gpu: hangcheck detected gpu lockup! [

Re: [Mesa-dev] [Mesa-stable] [PATCH 3/3] gallium/radeon/gfx9: fix PBO texture uploads to compressed textures

For the series: Reviewed-by: Marek Olšák Thanks for fixing this VM fault / hang! Marek On Mon, Jun 12, 2017 at 9:33 PM, Nicolai Hähnle wrote: > From: Nicolai Hähnle > > st/mesa creates a surface that reinterprets the

Re: [Mesa-dev] [PATCH 2/8] radeonsi: do EarlyCSEMemSSA LLVM pass

On Wed, Jun 14, 2017 at 12:12 AM, Miklós Máté wrote: > On 05/06/17 18:50, Marek Olšák wrote: >> >> From: Marek Olšák >> >> so that LLVM IR looks like CSE has been run on it. It's also recommended >> by the instruction combining pass. >> >> This also fixes:

Re: [Mesa-dev] [PATCH] gallium/util: Allow pipe_resource_reference to be inlined again

On Tue, Jun 13, 2017 at 1:08 PM, Gustaw Smolarczyk wrote: > 2017-06-13 12:07 GMT+02:00 Michel Dänzer : >> On 13/06/17 06:51 PM, Timothy Arceri wrote: >>> On 13/06/17 19:22, Michel Dänzer wrote: From: Michel Dänzer

Re: [Mesa-dev] [PATCH] gallium/u_threaded: replace pipe_resource_reference with atomic_inc

On Tue, Jun 13, 2017 at 5:18 AM, Michel Dänzer wrote: > On 13/06/17 01:31 AM, Marek Olšák wrote: >> From: Marek Olšák >> >> --- >> src/gallium/auxiliary/util/u_threaded_context.c | 9 +++-- >> 1 file changed, 7 insertions(+), 2 deletions(-) >> >>

[Mesa-dev] [PATCH] swr: Don't crash when encountering a VBO with stride = 0.

The swr driver uses vertex_buffer->stride to determinine the number of elements in a VBO. A recent change to the state-tracker made it possible for VBO's with stride=0. This resulted in a divide by zero crash in the driver. The solution is to use the pre-calculated vertex element stream_pitch in

Re: [Mesa-dev] glmark2 segfault on imx6

Hi Lucas, On Tue, Jun 13, 2017 at 7:10 PM, Lucas Stach wrote: > Hi Fabio, > > the attached patch should fix the issue. I should really try to get > this upstream, as some people complained about this already... Excellent! This fixes the segfault. Thanks a lot!

Re: [Mesa-dev] [PATCH 2/8] radeonsi: do EarlyCSEMemSSA LLVM pass

On 05/06/17 18:50, Marek Olšák wrote: From: Marek Olšák so that LLVM IR looks like CSE has been run on it. It's also recommended by the instruction combining pass. This also fixes: - GL45-CTS.arrays_of_arrays_gl.InteractionFunctionCalls2 (crash) -

Re: [Mesa-dev] [PATCH 0/5] GL_OES_required_internalformat

Tapani Pälli writes: > On 06/12/2017 09:52 AM, Tapani Pälli wrote: >> >> >> On 05/18/2017 09:39 PM, Eric Anholt wrote: >>> Eric Anholt writes: >>> This series came out of fixing dEQP failures on vc4's GLES2 context. Mesa was allowing RGB565

Re: [Mesa-dev] glmark2 segfault on imx6

Hi Fabio, the attached patch should fix the issue. I should really try to get this upstream, as some people complained about this already... Regards, Lucas Am Dienstag, den 13.06.2017, 16:20 -0300 schrieb Fabio Estevam: > Hi, > > I am running kernel 4.11.4 with Etnaviv 17.1.2 on a imx6qsabresd

Re: [Mesa-dev] [PATCH v5 58/63] radeonsi: only decompress resident textures/images when used

Reviewed-by: Marek Olšák Marek On Tue, Jun 13, 2017 at 11:26 PM, Samuel Pitoiset wrote: > When the current bound shaders don't use any bindless textures > or images, it's useless to decompress the resident resources. > > v5: - fix conditionals >

Re: [Mesa-dev] [PATCH 05/31] mesa: remove update_framebuffer_size

On Tue, Jun 13, 2017 at 3:46 AM, Timothy Arceri wrote: > On 13/06/17 02:55, Marek Olšák wrote: >> >> From: Marek Olšák >> >> For the default framebuffer, _mesa_resize_framebuffer updates it. >> For FBOs, _mesa_test_framebuffer_completeness updates it.

[Mesa-dev] [PATCH 7/7] i965: Do an end-of-pipe sync after flushes

According to the docs, a simple CS stall is insufficient to ensure that the memory from the flush is visible and an end-of-pipe sync is needed. --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[Mesa-dev] [PATCH 4/7] i965: Add an end-of-pipe sync helper

From: Topi Pohjolainen v2 (Jason Ekstrand): - Take a flags parameter to control the flushes - Refactoring Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_context.h | 1 +

[Mesa-dev] [PATCH 1/7] i965: Flush around state base address

--- src/mesa/drivers/dri/i965/brw_misc_state.c | 32 + src/mesa/drivers/dri/i965/genX_blorp_exec.c | 2 +- 2 files changed, 33 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index

[Mesa-dev] [PATCH 3/7] i965: Unify the two emit_pipe_control functions

These two functions contain almost identical logic except for one SNB workaround required for render target cache flushes. They may as well call into the same code so we only have to handle the work-arounds in one place. --- src/mesa/drivers/dri/i965/brw_pipe_control.c | 137

[Mesa-dev] [PATCH 0/7] i965: Stop hanging on Haswell

As I've been working on converting more things in the GL driver over to blorp, I've been highly annoyed by all of the hangs on Haswell. About one in 3-5 Jenkins runs would hang somewhere. After looking at about a half-dozen error states, I noticed that all of the hangs seemed to be on fast-clear

[Mesa-dev] [PATCH 5/7] i965: Do an end-of-pipe sync prior to STATE_BASE_ADDRESS

--- src/mesa/drivers/dri/i965/brw_misc_state.c | 18 -- 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_misc_state.c b/src/mesa/drivers/dri/i965/brw_misc_state.c index 97b6bbf..df52165 100644 ---

[Mesa-dev] [PATCH 6/7] i965/blorp: Do an end-of-pipe sync around CCS ops

--- src/mesa/drivers/dri/i965/brw_blorp.c | 16 1 file changed, 4 insertions(+), 12 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index e9745ef..f47e837 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++

[Mesa-dev] [PATCH 2/7] i965: Take a uint64_t immediate in emit_pipe_control_write

It's a 64-bit value. Splitting it up just makes the function arguments awkward. --- src/mesa/drivers/dri/i965/brw_context.h | 2 +- src/mesa/drivers/dri/i965/brw_pipe_control.c | 22 ++ src/mesa/drivers/dri/i965/brw_queryobj.c | 5 ++---

[Mesa-dev] [PATCH v5 58/63] radeonsi: only decompress resident textures/images when used

When the current bound shaders don't use any bindless textures or images, it's useless to decompress the resident resources. v5: - fix conditionals v4: - inline si_*_uses_bindless_*() v3: - rebased and updated check for compute Signed-off-by: Samuel Pitoiset

Re: [Mesa-dev] [PATCH v4 58/63] radeonsi: only decompress resident textures/images when used

On 06/13/2017 11:13 PM, Marek Olšák wrote: On Mon, Jun 12, 2017 at 2:36 PM, Samuel Pitoiset wrote: When the current bound shaders don't use any bindless textures or images, it's useless to decompress the resident resources. v4: - inline si_*_uses_bindless_*() v3:

Re: [Mesa-dev] [PATCH v4 58/63] radeonsi: only decompress resident textures/images when used

On Mon, Jun 12, 2017 at 2:36 PM, Samuel Pitoiset wrote: > When the current bound shaders don't use any bindless textures > or images, it's useless to decompress the resident resources. > > v4: - inline si_*_uses_bindless_*() > v3: - rebased and updated check for compute

Re: [Mesa-dev] [PATCH v4 57/63] radeonsi: track use of bindless samplers/images from tgsi_shader_info

Ignore my previous question. Reviewed-by: Marek Olšák Marek On Mon, Jun 12, 2017 at 2:35 PM, Samuel Pitoiset wrote: > This adds some new helper functions to know if the current draw > call (or dispatch compute) is using bindless samplers/images,

Re: [Mesa-dev] [PATCH v4 57/63] radeonsi: track use of bindless samplers/images from tgsi_shader_info

On Mon, Jun 12, 2017 at 2:37 PM, Samuel Pitoiset wrote: > Please ignore this one. So which one can I review? Marek ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org

Re: [Mesa-dev] [PATCH v3 56/63] radeonsi: decompress resident textures/images before graphics/compute

On Fri, Jun 9, 2017 at 3:35 PM, Samuel Pitoiset wrote: > Similar to the existing decompression code path except that it > loops over the list of resident textures/images. > > v3: - move the blitter check back to si_decompress_textures() > - decompress resident

Re: [Mesa-dev] [RFC 0/2] nvc0: Fix non-integer counters in AMD_performance_monitor

Looks good to me. For the series: Reviewed-by: Samuel Pitoiset On 06/11/2017 03:52 PM, Boyan Ding wrote: Some performance counters in nouveau uses non-integer type in AMD_perfmon, but they are currently returning int values. One reason behind this is that gallium

Re: [Mesa-dev] [PATCH 2/2] st/mesa: simplify returning GL_VENDOR

Rb, anyone? Thanks, Marek On Wed, Jun 7, 2017 at 10:09 PM, Marek Olšák wrote: > From: Marek Olšák > > --- > src/mesa/state_tracker/st_cb_strings.c | 4 +--- > src/mesa/state_tracker/st_context.h| 2 -- > 2 files changed, 1 insertion(+), 5

Re: [Mesa-dev] [PATCH 00/31] Mesa: Moving from _NEW flags to NewDriverState

On 14/06/17 02:15, Eero Tamminen wrote: Hi, On 13.06.2017 18:35, Ernst Sjöstrand wrote: does GfxBench v4 work on RadeonSI at all? GfxBench Manhattan, CarChase and tessellation tests require GL 4.x, its other tests (like Driver2) work with GL 3.x. Public GUI version is build with Qt. Why

Re: [Mesa-dev] glmark2 segfault on imx6

Hello Fabio, Can you get a traceback using gdb? That'd be very useful to find out where in the driver this crash happens. Regards, Wladimir On Tue, Jun 13, 2017 at 04:20:23PM -0300, Fabio Estevam wrote: > Hi, > > I am running kernel 4.11.4 with Etnaviv 17.1.2 on a imx6qsabresd board > and

[Mesa-dev] glmark2 segfault on imx6

Hi, I am running kernel 4.11.4 with Etnaviv 17.1.2 on a imx6qsabresd board and when I try to run glmark I am getting a segmentation fault: # glmark2-es2-drm ** Failed to set swap interval. Results may be bounded above by refresh rate. ===

Re: [Mesa-dev] [PATCH 1/2] clover/device: Get device/host unified memory from pipe driver

Aaron Watry writes: > Humble ping for this one. > Thanks for CC'ing me on this -- Patch is: Reviewed-by: Francisco Jerez > --Aaron > > On Sun, Jun 4, 2017 at 7:32 PM, Aaron Watry wrote: >> clinfo no longer reports my discrete GCN

[Mesa-dev] [PATCH 14/15] i965: Drop redundant check for non-tiled depth buffer

Depth buffers are always Y-tiled. In brw_miptree_choose_tiling() driver opts to use linear buffers for small and 1D but this does not apply for depth - GL_DEPTH_COMPONENT and GL_DEPTH_STENCIL_EXT are considered first. Signed-off-by: Topi Pohjolainen ---

[Mesa-dev] [PATCH 13/15] i965/gen4: Set tile offsets to zero after depth rebase

Current logic calls intel_renderbuffer_set_draw_offset() which in turn tries to calculate x and y offset against layer/level settings that are against the original miptree actually having sufficient levels/layers. This returns correctly x=0 y=0 regardless of the given layer/level only because one

[Mesa-dev] [PATCH 15/15] i965: Represent depth surfaces with isl

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_misc_state.c| 9 +- src/mesa/drivers/dri/i965/gen6_depth_state.c | 2 +- src/mesa/drivers/dri/i965/gen7_misc_state.c | 2 +- src/mesa/drivers/dri/i965/gen8_depth_state.c | 5 +-

[Mesa-dev] [PATCH 04/15] i965/miptree: Represent w-tiled stencil surfaces with isl

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/gen7_misc_state.c | 20 ++- src/mesa/drivers/dri/i965/gen8_depth_state.c | 26 ++- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 36 --- 3 files

[Mesa-dev] [PATCH 12/15] i965: Refactor check for separate stencil

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 29 --- src/mesa/drivers/dri/i965/intel_mipmap_tree.h | 4 ++-- 2 files changed, 24 insertions(+), 9 deletions(-) diff --git

[Mesa-dev] [PATCH 10/15] i965/miptree: Add support for isl based offsets

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 27 +++ 1 file changed, 23 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 07/15] i965/miptree: Prepare aux state map for isl based

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 21 ++--- 1 file changed, 18 insertions(+), 3 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 09/15] i965/fbo: Add support for isl-based miptrees in rb wrapper

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_fbo.c | 7 ++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c index e49f6df408..04ca480dfa 100644 ---

[Mesa-dev] [PATCH 01/15] i965: Prepare blit engine for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_blit.c | 62 ++ 1 file changed, 48 insertions(+), 14 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index

[Mesa-dev] [PATCH 11/15] i965/miptree: Add support for isl in readpixels_tiled_memcpy()

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_pixel_read.c | 27 ++- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_pixel_read.c

[Mesa-dev] [PATCH 05/15] i965/miptree: Represent y-tiled stencil copies with isl

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 9 - 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index

[Mesa-dev] [PATCH 02/15] i965: Refactor miptree to isl converter and adjustment

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 103 +-- 1 file changed, 57 insertions(+), 46 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c

[Mesa-dev] [PATCH 08/15] i965/miptree: Add support isl based miptrees in map_movntdqa()

--- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 17 + 1 file changed, 13 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 9fdd56eaf2..a2d4fa9d92 100644 ---

[Mesa-dev] [PATCH 06/15] i965/miptree: Prepare mapping for isl based

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 35 ++- 1 file changed, 24 insertions(+), 11 deletions(-) diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c

[Mesa-dev] [PATCH 03/15] i965: Prepare tex, img and rt state emission for isl based miptrees

Signed-off-by: Topi Pohjolainen --- src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 18 ++ 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c

[Mesa-dev] i965: Represent depth surfaces using isl

Building on top of hiz and stencil isl, this series first moves gen7+ stencil and then all depth surfaces on top of isl. Topi Pohjolainen (15): i965: Prepare blit engine for isl based miptrees i965: Refactor miptree to isl converter and adjustment i965: Prepare tex, img and rt state

Re: [Mesa-dev] [PATCH 0/6] i965: Add RGBX, RGBA configs, even on gen9

On Fri 09 Jun 2017, Tapani Pälli wrote: > > > On 06/08/2017 09:27 PM, Chad Versace wrote: > > On Thu 08 Jun 2017, Tomasz Figa wrote: > > > On Thu, Jun 8, 2017 at 4:08 PM, Tapani Pälli > > > wrote: > > > > > > > > On 06/08/2017 09:36 AM, Tapani Pälli wrote: > > > > > >

Re: [Mesa-dev] [PATCH 1/2] st/mesa: remove the "Gallium 0.4 on" prefix from GL_RENDERER

Marek Olšák writes: > From: Marek Olšák > > If you want to keep it for your driver, please raise your hand. > The prefix will probably have to be added into the driver instead of here. > > I cringe when I look at my long renderer string: > Gallium 0.4 on

[Mesa-dev] [PATCH 02/13] intel/blorp: Assert on gen7 fast-cleared subresource

Signed-off-by: Nanley Chery --- src/intel/blorp/blorp_clear.c | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/blorp/blorp_clear.c b/src/intel/blorp/blorp_clear.c index 3d5c41cc71..f43d05ad19 100644 --- a/src/intel/blorp/blorp_clear.c +++

[Mesa-dev] [PATCH 12/13] anv/blorp: Provide surface states for CCS resolves

In the future, we plan on using this method to resolve images whose surface state fast-clear value is dynamically updated during command buffer execution. Start using it now for testing and to reduce churn later on. Signed-off-by: Nanley Chery ---

[Mesa-dev] [PATCH 13/13] anv/gpu_memcpy: Rename the gpu_memcpy function

A GPU memcpy function could alternatively be implemented using MI_* commands. Provide more detail into how this one operates in case another memcpy function is created. v2: Update the commit message. Suggested-by: Jason Ekstrand Signed-off-by: Nanley Chery

[Mesa-dev] [PATCH 06/13] anv/cmd_buffer: Adjust layout transition aspect checking

Reflect the fact that an image view or subresource range with the color aspect cannot have any other aspect. Signed-off-by: Nanley Chery --- src/intel/vulkan/genX_cmd_buffer.c | 8 +++- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git

[Mesa-dev] [PATCH 11/13] anv/blorp: Add a surface-state-based CCS resolve function

This will be used in the next patch. v2: - Omit BLORP_BATCH_NO_EMIT_DEPTH_STENCIL (Jason Ekstrand) - Update commit message. Signed-off-by: Nanley Chery --- src/intel/vulkan/anv_blorp.c | 41 + src/intel/vulkan/anv_private.h |

[Mesa-dev] [PATCH 08/13] anv: Adjust params of color buffer transitioning functions

Splitting out these fields will make the color buffer transitioning function simpler when it gains more features. Signed-off-by: Nanley Chery --- src/intel/vulkan/anv_blorp.c | 33 src/intel/vulkan/anv_private.h | 4 ++--

[Mesa-dev] [PATCH 07/13] anv/blorp: Remove 3D subresource transition workaround

For 3D image subresources undergoing a layout transition via PipelineBarrier, we increase the number of fast-cleared layers to match the intended behaviour of KHR_maintenance1. When such subresources undergo layout transitions between subpasses, we don't do this to avoid failing incorrect CTS

[Mesa-dev] [PATCH 00/13] anv: Prep-work for layout-based CCS resolves

This series implements refactors and behavioral changes to make the follow-on series which implements layout-based CCS resolves a lot clearer. Cc: Jason Ekstrand Nanley Chery (13): intel/blorp: Assert on subresource in surface_info_init intel/blorp: Assert on gen7

[Mesa-dev] [PATCH 01/13] intel/blorp: Assert on subresource in surface_info_init

Signed-off-by: Nanley Chery --- src/intel/blorp/blorp.c | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/blorp/blorp.c b/src/intel/blorp/blorp.c index 9c88658e8a..993b42fa85 100644 --- a/src/intel/blorp/blorp.c +++ b/src/intel/blorp/blorp.c @@ -66,6

[Mesa-dev] [PATCH 10/13] blorp/clear: Add a binding-table-based CCS resolve function

v2: - Do layered resolves. (Jason Ekstrand): - Replace "bt" suffix with "attachment". - Rename helper function to prepare_ccs_resolve. - Move blorp_params_init() into helper function. Signed-off-by: Nanley Chery --- Looks like layered CCS resolves actually do work. I

[Mesa-dev] [PATCH 04/13] intel/isl: Only create a CCS buffer if the image supports rendering

v2: Omit the commit message. Reviewed-by: Jason Ekstrand (v1) Signed-off-by: Nanley Chery --- src/intel/isl/isl.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index

[Mesa-dev] [PATCH 03/13] intel/isl: Limit CCS to one subresource on gen7

Signed-off-by: Nanley Chery --- src/intel/isl/isl.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/intel/isl/isl.c b/src/intel/isl/isl.c index 860fc28b27..b593e153dc 100644 --- a/src/intel/isl/isl.c +++ b/src/intel/isl/isl.c @@ -1714,14

[Mesa-dev] [PATCH 09/13] anv/cmd_buffer: Adjust the image view reloc function

Make the function take in an image instead of an image view. This enables us to record relocations for surfaces states created outside of the anv_CreateImageView path. v2 (Jason Ekstrand): - Use image->offset instead of surf_offset in aux_offset calculation. Signed-off-by: Nanley Chery

[Mesa-dev] [PATCH 05/13] anv: Add and use color auxiliary buffer helpers

v2: - Check for aux levels in layer helper (Jason Ekstrand) - Don't assert aux is present, return 0 if it isn't. - Use the helpers. Signed-off-by: Nanley Chery --- src/intel/vulkan/anv_blorp.c | 4 src/intel/vulkan/anv_private.h | 39

[Mesa-dev] [PATCH 03/11] intel/genxml: Combine DataDWord{0, 1} fields in to ImmediateData field

Signed-off-by: Anuj Phogat --- src/intel/genxml/gen10.xml | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 04d89cb..64041c1 100644 --- a/src/intel/genxml/gen10.xml +++

[Mesa-dev] [PATCH 06/11] intel/genxml: Add Gen10 CACHE_MODE_1 definitions

Few of the fields in this register are changed as compared to gen9.xml. Signed-off-by: Anuj Phogat --- src/intel/genxml/gen10.xml | 22 ++ 1 file changed, 22 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index

[Mesa-dev] [PATCH 07/11] anv/cnl: Add #defines for MOCS and genX(x)

Signed-off-by: Anuj Phogat --- src/intel/vulkan/anv_private.h | 14 ++ 1 file changed, 14 insertions(+) diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h index fe6ac3b..e5d88f2 100644 --- a/src/intel/vulkan/anv_private.h +++

[Mesa-dev] [PATCH 11/11] intel: Enable vulkan build for gen10

This patch just enables building Vulkan libs for gen10. We still don't have gen 10 support enabled on Vulkan. Signed-off-by: Anuj Phogat --- src/intel/Makefile.sources | 4 1 file changed, 4 insertions(+) diff --git a/src/intel/Makefile.sources

[Mesa-dev] [PATCH 01/11] intel/genxml: Add better support for MI_MATH in gen10

Signed-off-by: Anuj Phogat --- src/intel/genxml/gen10.xml | 69 +++--- 1 file changed, 65 insertions(+), 4 deletions(-) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index ebeb5da8f..26dba22 100644 ---

[Mesa-dev] [PATCH 09/11] anv/cnl: Don't set FloatBlendOptimizationEnable{Mask}

This field is removed from CACHE_MODE_1 register in gen10. Signed-off-by: Anuj Phogat --- src/intel/vulkan/genX_state.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c index

[Mesa-dev] [PATCH 04/11] intel/genxml: Rename IndirectStatePointer to BorderColorPointer

Signed-off-by: Anuj Phogat --- src/intel/genxml/gen10.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 64041c1..06260cf 100644 --- a/src/intel/genxml/gen10.xml +++

[Mesa-dev] [PATCH 10/11] anv/cnl: Generate and use gen10 functions

Signed-off-by: Anuj Phogat --- src/intel/vulkan/anv_blorp.c| 3 +++ src/intel/vulkan/anv_cmd_buffer.c | 2 ++ src/intel/vulkan/anv_device.c | 2 ++ src/intel/vulkan/anv_entrypoints_gen.py | 7 ++- 4 files changed, 13 insertions(+), 1

[Mesa-dev] [PATCH 08/11] anv/cnl: Use GENX(xx) in place of GEN9_xx

Signed-off-by: Anuj Phogat --- src/intel/vulkan/gen8_cmd_buffer.c | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/src/intel/vulkan/gen8_cmd_buffer.c b/src/intel/vulkan/gen8_cmd_buffer.c index 5241206..a209d70 100644 ---

[Mesa-dev] [PATCH 02/11] intel/genxml: Add INSTDONE registers in gen10

Signed-off-by: Anuj Phogat --- src/intel/genxml/gen10.xml | 115 + 1 file changed, 115 insertions(+) diff --git a/src/intel/genxml/gen10.xml b/src/intel/genxml/gen10.xml index 26dba22..04d89cb 100644 ---

[Mesa-dev] [PATCH 05/11] intel/genxml: Rename StartInstanceLocation to StartingInstanceLocation

This is required because we already have a macro defined with the name StartInstanceLocation. Signed-off-by: Anuj Phogat --- src/intel/genxml/gen10.xml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/intel/genxml/gen10.xml

Re: [Mesa-dev] [PATCH 1/2] st/mesa: remove the "Gallium 0.4 on" prefix from GL_RENDERER

On 08/06/17 05:17, Timothy Arceri wrote: On 08/06/17 12:04, Michel Dänzer wrote: On 08/06/17 05:09 AM, Marek Olšák wrote: From: Marek Olšák If you want to keep it for your driver, please raise your hand. The prefix will probably have to be added into the driver instead

Re: [Mesa-dev] [PATCH 1/4] i965: Add a "write" parameter to intel_bufferobj_buffer.

On Tuesday, June 13, 2017 4:45:18 AM PDT Chris Wilson wrote: > Quoting Kenneth Graunke (2017-06-13 01:33:29) > > This doesn't do anything yet, but soon we'll want to know whether an > > access to a buffer section may write that data, or simply reads it. > > This series doesn't got further than

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