Re: [Mesa-dev] [PATCH 1/3] i965: Fix offset addition in get_isl_surf.

[Pohjolainen, Topi]

On Tue, Jul 25, 2017 at 11:04:12AM -0700, Kenneth Graunke wrote:
> Increase the value, not the pointer to the stack variable.
> 
> Caught by Coverity (CID 1415574).  Not shipped in a real release.
> 
> Cc: "17.2" 

I already had the same patch:

Reviewed-by: Topi Pohjolainen 

I didn't see us actually taking this fallback path these days - I wonder if we
actually do. But needs fixing anyway.

> ---
>  src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
> b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> index 250806d28e4..a0ca6ddf985 100644
> --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
> @@ -101,9 +101,9 @@ get_isl_surf(struct brw_context *brw, struct 
> intel_mipmap_tree *mt,
> assert(view->levels == 1 && view->array_len == 1);
> assert(*tile_x == 0 && *tile_y == 0);
>  
> -   offset += intel_miptree_get_tile_offsets(mt, view->base_level,
> -view->base_array_layer,
> -tile_x, tile_y);
> +   *offset += intel_miptree_get_tile_offsets(mt, view->base_level,
> + view->base_array_layer,
> + tile_x, tile_y);
>  
> /* Minify the logical dimensions of the texture. */
> const unsigned l = view->base_level - mt->first_level;
> -- 
> 2.13.3
> 
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[Mesa-dev] [PATCH] radv: force compute flush at end of command stream.

[Dave Airlie]

From: Dave Airlie 

This seems like a workaround, but we don't see the bug on CIK/VI.

On SI with the dEQP-VK.memory.pipeline_barrier.host_read_transfer_dst.*
tests, when one tests complete, the first flush at the start of the next
test causes a VM fault as we've destroyed the VM, but we end up flushing
the compute shader then, and it must still be in the process of doing
something.

Could also be a kernel difference between SI and CIK.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4415e36..d185c00 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2233,8 +2233,10 @@ VkResult radv_EndCommandBuffer(
 {
RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
 
-   if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER)
+   if (cmd_buffer->queue_family_index != RADV_QUEUE_TRANSFER) {
+   cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
si_emit_cache_flush(cmd_buffer);
+   }
 
if (!cmd_buffer->device->ws->cs_finalize(cmd_buffer->cs) ||
cmd_buffer->record_fail)
-- 
2.9.4

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Re: [Mesa-dev] [PATCH] genxml: Remove a redundant identical code for different branches

[Mun, Gwan-gyeong]

Hi Jason,
You are right, as you commented, compilers can eliminate these redundancies
easy.
However I think we don't need to generate redundant codes.

Best regards,
Gwan-gyeong

2017년 7월 26일 (수) 오전 12:34, Jason Ekstrand 님이 작성:

> Does the redundancy ends up mattering in any way?  A decent optimizing
> compiler should easily be able to get rid of that for you.
>
> --Jason
>
>
> On July 25, 2017 2:51:31 AM Gwan-gyeong Mun  wrote:
>
> > Before, it generates functions like this,
> >
> > static inline uint32_t ATTRIBUTE_PURE
> > RENDER_SURFACE_STATE_RedClearColor_start(const struct gen_device_info
> *devinfo)
> > {
> >switch (devinfo->gen) {
> >case 10: return 384;
> >case 9: return 384;
> >case 8: return 255;
> >case 7:
> >   if (devinfo->is_haswell) {
> >  return 255;
> >   } else {
> >  return 255;
> >   }
> >case 6: return 0;
> >case 5: return 0;
> >case 4:
> >   if (devinfo->is_g4x) {
> >  return 0;
> >   } else {
> >  return 0;
> >   }
> >default:
> >   unreachable("Invalid hardware generation");
> >}
> > }
> >
> > After, it generates fuctions without a redundant identical code for
> different
> > branches.
> >
> > static inline uint32_t ATTRIBUTE_PURE
> > RENDER_SURFACE_STATE_RedClearColor_start(const struct gen_device_info
> *devinfo)
> > {
> >switch (devinfo->gen) {
> >case 10: return 384;
> >case 9: return 384;
> >case 8: return 255;
> >case 7: return 255;
> >case 6: return 0;
> >case 5: return 0;
> >case 4: return 0;
> >default:
> >   unreachable("Invalid hardware generation");
> >}
> > }
> >
> > Signed-off-by: Mun Gwan-gyeong 
> > ---
> >  src/intel/genxml/gen_bits_header.py | 8 
> >  1 file changed, 8 insertions(+)
> >
> > diff --git a/src/intel/genxml/gen_bits_header.py
> > b/src/intel/genxml/gen_bits_header.py
> > index 1b3504073b..8084facdb7 100644
> > --- a/src/intel/genxml/gen_bits_header.py
> > +++ b/src/intel/genxml/gen_bits_header.py
> > @@ -83,20 +83,28 @@ ${item.token_name}_${prop}(const struct
> gen_device_info
> > *devinfo)
> > case 10: return ${item.get_prop(prop, 10)};
> > case 9: return ${item.get_prop(prop, 9)};
> > case 8: return ${item.get_prop(prop, 8)};
> > +% if item.get_prop(prop, 7) == item.get_prop(prop, 7.5):
> > +   case 7: return ${item.get_prop(prop, 7)};
> > +% else:
> > case 7:
> >if (devinfo->is_haswell) {
> >   return ${item.get_prop(prop, 7.5)};
> >} else {
> >   return ${item.get_prop(prop, 7)};
> >}
> > +% endif
> > case 6: return ${item.get_prop(prop, 6)};
> > case 5: return ${item.get_prop(prop, 5)};
> > +% if item.get_prop(prop, 4) == item.get_prop(prop, 4.5):
> > +   case 4: return ${item.get_prop(prop, 4)};
> > +% else:
> > case 4:
> >if (devinfo->is_g4x) {
> >   return ${item.get_prop(prop, 4.5)};
> >} else {
> >   return ${item.get_prop(prop, 4)};
> >}
> > +% endif
> > default:
> >unreachable("Invalid hardware generation");
> > }
> > --
> > 2.13.3
> >
>
>
> --
Gwan-gyeong Mun
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Re: [Mesa-dev] [PATCH v2] st/dri: add 32-bit RGBX/RGBA formats

[Chih-Wei Huang]

2017-07-26 1:24 GMT+08:00 Rob Herring :
> On Tue, Jul 25, 2017 at 10:15 AM, Emil Velikov  
> wrote:
>> On 25 July 2017 at 03:46, Chih-Wei Huang  wrote:
>>> On Tue 11 Jul 2017, Rob Herring wrote:
> From: Marek Olšák 
>
> Add support for 32-bit RGBX/RGBA formats which are required for Android.
>
> The original patch (commit ccdcf91104a5) was reverted (commit
> c0c6ca40a25e) in mesa as it broke GLX resulting in swapped colors. Based
> on further investigation by Chad Versace, moving the RGBX/RGBA configs
> to the end is enough to prevent breaking GLX.
>
> The handling of RGBA/RGBX in dri_fill_st_visual is a fix from Marek
> Olšák.
>
> Cc: Eric Anholt 
> Cc: Chad Versace 
> Cc: Mauro Rossi 
> Reviewed-by: Marek Olšák 
> Signed-off-by: Rob Herring 
> ---
>>>
>>> Hi Rob,
>>> I'm testing this patch with your gbm_gralloc and mesa 17.1.5.
>>> Before applying this patch, the SurfaceFlinger sees
>>> the alpha=8 in RenderEngine::chooseEglConfig()
>>>
>> May want to check for patches in the Android EGL (meta) library.
>> I think, in does/did have a handful of workarounds.
>>
>> Is the Android-x86 one in sync with the one RobH uses?
>
> I double checked and I get 8-8-8-8. I'm have HWC2 enabled and
> SurfaceFlinger is unpatched master branch.

Hmm, strange.
Which hwcomposer branch did you use and
what GPU did you test?

As I explained to you (in another private email),
I'm testing QEMU x86 virgl with your branches:

http://github.com/robherring/gbm_gralloc  (master branch)
http://github.com/robherring/drm_hwcomposer (android-m branch)

If I understand your code correctly, it supports
only HWC1, no HWC2 yet.
I accidentally set HWC2=true in the first time testing
but it didn't work. Setting HWC2=false works.
(on the other hand, the chromium upstream[1] does
switch to HWC2 now, but I can't make it work yet)

About the client (SurfaceFlinger), I believe it requests
HAL_PIXEL_FORMAT_RGBA_ but finally
HAL_PIXEL_FORMAT_RGBX_ is used.

The logic I saw is:
1. In SurfaceFlinger::init(), it calls RenderEngine::create() with
hwcFormat=HAL_PIXEL_FORMAT_RGBA_
   (if HWC2 is used or if HWC1 api ver >= 1.1)
2. RenderEngine::create() calls RenderEngine::chooseEglConfig()
   with format=HAL_PIXEL_FORMAT_RGBA_
3. chooseEglConfig() tries to find a config and prints
   the info as we see in the logcat. With this patch,
   the selected config is 8-8-8-0.
4. RenderEngine::create() saves the config to mEGLConfig
   by engine->setEGLHandles()
5. Later, new DisplayDevice::DisplayDevice() is called with
   with the selected config (mRenderEngine->getEGLConfig()).
   Then it calls eglCreateWindowSurface() with the config.
6. eglCreateWindowSurface() checks[2] the alpha attrib
   of this config to decide which format to be used.
   With this patch, alpha=0 so HAL_PIXEL_FORMAT_RGBX_
   is used. (if alpha > 0, HAL_PIXEL_FORMAT_RGBA_ is used)

The differences between you and me maybe:
* AOSP: master vs 7.1.2
* Mesa: master(?) vs 17.1.5
* GPU: ?? vs virgl

I think AOSP doesn't matter. I don't see explicit change
of the above logic in the master branch.
Does Mesa version matter? May I need more patches in 17.1.5?
About GPU, did you test virgl and still see 8-8-8-8?

About the problem of the change, it's not explicitly.
But some apps require RGBA_ still can't work.
An example is the screen capture apps like Screenshot touch[3].
It complains the producer output format is RGBX_
but RGBA_ is expected:

07-26 10:18:28.236  2602  2669 E ImageReader_JNI: Producer output
buffer format: 0x2, ImageReader configured format: 0x1

I expect the patch fix it but it's not.

[1]: https://chromium.googlesource.com/chromiumos/drm_hwcomposer
[2]: 
https://android.googlesource.com/platform/frameworks/native/+/master/opengl/libs/EGL/eglApi.cpp#484
[3]: https://play.google.com/store/apps/details?id=com.mdiwebma.screenshot


-- 
Chih-Wei
Android-x86 project
http://www.android-x86.org
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[Mesa-dev] [PATCH] radv: implement SI/CIK compute shader regalloc hang workaround.

[Dave Airlie]

From: Dave Airlie 

This ports the regalloc hang workaround from radeonsi, not 100%
sure if this is only needed on the GFX queue as the workaround
references async compute not requiring it.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_cmd_buffer.c | 10 ++
 src/amd/vulkan/radv_pipeline.c   |  8 
 src/amd/vulkan/radv_private.h|  3 +++
 3 files changed, 21 insertions(+)

diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c
index 4b08781..4415e36 100644
--- a/src/amd/vulkan/radv_cmd_buffer.c
+++ b/src/amd/vulkan/radv_cmd_buffer.c
@@ -2290,6 +2290,16 @@ radv_emit_compute_pipeline(struct radv_cmd_buffer 
*cmd_buffer)
radeon_emit(cmd_buffer->cs,

S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
 
+   /* HW bug workaround when CS threadgroups > 256 threads and async
+* compute isn't used, i.e. only one compute job can run at a time.
+* If async compute is possible, the threadgroup size must be limited
+* to 256 threads on all queues to avoid the bug.
+* Only SI and certain CIK chips are affected.
+*/
+   if (pipeline->compute.regalloc_hang) {
+   cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_PS_PARTIAL_FLUSH |
+   RADV_CMD_FLAG_CS_PARTIAL_FLUSH;
+   }
assert(cmd_buffer->cs->cdw <= cdw_max);
 }
 
diff --git a/src/amd/vulkan/radv_pipeline.c b/src/amd/vulkan/radv_pipeline.c
index 496c06a..fcfe7dc 100644
--- a/src/amd/vulkan/radv_pipeline.c
+++ b/src/amd/vulkan/radv_pipeline.c
@@ -2376,6 +2376,14 @@ static VkResult radv_compute_pipeline_create(
return result;
}
 
+   if ((device->physical_device->rad_info.chip_class == SI ||
+device->physical_device->rad_info.family == CHIP_BONAIRE ||
+device->physical_device->rad_info.family == CHIP_KABINI) &&
+   (pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
+pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
+pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2] > 
256))
+   pipeline->compute.regalloc_hang = true;
+
*pPipeline = radv_pipeline_to_handle(pipeline);
 
if (device->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) {
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 8cd5ec0..4eac84c 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1094,6 +1094,9 @@ struct radv_pipeline {
struct radv_prim_vertex_count prim_vertex_count;
bool can_use_guardband;
} graphics;
+   struct {
+   bool regalloc_hang;
+   } compute;
};
 
unsigned max_waves;
-- 
2.9.4

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[Mesa-dev] [PATCH] radv/winsys: fix padding command stream for SI

[Dave Airlie]

From: Dave Airlie 

We were adding pad to size after creating the object, so we could
submit a CS bigger than the bo created for it.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c | 10 ++
 1 file changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c 
b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
index 0d89b95..ad4b0b3 100644
--- a/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
+++ b/src/amd/vulkan/winsys/amdgpu/radv_amdgpu_cs.c
@@ -841,7 +841,7 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
uint32_t *ptr;
unsigned cnt = 0;
unsigned size = 0;
-
+   unsigned pad_words = 0;
if (preamble_cs)
size += preamble_cs->cdw;
 
@@ -850,6 +850,10 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
++cnt;
}
 
+   while(!size || (size & 7)) {
+   size++;
+   pad_words++;
+   }
assert(cnt);
 
bo = ws->buffer_create(ws, 4 * size, 4096, RADEON_DOMAIN_GTT, 
RADEON_FLAG_CPU_ACCESS);
@@ -867,10 +871,8 @@ static int radv_amdgpu_winsys_cs_submit_sysmem(struct 
radeon_winsys_ctx *_ctx,
 
}
 
-   while(!size || (size & 7)) {
+   for (unsigned j = 0; j < pad_words; ++j)
*ptr++ = pad_word;
-   ++size;
-   }
 
memset(, 0, sizeof(request));
 
-- 
2.9.4

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Re: [Mesa-dev] [PATCH 075/101] mesa: add KHR_no_error support to glVertexArrayElementBuffer()

[Timothy Arceri]

67-75:

Reviewed-by: Timothy Arceri 
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Re: [Mesa-dev] [PATCH 2/3] i965: Fix = vs == in MCS aux usage assert.

[Jason Ekstrand]

Oops... R-B


On July 25, 2017 11:04:22 AM Kenneth Graunke  wrote:


Caught by Coverity (CID 1415680).

Cc: "17.2" 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c

index 36f7ed2a39d..a0f37780ef5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1103,7 +1103,7 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw,
DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
start_layer, start_layer + num_layers - 1);

-   assert(mt->aux_usage = ISL_AUX_USAGE_MCS);
+   assert(mt->aux_usage == ISL_AUX_USAGE_MCS);

const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
enum isl_format isl_format = brw_blorp_to_isl_format(brw, format, true);
--
2.13.3

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Re: [Mesa-dev] [PATCH 3/3] i965: Shut up Coverity warning about HiZ buffers.

[Jason Ekstrand]

R-B


On July 25, 2017 11:04:25 AM Kenneth Graunke  wrote:


Here the AUX_USAGE_* mode indicates that we have HiZ, so we will have
a HiZ buffer.  But Coverity doesn't know that, so it thinks it might
be NULL because we checked hiz_buf != NULL earlier.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c

index a0f37780ef5..b2987ca4faf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -184,6 +184,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
  surf->aux_addr.buffer = mt->mcs_buf->bo;
  surf->aux_addr.offset = mt->mcs_buf->offset;
   } else {
+ assert(mt->hiz_buf);
  assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);

  surf->aux_addr.buffer = mt->hiz_buf->bo;
--
2.13.3

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Re: [Mesa-dev] [PATCH 066/101] mesa: add draw_buffers_error() helper

[Timothy Arceri]

On 22/07/17 03:40, Samuel Pitoiset wrote:

And make draw_buffers() always inline.

Signed-off-by: Samuel Pitoiset 
---
  src/mesa/main/buffers.c | 223 ++--
  1 file changed, 119 insertions(+), 104 deletions(-)

diff --git a/src/mesa/main/buffers.c b/src/mesa/main/buffers.c
index 9a049e94c7..a2a1a3a741 100644
--- a/src/mesa/main/buffers.c
+++ b/src/mesa/main/buffers.c
@@ -389,9 +389,9 @@ _mesa_NamedFramebufferDrawBuffer(GLuint framebuffer, GLenum 
buf)
   * that is considered special and allowed as far as n is one
   * since 4.5.
   */
-static void
-draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb,
- GLsizei n, const GLenum *buffers, const char *caller)
+static ALWAYS_INLINE void
+draw_buffers(struct gl_context *ctx, struct gl_framebuffer *fb, GLsizei n,
+ const GLenum *buffers, const char *caller, bool no_error)
  {
 GLuint output;
 GLbitfield usedBufferMask, supportedMask;
@@ -399,22 +399,24 @@ draw_buffers(struct gl_context *ctx, struct 
gl_framebuffer *fb,
  
 FLUSH_VERTICES(ctx, 0);
  
-   /* Turns out n==0 is a valid input that should not produce an error.

-* The remaining code below correctly handles the n==0 case.
-*
-* From the OpenGL 3.0 specification, page 258:
-* "An INVALID_VALUE error is generated if n is greater than
-*  MAX_DRAW_BUFFERS."
-*/
-   if (n < 0) {
-  _mesa_error(ctx, GL_INVALID_VALUE, "%s(n < 0)", caller);
-  return;
-   }
+   if (!no_error) {
+  /* Turns out n==0 is a valid input that should not produce an error.
+   * The remaining code below correctly handles the n==0 case.
+   *
+   * From the OpenGL 3.0 specification, page 258:
+   * "An INVALID_VALUE error is generated if n is greater than
+   *  MAX_DRAW_BUFFERS."
+   */
+  if (n < 0) {
+ _mesa_error(ctx, GL_INVALID_VALUE, "%s(n < 0)", caller);
+ return;
+  }
  
-   if (n > (GLsizei) ctx->Const.MaxDrawBuffers) {

-  _mesa_error(ctx, GL_INVALID_VALUE,
-  "%s(n > maximum number of draw buffers)", caller);
-  return;
+  if (n > (GLsizei) ctx->Const.MaxDrawBuffers) {
+ _mesa_error(ctx, GL_INVALID_VALUE,
+ "%s(n > maximum number of draw buffers)", caller);
+ return;
+  }
 }
  
 supportedMask = supported_buffer_bitmask(ctx, fb);


You seem to have missed an error check here.

   /* From the ES 3.0 specification, page 180:
* "If the GL is bound to the default framebuffer, then n must be 1
*  and the constant must be BACK or NONE."
* (same restriction applies with GL_EXT_draw_buffers specification)
*/
   if (ctx->API == API_OPENGLES2 && _mesa_is_winsys_fbo(fb) &&
   (n != 1 || (buffers[0] != GL_NONE && buffers[0] != GL_BACK))) {
  _mesa_error(ctx, GL_INVALID_OPERATION, "%s(invalid buffers)", 
caller);

  return;
   }

This should be moved into the new if block above.

With that fixed this patch is:

Reviewed-by: Timothy Arceri 


@@ -435,65 +437,67 @@ draw_buffers(struct gl_context *ctx, struct 
gl_framebuffer *fb,
 for (output = 0; output < n; output++) {
destMask[output] = draw_buffer_enum_to_bitmask(ctx, buffers[output]);
  
-  /* From the OpenGL 3.0 specification, page 258:

-   * "Each buffer listed in bufs must be one of the values from tables
-   *  4.5 or 4.6.  Otherwise, an INVALID_ENUM error is generated.
-   */
-  if (destMask[output] == BAD_MASK) {
- _mesa_error(ctx, GL_INVALID_ENUM, "%s(invalid buffer %s)",
- caller, _mesa_enum_to_string(buffers[output]));
- return;
-  }
-
-  /* From the OpenGL 4.5 specification, page 493 (page 515 of the PDF)
-   * "An INVALID_ENUM error is generated if any value in bufs is FRONT,
-   *  LEFT, RIGHT, or FRONT_AND_BACK . This restriction applies to both
-   *  the default framebuffer and framebuffer objects, and exists because
-   *  these constants may themselves refer to multiple buffers, as shown
-   *  in table 17.4."
-   *
-   * And on page 492 (page 514 of the PDF):
-   * "If the default framebuffer is affected, then each of the constants
-   *  must be one of the values listed in table 17.6 or the special value
-   *  BACK. When BACK is used, n must be 1 and color values are written
-   *  into the left buffer for single-buffered contexts, or into the back
-   *  left buffer for double-buffered contexts."
-   *
-   * Note "special value BACK". GL_BACK also refers to multiple buffers,
-   * but it is consider a special case here. This is a change on 4.5. For
-   * OpenGL 4.x we check that behaviour. For any previous version we keep
-   * considering it wrong (as INVALID_ENUM).
-   */
-  if (_mesa_bitcount(destMask[output]) > 1) {
- if (_mesa_is_winsys_fbo(fb) && 

[Mesa-dev] [PATCH] radv/ac: port SI TC L1 write corruption fix.

[Dave Airlie]

From: Dave Airlie 

This ports 72e46c988 to radv.
radeonsi: apply a TC L1 write corruption workaround for SI

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 9 ++---
 1 file changed, 6 insertions(+), 3 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index a427f48..570e375 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -3400,7 +3400,10 @@ static void visit_image_store(struct nir_to_llvm_context 
*ctx,
char intrinsic_name[64];
const nir_variable *var = instr->variables[0]->var;
const struct glsl_type *type = glsl_without_array(var->type);
-
+   LLVMValueRef glc = ctx->i1false;
+   bool force_glc = ctx->options->chip_class == SI;
+   if (force_glc)
+   glc = ctx->i1true;
if (ctx->stage == MESA_SHADER_FRAGMENT)
ctx->shader_info->fs.writes_memory = true;
 
@@ -3410,7 +3413,7 @@ static void visit_image_store(struct nir_to_llvm_context 
*ctx,
params[2] = LLVMBuildExtractElement(ctx->builder, get_src(ctx, 
instr->src[0]),
LLVMConstInt(ctx->i32, 0, 
false), ""); /* vindex */
params[3] = LLVMConstInt(ctx->i32, 0, false); /* voffset */
-   params[4] = ctx->i1false;  /* glc */
+   params[4] = glc;  /* glc */
params[5] = ctx->i1false;  /* slc */
ac_build_intrinsic(>ac, 
"llvm.amdgcn.buffer.store.format.v4f32", ctx->voidt,
   params, 6, 0);
@@ -3418,7 +3421,7 @@ static void visit_image_store(struct nir_to_llvm_context 
*ctx,
bool is_da = glsl_sampler_type_is_array(type) ||
 glsl_get_sampler_dim(type) == 
GLSL_SAMPLER_DIM_CUBE;
LLVMValueRef da = is_da ? ctx->i1true : ctx->i1false;
-   LLVMValueRef glc = ctx->i1false;
+
LLVMValueRef slc = ctx->i1false;
 
params[0] = to_float(>ac, get_src(ctx, instr->src[2]));
-- 
2.9.4

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[Mesa-dev] [PATCH] radv/ac: realign SI workaround with radeonsi.

[Dave Airlie]

From: Dave Airlie 

This ports: da7453666ae
radeonsi: don't apply the Z export bug workaround to Hainan
to radv.

Just noticed in passing.

Fixes: f4e499ec7 (radv: add initial non-conformant radv vulkan driver)
Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index 9a69066..a427f48 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -5815,10 +5815,11 @@ si_export_mrt_z(struct nir_to_llvm_context *ctx,
args.enabled_channels |= 0x4;
}
 
-   /* SI (except OLAND) has a bug that it only looks
+   /* SI (except OLAND and HAINAN) has a bug that it only looks
 * at the X writemask component. */
if (ctx->options->chip_class == SI &&
-   ctx->options->family != CHIP_OLAND)
+   ctx->options->family != CHIP_OLAND &&
+   ctx->options->family != CHIP_HAINAN)
args.enabled_channels |= 0x1;
 
ac_build_export(>ac, );
-- 
2.9.4

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[Mesa-dev] [PATCH 3/3] mesa: don't error check the default buffer object

[Timothy Arceri]

An allocation check is already done when the buffer is created at
context creation.
---
 src/mesa/main/bufferobj.c | 22 +++---
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index cb666dc..b02d011 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -4047,6 +4047,12 @@ bind_buffer_range(GLenum target, GLuint index, GLuint 
buffer, GLintptr offset,
   if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
 , "glBindBufferRange"))
  return;
+
+  if (!no_error && !bufObj) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "glBindBufferRange(invalid buffer=%u)", buffer);
+ return;
+  }
}
 
if (no_error) {
@@ -4069,12 +4075,6 @@ bind_buffer_range(GLenum target, GLuint index, GLuint 
buffer, GLintptr offset,
  unreachable("invalid BindBufferRange target with KHR_no_error");
   }
} else {
-  if (!bufObj) {
- _mesa_error(ctx, GL_INVALID_OPERATION,
- "glBindBufferRange(invalid buffer=%u)", buffer);
- return;
-  }
-
   if (buffer != 0) {
  if (size <= 0) {
 _mesa_error(ctx, GL_INVALID_VALUE, "glBindBufferRange(size=%d)",
@@ -4145,12 +4145,12 @@ _mesa_BindBufferBase(GLenum target, GLuint index, 
GLuint buffer)
   if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
 , "glBindBufferBase"))
  return;
-   }
 
-   if (!bufObj) {
-  _mesa_error(ctx, GL_INVALID_OPERATION,
-  "glBindBufferBase(invalid buffer=%u)", buffer);
-  return;
+  if (!bufObj) {
+ _mesa_error(ctx, GL_INVALID_OPERATION,
+ "glBindBufferBase(invalid buffer=%u)", buffer);
+ return;
+  }
}
 
/* Note that there's some oddness in the GL 3.1-GL 3.3 specifications with
-- 
2.9.4

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[Mesa-dev] [PATCH 2/3] mesa: check default buffer object creation was successful

[Timothy Arceri]

---
 src/mesa/main/shared.c | 9 +
 1 file changed, 9 insertions(+)

diff --git a/src/mesa/main/shared.c b/src/mesa/main/shared.c
index 4bc93a7..27e8094 100644
--- a/src/mesa/main/shared.c
+++ b/src/mesa/main/shared.c
@@ -44,6 +44,9 @@
 #include "util/hash_table.h"
 #include "util/set.h"
 
+static void
+free_shared_state(struct gl_context *ctx, struct gl_shared_state *shared);
+
 /**
  * Allocate and initialize a shared context state structure.
  * Initializes the display list, texture objects and vertex programs hash
@@ -90,6 +93,8 @@ _mesa_alloc_shared_state(struct gl_context *ctx)
 
/* Allocate the default buffer object */
shared->NullBufferObj = ctx->Driver.NewBufferObject(ctx, 0);
+   if (!shared->NullBufferObj)
+  goto no_mem;
 
/* Create default texture objects */
for (i = 0; i < NUM_TEXTURE_TARGETS; i++) {
@@ -131,6 +136,10 @@ _mesa_alloc_shared_state(struct gl_context *ctx)
   _mesa_key_pointer_equal);
 
return shared;
+
+no_mem:
+   free_shared_state(ctx, shared);
+   return NULL;
 }
 
 
-- 
2.9.4

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[Mesa-dev] [PATCH 1/3] mesa: add NULL checking to free_shared_state()

[Timothy Arceri]

This will allow us to call this function from
_mesa_alloc_shared_state() in the case that we run out of memory
part way through allocating the state.
---
 src/mesa/main/shared.c  | 88 +++--
 src/mesa/main/texturebindless.c |  8 +++-
 2 files changed, 65 insertions(+), 31 deletions(-)

diff --git a/src/mesa/main/shared.c b/src/mesa/main/shared.c
index 6926d40..4bc93a7 100644
--- a/src/mesa/main/shared.c
+++ b/src/mesa/main/shared.c
@@ -322,46 +322,73 @@ free_shared_state(struct gl_context *ctx, struct 
gl_shared_state *shared)
/*
 * Free display lists
 */
-   _mesa_HashDeleteAll(shared->DisplayList, delete_displaylist_cb, ctx);
-   _mesa_DeleteHashTable(shared->DisplayList);
-   _mesa_HashDeleteAll(shared->BitmapAtlas, delete_bitmap_atlas_cb, ctx);
-   _mesa_DeleteHashTable(shared->BitmapAtlas);
+   if (shared->DisplayList) {
+  _mesa_HashDeleteAll(shared->DisplayList, delete_displaylist_cb, ctx);
+  _mesa_DeleteHashTable(shared->DisplayList);
+   }
+
+   if (shared->BitmapAtlas) {
+  _mesa_HashDeleteAll(shared->BitmapAtlas, delete_bitmap_atlas_cb, ctx);
+  _mesa_DeleteHashTable(shared->BitmapAtlas);
+   }
 
-   _mesa_HashWalk(shared->ShaderObjects, free_shader_program_data_cb, ctx);
-   _mesa_HashDeleteAll(shared->ShaderObjects, delete_shader_cb, ctx);
-   _mesa_DeleteHashTable(shared->ShaderObjects);
+   if (shared->ShaderObjects) {
+  _mesa_HashWalk(shared->ShaderObjects, free_shader_program_data_cb, ctx);
+  _mesa_HashDeleteAll(shared->ShaderObjects, delete_shader_cb, ctx);
+  _mesa_DeleteHashTable(shared->ShaderObjects);
+   }
 
-   _mesa_HashDeleteAll(shared->Programs, delete_program_cb, ctx);
-   _mesa_DeleteHashTable(shared->Programs);
+   if (shared->Programs) {
+  _mesa_HashDeleteAll(shared->Programs, delete_program_cb, ctx);
+  _mesa_DeleteHashTable(shared->Programs);
+   }
 
-   _mesa_reference_program(ctx, >DefaultVertexProgram, NULL);
-   _mesa_reference_program(ctx, >DefaultFragmentProgram, NULL);
+   if (shared->DefaultVertexProgram)
+  _mesa_reference_program(ctx, >DefaultVertexProgram, NULL);
 
-   _mesa_HashDeleteAll(shared->ATIShaders, delete_fragshader_cb, ctx);
-   _mesa_DeleteHashTable(shared->ATIShaders);
-   _mesa_delete_ati_fragment_shader(ctx, shared->DefaultFragmentShader);
+   if (shared->DefaultFragmentProgram)
+  _mesa_reference_program(ctx, >DefaultFragmentProgram, NULL);
 
-   _mesa_HashDeleteAll(shared->BufferObjects, delete_bufferobj_cb, ctx);
-   _mesa_DeleteHashTable(shared->BufferObjects);
+   if (shared->DefaultFragmentShader)
+  _mesa_delete_ati_fragment_shader(ctx, shared->DefaultFragmentShader);
 
-   _mesa_HashDeleteAll(shared->FrameBuffers, delete_framebuffer_cb, ctx);
-   _mesa_DeleteHashTable(shared->FrameBuffers);
-   _mesa_HashDeleteAll(shared->RenderBuffers, delete_renderbuffer_cb, ctx);
-   _mesa_DeleteHashTable(shared->RenderBuffers);
+   if (shared->ATIShaders) {
+  _mesa_HashDeleteAll(shared->ATIShaders, delete_fragshader_cb, ctx);
+  _mesa_DeleteHashTable(shared->ATIShaders);
+   }
 
-   _mesa_reference_buffer_object(ctx, >NullBufferObj, NULL);
+   if (shared->BufferObjects) {
+  _mesa_HashDeleteAll(shared->BufferObjects, delete_bufferobj_cb, ctx);
+  _mesa_DeleteHashTable(shared->BufferObjects);
+   }
 
-   {
-  struct set_entry *entry;
+   if (shared->FrameBuffers) {
+  _mesa_HashDeleteAll(shared->FrameBuffers, delete_framebuffer_cb, ctx);
+  _mesa_DeleteHashTable(shared->FrameBuffers);
+   }
+
+   if (shared->RenderBuffers) {
+  _mesa_HashDeleteAll(shared->RenderBuffers, delete_renderbuffer_cb, ctx);
+  _mesa_DeleteHashTable(shared->RenderBuffers);
+   }
+
+   if (shared->NullBufferObj)
+  _mesa_reference_buffer_object(ctx, >NullBufferObj, NULL);
 
+   if (shared->SyncObjects) {
+  struct set_entry *entry;
   set_foreach(shared->SyncObjects, entry) {
  _mesa_unref_sync_object(ctx, (struct gl_sync_object *) entry->key, 1);
   }
+
+  _mesa_set_destroy(shared->SyncObjects, NULL);
}
-   _mesa_set_destroy(shared->SyncObjects, NULL);
 
-   _mesa_HashDeleteAll(shared->SamplerObjects, delete_sampler_object_cb, ctx);
-   _mesa_DeleteHashTable(shared->SamplerObjects);
+   if (shared->SamplerObjects) {
+  _mesa_HashDeleteAll(shared->SamplerObjects, delete_sampler_object_cb,
+  ctx);
+  _mesa_DeleteHashTable(shared->SamplerObjects);
+   }
 
/*
 * Free texture objects (after FBOs since some textures might have
@@ -370,12 +397,15 @@ free_shared_state(struct gl_context *ctx, struct 
gl_shared_state *shared)
assert(ctx->Driver.DeleteTexture);
/* the default textures */
for (i = 0; i < NUM_TEXTURE_TARGETS; i++) {
-  ctx->Driver.DeleteTexture(ctx, shared->DefaultTex[i]);
+  if (shared->DefaultTex[i])
+ ctx->Driver.DeleteTexture(ctx, shared->DefaultTex[i]);
}
 
/* all other textures */
-   

[Mesa-dev] [PATCH 2/3] i965: Only do depth resolves prior to clearing when needed

[Kenneth Graunke]

From: Jason Ekstrand 

When changing the clear value, we need to resolve any fast cleared data.

Previously, we were performing resolves on every slice with HiZ enabled.
We only need to resolve slices that a) have fast clear data, and b)
aren't about to be cleared to the new color.  In the latter case, we
were actually doing a resolve, and then a fast clear - when we could
skip both, causing the existing fast cleared area to be updated to the
new clear value for no additional work.

This patch stops using intel_miptree_prepare_access in favor of a more
optimal open coded loop that knows about our clear operation.

v2: (by Ken) Rebase on islification, write a real commit message.

Reviewed-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_clear.c | 39 ---
 1 file changed, 36 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 772d7c33991..0429b3b6f51 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -165,9 +165,42 @@ brw_fast_clear_depth(struct gl_context *ctx)
 * flags out of the HiZ buffer into the real depth buffer.
 */
if (mt->fast_clear_color.f32[0] != ctx->Depth.Clear) {
-  intel_miptree_prepare_access(brw, mt, 0, INTEL_REMAINING_LEVELS,
-   0, INTEL_REMAINING_LAYERS,
-   ISL_AUX_USAGE_HIZ, false);
+  for (uint32_t level = mt->first_level; level <= mt->last_level; level++) 
{
+ if (!intel_miptree_level_has_hiz(mt, level))
+continue;
+
+ const unsigned level_layers = brw_get_num_logical_layers(mt, level);
+
+ for (uint32_t layer = 0; layer < level_layers; layer++) {
+if (level == depth_irb->mt_level &&
+layer >= depth_irb->mt_layer &&
+layer < depth_irb->mt_layer + num_layers) {
+   /* We're going to clear this layer anyway.  Leave it alone. */
+   continue;
+}
+
+enum isl_aux_state aux_state =
+   intel_miptree_get_aux_state(mt, level, layer);
+
+if (aux_state != ISL_AUX_STATE_CLEAR &&
+aux_state != ISL_AUX_STATE_COMPRESSED_CLEAR) {
+   /* This slice doesn't have any fast-cleared bits. */
+   continue;
+}
+
+/* If we got here, then the level may have fast-clear bits that
+ * use the old clear value.  We need to do a depth resolve to get
+ * rid of their use of the clear value before we can change it.
+ * Fortunately, few applications ever change their depth clear
+ * value so this shouldn't happen often.
+ */
+intel_hiz_exec(brw, mt, level, layer, 1,
+   BLORP_HIZ_OP_DEPTH_RESOLVE);
+intel_miptree_set_aux_state(brw, mt, level, layer, 1,
+ISL_AUX_STATE_RESOLVED);
+ }
+  }
+
   mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
 
-- 
2.13.3

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[Mesa-dev] [PATCH 1/3] i965: Expose get_num_logical_layers outside of intel_mipmap_tree.c.

[Kenneth Graunke]

I want to use it in brw_clear.c.
---
 src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 10 +-
 src/mesa/drivers/dri/i965/intel_mipmap_tree.h |  3 +++
 2 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index ed7cb8e2152..628d80c0ff8 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -393,8 +393,8 @@ intel_lower_compressed_format(struct brw_context *brw, 
mesa_format format)
}
 }
 
-static unsigned
-get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level)
+unsigned
+brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level)
 {
if (mt->surf.dim == ISL_SURF_DIM_3D)
   return minify(mt->surf.logical_level0_px.depth, level);
@@ -440,7 +440,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
 
uint32_t total_slices = 0;
for (uint32_t level = 0; level < levels; level++)
-  total_slices += get_num_logical_layers(mt, level);
+  total_slices += brw_get_num_logical_layers(mt, level);
 
const size_t per_level_array_size = levels * sizeof(enum isl_aux_state *);
 
@@ -458,7 +458,7 @@ create_aux_state_map(struct intel_mipmap_tree *mt,
enum isl_aux_state *s = data + per_level_array_size;
for (uint32_t level = 0; level < levels; level++) {
   per_level_arr[level] = s;
-  const unsigned level_layers = get_num_logical_layers(mt, level);
+  const unsigned level_layers = brw_get_num_logical_layers(mt, level);
   for (uint32_t a = 0; a < level_layers; a++)
  *(s++) = initial;
}
@@ -1871,7 +1871,7 @@ miptree_layer_range_length(const struct intel_mipmap_tree 
*mt, uint32_t level,
 {
assert(level <= mt->last_level);
 
-   const uint32_t total_num_layers = get_num_logical_layers(mt, level);
+   const uint32_t total_num_layers = brw_get_num_logical_layers(mt, level);
assert(start_layer < total_num_layers);
if (num_layers == INTEL_REMAINING_LAYERS)
   num_layers = total_num_layers - start_layer;
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h 
b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 3628345c4e9..2179318413e 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -419,6 +419,9 @@ intel_depth_format_for_depthstencil_format(mesa_format 
format);
 mesa_format
 intel_lower_compressed_format(struct brw_context *brw, mesa_format format);
 
+unsigned
+brw_get_num_logical_layers(const struct intel_mipmap_tree *mt, unsigned level);
+
 /** \brief Assert that the level and layer are valid for the miptree. */
 void
 intel_miptree_check_level_layer(const struct intel_mipmap_tree *mt,
-- 
2.13.3

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[Mesa-dev] [PATCH 3/3] i965/clear: Don't perform redundant depth clears

[Kenneth Graunke]

From: Jason Ekstrand 

We already have this little optimization for color clears.  Now that
we're actually tracking whether or not a slice has any fast-clear
blocks, it's easy enough to add for depth clears too.

Improves performance of GFXBench 4 TRex at 1920x1080 by:
- Skylake GT4: 0.905932% +/- 0.0620197% (n = 30)
- Apollolake:  0.382434% +/- 0.1134730% (n = 25)

v2: (by Ken) Rebase and drop intel_mipmap_tree.c changes, as they're
no longer necessary (other patches already landed to do that part)

Reviewed-by: Kenneth Graunke 
---
 src/mesa/drivers/dri/i965/brw_clear.c | 34 +++---
 1 file changed, 31 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_clear.c 
b/src/mesa/drivers/dri/i965/brw_clear.c
index 0429b3b6f51..5eb24237927 100644
--- a/src/mesa/drivers/dri/i965/brw_clear.c
+++ b/src/mesa/drivers/dri/i965/brw_clear.c
@@ -204,9 +204,37 @@ brw_fast_clear_depth(struct gl_context *ctx)
   mt->fast_clear_color.f32[0] = ctx->Depth.Clear;
}
 
-   intel_hiz_exec(brw, mt, depth_irb->mt_level,
-  depth_irb->mt_layer, num_layers,
-  BLORP_HIZ_OP_DEPTH_CLEAR);
+   bool need_clear = false;
+   for (unsigned a = 0; a < num_layers; a++) {
+  enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
+
+  if (aux_state != ISL_AUX_STATE_CLEAR) {
+ need_clear = true;
+ break;
+  }
+   }
+
+   if (!need_clear) {
+  /* If all of the layers we intend to clear are already in the clear
+   * state then simply updating the miptree fast clear value is sufficient
+   * to change their clear value.
+   */
+  return true;
+   }
+
+   for (unsigned a = 0; a < num_layers; a++) {
+  enum isl_aux_state aux_state =
+ intel_miptree_get_aux_state(mt, depth_irb->mt_level,
+ depth_irb->mt_layer + a);
+
+  if (aux_state != ISL_AUX_STATE_CLEAR) {
+ intel_hiz_exec(brw, mt, depth_irb->mt_level,
+depth_irb->mt_layer + a, 1,
+BLORP_HIZ_OP_DEPTH_CLEAR);
+  }
+   }
 
/* Now, the HiZ buffer contains data that needs to be resolved to the depth
 * buffer.
-- 
2.13.3

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Re: [Mesa-dev] [PATCH v2 17/73] radeonsi: add si_shader_selector::nir

[Marek Olšák]

For patches 9-17:

Reviewed-by: Marek Olšák 

Marek

On Wed, Jul 5, 2017 at 12:48 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> ---
>  src/gallium/drivers/radeonsi/si_shader.h | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.h 
> b/src/gallium/drivers/radeonsi/si_shader.h
> index a10067d..6de7b69 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.h
> +++ b/src/gallium/drivers/radeonsi/si_shader.h
> @@ -136,20 +136,22 @@
>  #define SI_SHADER_H
>
>  #include  /* LLVMModuleRef */
>  #include 
>  #include "tgsi/tgsi_scan.h"
>  #include "util/u_queue.h"
>
>  #include "ac_binary.h"
>  #include "si_state.h"
>
> +struct nir_shader;
> +
>  #define SI_MAX_VS_OUTPUTS  40
>
>  /* Shader IO unique indices are supported for TGSI_SEMANTIC_GENERIC with an
>   * index smaller than this.
>   */
>  #define SI_MAX_IO_GENERIC   46
>
>  /* SGPR user data indices */
>  enum {
> /* GFX9 merged shaders have RW_BUFFERS among the first 8 system SGPRs,
> @@ -313,20 +315,21 @@ struct si_shader_selector {
> /* The compiled TGSI shader expecting a prolog and/or epilog (not
>  * uploaded to a buffer).
>  */
> struct si_shader*main_shader_part;
> struct si_shader*main_shader_part_ls; /* as_ls is set in the 
> key */
> struct si_shader*main_shader_part_es; /* as_es is set in the 
> key */
>
> struct si_shader*gs_copy_shader;
>
> struct tgsi_token   *tokens;
> +   struct nir_shader   *nir;
> struct pipe_stream_output_info  so;
> struct tgsi_shader_info info;
>
> /* PIPE_SHADER_[VERTEX|FRAGMENT|...] */
> unsignedtype;
> boolvs_needs_prolog;
> unsignedpa_cl_vs_out_cntl;
> ubyte   clipdist_mask;
> ubyte   culldist_mask;
>
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

[Andy Furniss]

Christian König wrote:

Leo and Boyuan can you take a quick look as well? On first glance looks 
totally sane to me.


This reminds me .

I don't know what's special about my setup, but I haven't been able to 
use gst + vce properly since March.


As I said at the time -

https://lists.freedesktop.org/archives/mesa-dev/2017-March/148216.html

I did ping as well, but never quite got round to doing a bug.

I guess devs who tests vce with gstreamer don't see this?

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Re: [Mesa-dev] [PATCH] st/mesa: always unconditionally revalidate main framebuffer after SwapBuffers

[Edmondo Tommasina]

Tested-by: Edmondo Tommasina 

Thanks
edmondo

On Tue, Jul 25, 2017 at 6:32 PM, Marek Olšák  wrote:
> This will also go to stable.
>
> Marek
>
> On Tue, Jul 25, 2017 at 5:39 PM, Marek Olšák  wrote:
>> From: Marek Olšák 
>>
>> This fixes the black Feral launcher window.
>>
>> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867
>> ---
>>  src/mesa/state_tracker/st_manager.c | 6 ++
>>  1 file changed, 6 insertions(+)
>>
>> diff --git a/src/mesa/state_tracker/st_manager.c 
>> b/src/mesa/state_tracker/st_manager.c
>> index 834bcc9..ede5439 100644
>> --- a/src/mesa/state_tracker/st_manager.c
>> +++ b/src/mesa/state_tracker/st_manager.c
>> @@ -635,20 +635,26 @@ st_context_flush(struct st_context_iface *stctxi, 
>> unsigned flags,
>> st_flush(st, fence, pipe_flags);
>>
>> if ((flags & ST_FLUSH_WAIT) && fence) {
>>st->pipe->screen->fence_finish(st->pipe->screen, NULL, *fence,
>>   PIPE_TIMEOUT_INFINITE);
>>st->pipe->screen->fence_reference(st->pipe->screen, fence, NULL);
>> }
>>
>> if (flags & ST_FLUSH_FRONT)
>>st_manager_flush_frontbuffer(st);
>> +
>> +   /* Enter st_validate_state in the next draw call to revalidate
>> +* the framebuffer.
>> +*/
>> +   if (flags & ST_FLUSH_END_OF_FRAME)
>> +  st->gfx_shaders_may_be_dirty = true;
>>  }
>>
>>  static boolean
>>  st_context_teximage(struct st_context_iface *stctxi,
>>  enum st_texture_type tex_type,
>>  int level, enum pipe_format pipe_format,
>>  struct pipe_resource *tex, boolean mipmap)
>>  {
>> struct st_context *st = (struct st_context *) stctxi;
>> struct gl_context *ctx = st->ctx;
>> --
>> 2.7.4
>>
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[Mesa-dev] [PATCH v8 3/3] mapi/glthread: generate asynchronous code for PBO transfer

[Gregory Hainaut]

Improve speed on PCSX2

v2:
Add ppbo/ubpo status in XML file
Disable variable parameter (as the pointer would be a fixed offset)

v3:
split buffer tracking into separate patches.
use 'goto fallback_to_sync' when asynchronous transfer isn't supported

v4:
add Nicolai comment to explain why ppbo isn't impacted by the variable_params
issue

v7:
rebase (update const handling)
s/GLint pixel_pack_buffer_bound/GLuint bound_pixel_pack_buffer/

Signed-off-by: Gregory Hainaut 
---
 src/mapi/glapi/gen/ARB_direct_state_access.xml | 16 +++
 src/mapi/glapi/gen/ARB_robustness.xml  |  2 +-
 src/mapi/glapi/gen/gl_API.dtd  | 10 +
 src/mapi/glapi/gen/gl_API.xml  | 28 +-
 src/mapi/glapi/gen/gl_marshal.py   | 24 --
 src/mapi/glapi/gen/marshal_XML.py  | 21 ++-
 6 files changed, 67 insertions(+), 34 deletions(-)

diff --git a/src/mapi/glapi/gen/ARB_direct_state_access.xml 
b/src/mapi/glapi/gen/ARB_direct_state_access.xml
index 0c34b63854..c555727682 100644
--- a/src/mapi/glapi/gen/ARB_direct_state_access.xml
+++ b/src/mapi/glapi/gen/ARB_direct_state_access.xml
@@ -367,79 +367,79 @@

   
   
   
   
   
   
   

 
-   
+   
   
   
   
   
   
   
   

 
-   
+   
   
   
   
   
   
   
   
   
   

 
-   
+   
   
   
   
   
   
   
   
   
   
   
   

 
-   
+   
   
   
   
   
   
   
   

 
-   
+   
   
   
   
   
   
   
   
   
   

 
-   
+   
   
   
   
   
   
   
   
   
   
   
@@ -516,30 +516,30 @@
 

   

 

   
   

 
-   
+   
   
   
   
   
   
   

 
-   
+   
   
   
   
   

 

   
   
   
diff --git a/src/mapi/glapi/gen/ARB_robustness.xml 
b/src/mapi/glapi/gen/ARB_robustness.xml
index 9b2f2f0a74..6e1ac09ce0 100644
--- a/src/mapi/glapi/gen/ARB_robustness.xml
+++ b/src/mapi/glapi/gen/ARB_robustness.xml
@@ -75,21 +75,21 @@
 
 
 
 
 
 
 
 
 
 
-
+
 
 
 
 
 
 
 
 
 
 
diff --git a/src/mapi/glapi/gen/gl_API.dtd b/src/mapi/glapi/gen/gl_API.dtd
index b464250777..447b03a41d 100644
--- a/src/mapi/glapi/gen/gl_API.dtd
+++ b/src/mapi/glapi/gen/gl_API.dtd
@@ -115,28 +115,30 @@ param:
  img_send_null - boolean flag to determine if blank pixel data should
 be sent when a NULL pointer is passed.  This is only used by
 TexImage1D and TexImage2D.
  img_null_flag - boolean flag to determine if an extra flag is used to
 determine if a NULL pixel pointer was passed.  This is used by
 TexSubImage1D, TexSubImage2D, TexImage3D and others.
  img_pad_dimensions - boolean flag to determine if dimension data and
 offset data should be padded to the next even number of dimensions.
 For example, this will insert an empty "height" field after the
 "width" field in the protocol for TexImage1D.
- marshal - One of "sync", "async", "draw", or "custom", defaulting to
-async unless one of the arguments is something we know we can't
-codegen for.  If "sync", we finish any queued glthread work and call
+ marshal - One of "sync", "async", "draw", "ppbo", "upbo" or "custom",
+defaulting to async unless one of the arguments is something we know we
+can't codegen for.  If "sync", we finish any queued glthread work and 
call
 the Mesa implementation directly.  If "async", we queue the function
 call to be performed by glthread.  If "custom", the prototype will be
 generated but a custom implementation will be present in marshal.c.
 If "draw", it will follow the "async" rules except that "indices" are
-ignored (since they may come from a VBO).
+ignored (since they may come from a VBO). If "ppbo"/"upbo", it will
+follow the "async" rules when a pack/unpack pixel buffer is bound
+otherwise it will follow the "sync" rules.
  marshal_fail - an expression that, if it evaluates true, causes glthread
 to switch back to the Mesa implementation and call it directly.  Used
 to disable glthread for GL compatibility interactions that we don't
 want to track state for.
 
 glx:
  rop - Opcode value for "render" commands
  sop - Opcode value for "single" commands
  vendorpriv - Opcode value for vendor private (or vendor private with
  reply) commands
diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 4b01ca552f..f7c8a21759 100644
--- a/src/mapi/glapi/gen/gl_API.xml

[Mesa-dev] [PATCH v8 2/3] mesa/glthread: add tracking of PBO binding

[Gregory Hainaut]

In gl core, buffer must be reserved first by CreateBuffers/GenBuffers
to be valid.

v4: update comments based on Nicolai review

v7:
s/GLint pixel_pack_buffer_bound/GLuint bound_pixel_pack_buffer/
Drop the ShadowBufferObjects hash. Synchronous creation/destruction
gives us enough guarantee to lookup the BufferObjects hash directly.

Signed-off-by: Gregory Hainaut 
---
 src/mesa/main/marshal.c | 36 +---
 1 file changed, 33 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/marshal.c b/src/mesa/main/marshal.c
index 1914b5..285a46457d 100644
--- a/src/mesa/main/marshal.c
+++ b/src/mesa/main/marshal.c
@@ -237,21 +237,34 @@ _mesa_unmarshal_DeleteBuffers(struct gl_context *ctx,
 
 /* BindBufferBase: marshalled asynchronously */
 struct marshal_cmd_BindBufferBase
 {
struct marshal_cmd_base cmd_base;
GLenum target;
GLuint index;
GLuint buffer;
 };
 
-/** Tracks the current bindings for the vertex array and index array buffers.
+/**
+ * Check that buffer is a valid buffer handle
+ * Always return false for ID 0.
+ */
+static bool
+is_bufferobj(struct gl_context *ctx, GLuint buffer)
+{
+   if (buffer == 0)
+  return false;
+   else
+  return _mesa_HashLookup(ctx->Shared->BufferObjects, buffer) != NULL;
+}
+
+/** Tracks the current bindings of GL buffer targets
  *
  * This is part of what we need to enable glthread on compat-GL contexts that
  * happen to use VBOs, without also supporting the full tracking of VBO vs
  * user vertex array bindings per attribute on each vertex array for
  * determining what to upload at draw call time.
  *
  * Note that GL core makes it so that a buffer binding with an invalid handle
  * in the "buffer" parameter will throw an error, and then a
  * glVertexAttribPointer() that followsmight not end up pointing at a VBO.
  * However, in GL core the draw call would throw an error as well, so we don't
@@ -259,37 +272,54 @@ struct marshal_cmd_BindBufferBase
  * marshal user data for draw calls, and the unmarshal will just generate an
  * error or not as appropriate.
  *
  * For compatibility GL, we do need to accurately know whether the draw call
  * on the unmarshal side will dereference a user pointer or load data from a
  * VBO per vertex.  That would make it seem like we need to track whether a
  * "buffer" is valid, so that we can know when an error will be generated
  * instead of updating the binding.  However, compat GL has the ridiculous
  * feature that if you pass a bad name, it just gens a buffer object for you,
  * so we escape without having to know if things are valid or not.
+ *
+ * Pixel buffers are tracked to decide whether pixel transfer goes to a user
+ * pointer (must be synchronous) or a GL buffer (can be asynchronous). Unlike
+ * for VBOs, we do need accurate tracking, since user pointers can be used in
+ * GL core contexts.
  */
 static void
-track_vbo_binding(struct gl_context *ctx, GLenum target, GLuint buffer)
+track_buffers_binding(struct gl_context *ctx, GLenum target, GLuint buffer)
 {
struct glthread_state *glthread = ctx->GLThread;
 
switch (target) {
case GL_ARRAY_BUFFER:
   glthread->vertex_array_is_vbo = (buffer != 0);
   break;
case GL_ELEMENT_ARRAY_BUFFER:
   /* The current element array buffer binding is actually tracked in the
* vertex array object instead of the context, so this would need to
* change on vertex array object updates.
*/
   glthread->element_array_is_vbo = (buffer != 0);
   break;
+   case GL_PIXEL_UNPACK_BUFFER:
+  if (ctx->API == API_OPENGL_COMPAT || is_bufferobj(ctx, buffer))
+ glthread->bound_pixel_unpack_buffer = buffer;
+  else
+ glthread->bound_pixel_unpack_buffer = 0;
+  break;
+   case GL_PIXEL_PACK_BUFFER:
+  if (ctx->API == API_OPENGL_COMPAT || is_bufferobj(ctx, buffer))
+ glthread->bound_pixel_pack_buffer = buffer;
+  else
+ glthread->bound_pixel_pack_buffer = 0;
+  break;
}
 }
 
 
 struct marshal_cmd_BindBuffer
 {
struct marshal_cmd_base cmd_base;
GLenum target;
GLuint buffer;
 };
@@ -307,21 +337,21 @@ _mesa_unmarshal_BindBuffer(struct gl_context *ctx,
CALL_BindBuffer(ctx->CurrentServerDispatch, (target, buffer));
 }
 void GLAPIENTRY
 _mesa_marshal_BindBuffer(GLenum target, GLuint buffer)
 {
GET_CURRENT_CONTEXT(ctx);
size_t cmd_size = sizeof(struct marshal_cmd_BindBuffer);
struct marshal_cmd_BindBuffer *cmd;
debug_print_marshal("BindBuffer");
 
-   track_vbo_binding(ctx, target, buffer);
+   track_buffers_binding(ctx, target, buffer);
 
if (cmd_size <= MARSHAL_MAX_CMD_SIZE) {
   cmd = _mesa_glthread_allocate_command(ctx, DISPATCH_CMD_BindBuffer,
 cmd_size);
   cmd->target = target;
   cmd->buffer = buffer;
   _mesa_post_marshal_hook(ctx);
} else {
   _mesa_glthread_finish(ctx);
   

[Mesa-dev] [PATCH v8 1/3] mesa/glthread: track buffer destruction

[Gregory Hainaut]

It would be used in following commits to allow asynchronous PBO transfer.

The tracking saves the buffer name into a hash. Saving pointer
will be more complex as the buffer is created in BindBuffer due to IsBuffer
insanity.

Perf wise DeleteBuffers is now synchronous for robustness.

v5: properly delete hash element with the help of _mesa_HashDeleteAll

v6: rebase

v7: rebase
s/GLint pixel_pack_buffer_bound/GLuint bound_pixel_pack_buffer/
Drop the ShadowBufferObjects hash. Synchronous creation/destruction
gives us enough guarantee to lookup the BufferObjects hash directly.
Drop custom code for GenBuffers/CreateBuffers

v8: rebase
Signed-off-by: Gregory Hainaut 
---
 src/mapi/glapi/gen/gl_API.xml |  2 +-
 src/mesa/main/glthread.h  | 10 ++
 src/mesa/main/marshal.c   | 40 
 src/mesa/main/marshal.h   |  8 
 4 files changed, 59 insertions(+), 1 deletion(-)

diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 18839ec70c..4b01ca552f 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -5055,21 +5055,21 @@
 
 
 
 
 
 
 
 
 
-
+
 
 
 
 
 
 
 
 
 
 
diff --git a/src/mesa/main/glthread.h b/src/mesa/main/glthread.h
index 306246ca1c..e5c8b79a97 100644
--- a/src/mesa/main/glthread.h
+++ b/src/mesa/main/glthread.h
@@ -88,20 +88,30 @@ struct glthread_state
 * Tracks on the main thread side whether the current vertex array binding
 * is in a VBO.
 */
bool vertex_array_is_vbo;
 
/**
 * Tracks on the main thread side whether the current element array (index
 * buffer) binding is in a VBO.
 */
bool element_array_is_vbo;
+
+   /**
+* Tracks on the main thread side the bound unpack pixel buffer
+*/
+   GLuint bound_pixel_unpack_buffer;
+
+   /**
+* Tracks on the main thread side the bound pack pixel buffer
+*/
+   GLuint bound_pixel_pack_buffer;
 };
 
 void _mesa_glthread_init(struct gl_context *ctx);
 void _mesa_glthread_destroy(struct gl_context *ctx);
 
 void _mesa_glthread_restore_dispatch(struct gl_context *ctx);
 void _mesa_glthread_flush_batch(struct gl_context *ctx);
 void _mesa_glthread_finish(struct gl_context *ctx);
 
 #endif /* _GLTHREAD_H*/
diff --git a/src/mesa/main/marshal.c b/src/mesa/main/marshal.c
index 8f8e8c78ed..1914b5 100644
--- a/src/mesa/main/marshal.c
+++ b/src/mesa/main/marshal.c
@@ -25,20 +25,21 @@
  *
  * Custom functions for marshalling GL calls from the main thread to a worker
  * thread when automatic code generation isn't appropriate.
  */
 
 #include "main/enums.h"
 #include "main/macros.h"
 #include "marshal.h"
 #include "dispatch.h"
 #include "marshal_generated.h"
+#include "hash.h"
 
 struct marshal_cmd_Flush
 {
struct marshal_cmd_base cmd_base;
 };
 
 
 void
 _mesa_unmarshal_Flush(struct gl_context *ctx,
   const struct marshal_cmd_Flush *cmd)
@@ -188,20 +189,59 @@ _mesa_marshal_ShaderSource(GLuint shader, GLsizei count,
   _mesa_post_marshal_hook(ctx);
} else {
   _mesa_glthread_finish(ctx);
   CALL_ShaderSource(ctx->CurrentServerDispatch,
 (shader, count, string, length_tmp));
}
free(length_tmp);
 }
 
 
+static void track_buffers_destruction(struct gl_context *ctx,
+  GLsizei n, const GLuint * buffers)
+{
+   GLsizei i;
+   struct glthread_state *glthread = ctx->GLThread;
+
+   if (n < 0 || !buffers)
+  return;
+
+   for (i = 0; i < n ; i++) {
+  if (buffers[i] == glthread->bound_pixel_pack_buffer)
+ glthread->bound_pixel_pack_buffer = 0;
+
+  if (buffers[i] == glthread->bound_pixel_unpack_buffer)
+ glthread->bound_pixel_unpack_buffer = 0;
+   }
+}
+
+/* DeleteBuffers: custom marshal to track buffers destruction */
+void GLAPIENTRY
+_mesa_marshal_DeleteBuffers(GLsizei n, const GLuint * buffer)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   _mesa_glthread_finish(ctx);
+   debug_print_sync("DeleteBuffers");
+
+   // It is done before CALL_DeleteBuffers to avoid any ABA multithread issue.
+   track_buffers_destruction(ctx, n, buffer);
+
+   CALL_DeleteBuffers(ctx->CurrentServerDispatch, (n, buffer));
+}
+
+void
+_mesa_unmarshal_DeleteBuffers(struct gl_context *ctx,
+   const struct marshal_cmd_DeleteBuffers *cmd)
+{
+   assert(0);
+}
+
 /* BindBufferBase: marshalled asynchronously */
 struct marshal_cmd_BindBufferBase
 {
struct marshal_cmd_base cmd_base;
GLenum target;
GLuint index;
GLuint buffer;
 };
 
 /** Tracks the current bindings for the vertex array and index array buffers.
diff --git a/src/mesa/main/marshal.h b/src/mesa/main/marshal.h
index 63e0295576..e7f681213c 100644
--- a/src/mesa/main/marshal.h
+++ b/src/mesa/main/marshal.h
@@ -180,20 +180,21 @@ struct marshal_cmd_Flush;
 struct marshal_cmd_BindBuffer;
 struct 

[Mesa-dev] [PATCH v8 0/3] asynchronous pbo transfer with glthread

[Gregory Hainaut]

Hello Mesa developers,

> Please find a new version to handle invalid buffer handles.
>
> Allow to handle this kind of case:
>genBuffer();
>BindBuffer(pbo)
>DeleteBuffer(pbo);
>BindBuffer(rand_pbo)
>TexSubImage2D(user_memory_pointer); // Data transfer will be synchronous
>
> There are various subtely to handle multi threaded shared context. In order to
> keep the code sane, I've considered a buffer invalid when it is deleted by a
> context even it is still bound to others contexts. It will force a synchronous
> transfer which is always safe.
>
> An example could be
>Ctx A: glGenBuffers(1, );
>Ctx A: glBindBuffer(PIXEL_UNPACK_BUFFER, pbo);
>Ctx B: glDeleteBuffers(1, );
>Ctx A: glTexSubImage2D(...); // will be synchronous, even though it
>_could_ be asynchronous (because the PBO that was generated first is
>still bound!)

V3: I mixed up the number so I jumped right away to v4...
V4: improve commments based on Nicolai feedback
V5: Properly delete element of the new hash (first patch)
v6: Rebase on latest master
v7: Fredrik's suggestion (remove shadow hash table
and rename pixel_*pack_buffer_bound variables)
I rebased the code on latest master, it got extra conflict (gl_marshal.py) since
the resent from Timothy
v8: rebase on latest master

Best regards,

Gregory Hainaut (3):
  mesa/glthread: track buffer destruction
  mesa/glthread: add tracking of PBO binding
  mapi/glthread: generate asynchronous code for PBO transfer

 src/mapi/glapi/gen/ARB_direct_state_access.xml | 16 +++---
 src/mapi/glapi/gen/ARB_robustness.xml  |  2 +-
 src/mapi/glapi/gen/gl_API.dtd  | 10 ++--
 src/mapi/glapi/gen/gl_API.xml  | 30 +-
 src/mapi/glapi/gen/gl_marshal.py   | 24 +++-
 src/mapi/glapi/gen/marshal_XML.py  | 21 +--
 src/mesa/main/glthread.h   | 10 
 src/mesa/main/marshal.c| 76 +-
 src/mesa/main/marshal.h|  8 +++
 9 files changed, 159 insertions(+), 38 deletions(-)

-- 
2.11.0

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Re: [Mesa-dev] [Mesa-stable] [PATCH] mesa: fix mismatch when returning 64-bit bindless uniform handles

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jul 25, 2017 at 9:39 PM, Samuel Pitoiset
 wrote:
> The slower convert-and-copy process performs a bad conversion
> because it converts the value to signed 64-bit integer, but
> bindless uniform handles are considered unsigned 64-bit.
>
> This fixes "Check glUniform*() with mixed texture units/handles"
> from arb_bindless_texture-uniform piglit.
>
> Signed-off-by: Samuel Pitoiset 
> Cc: "17.2" 
> ---
>  src/mesa/main/uniform_query.cpp | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
> index 928d3ce4fd..a48b6d2921 100644
> --- a/src/mesa/main/uniform_query.cpp
> +++ b/src/mesa/main/uniform_query.cpp
> @@ -358,7 +358,8 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
> GLint location,
> */
>if (returnType == uni->type->base_type ||
>((returnType == GLSL_TYPE_INT || returnType == GLSL_TYPE_UINT) &&
> -   (uni->type->is_sampler() || uni->type->is_image( {
> +   (uni->type->is_sampler() || uni->type->is_image())) ||
> +  (returnType == GLSL_TYPE_UINT64 && uni->is_bindless)) {
>   memcpy(paramsOut, src, bytes);
>} else {
>   union gl_constant_value *const dst =
> --
> 2.13.3
>
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Re: [Mesa-dev] [PATCH v2 07/73] st/glsl_to_nir: fix the case where NIR clone testing is enabled

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Wed, Jul 5, 2017 at 12:47 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> In that case, prog->nir must be assigned at the end.
> ---
>  src/mesa/state_tracker/st_glsl_to_nir.cpp | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_glsl_to_nir.cpp 
> b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> index 89f7888..5c4ae81 100644
> --- a/src/mesa/state_tracker/st_glsl_to_nir.cpp
> +++ b/src/mesa/state_tracker/st_glsl_to_nir.cpp
> @@ -229,21 +229,20 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
> *prog,
> assert(pscreen->get_compiler_options);   /* drivers using NIR must 
> implement this */
>
> options = (const nir_shader_compiler_options *)
>pscreen->get_compiler_options(pscreen, PIPE_SHADER_IR_NIR, ptarget);
> assert(options);
>
> if (prog->nir)
>return prog->nir;
>
> nir = glsl_to_nir(shader_program, stage, options);
> -   prog->nir = nir;
>
> NIR_PASS_V(nir, nir_lower_io_to_temporaries,
>   nir_shader_get_entrypoint(nir),
>   true, true);
> NIR_PASS_V(nir, nir_lower_global_vars_to_local);
> NIR_PASS_V(nir, nir_split_var_copies);
> NIR_PASS_V(nir, nir_lower_var_copies);
> NIR_PASS_V(nir, st_nir_lower_builtin);
> NIR_PASS_V(nir, nir_lower_atomics, shader_program);
>
> @@ -274,20 +273,22 @@ st_glsl_to_nir(struct st_context *st, struct gl_program 
> *prog,
>
> if (st->ctx->_Shader->Flags & GLSL_DUMP) {
>_mesa_log("\n");
>_mesa_log("NIR IR for linked %s program %d:\n",
>   _mesa_shader_stage_to_string(stage),
>   shader_program->Name);
>nir_print_shader(nir, _mesa_get_log_file());
>_mesa_log("\n\n");
> }
>
> +   prog->nir = nir;
> +
> return nir;
>  }
>
>  /* TODO any better helper somewhere to sort a list? */
>
>  static void
>  insert_sorted(struct exec_list *var_list, nir_variable *new_var)
>  {
> nir_foreach_variable(var, var_list) {
>if (var->data.location > new_var->data.location) {
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH] mesa: fix mismatch when returning 64-bit bindless uniform handles

[Samuel Pitoiset]

On 07/25/2017 09:47 PM, Ilia Mirkin wrote:

On Tue, Jul 25, 2017 at 3:39 PM, Samuel Pitoiset
 wrote:

The slower convert-and-copy process performs a bad conversion
because it converts the value to signed 64-bit integer, but
bindless uniform handles are considered unsigned 64-bit.

This fixes "Check glUniform*() with mixed texture units/handles"
from arb_bindless_texture-uniform piglit.

Signed-off-by: Samuel Pitoiset 
Cc: "17.2" 
---
  src/mesa/main/uniform_query.cpp | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 928d3ce4fd..a48b6d2921 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -358,7 +358,8 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
 */
if (returnType == uni->type->base_type ||
((returnType == GLSL_TYPE_INT || returnType == GLSL_TYPE_UINT) &&
-   (uni->type->is_sampler() || uni->type->is_image( {
+   (uni->type->is_sampler() || uni->type->is_image())) ||
+  (returnType == GLSL_TYPE_UINT64 && uni->is_bindless)) {


Won't this mess things up for when returnType == INT and
uni->type->is_sampler() but uni->is_bindless is true? Or can that not
happen?


Shouldn't happen because rmul/dmul are correctly set (ie. src and dst 
offsets are good). See my recent piglit patch.




   -ilia

P.S. yes, that's a pre-existing issue in this code...


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Re: [Mesa-dev] [PATCH] mesa: fix mismatch when returning 64-bit bindless uniform handles

[Ilia Mirkin]

On Tue, Jul 25, 2017 at 3:39 PM, Samuel Pitoiset
 wrote:
> The slower convert-and-copy process performs a bad conversion
> because it converts the value to signed 64-bit integer, but
> bindless uniform handles are considered unsigned 64-bit.
>
> This fixes "Check glUniform*() with mixed texture units/handles"
> from arb_bindless_texture-uniform piglit.
>
> Signed-off-by: Samuel Pitoiset 
> Cc: "17.2" 
> ---
>  src/mesa/main/uniform_query.cpp | 3 ++-
>  1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
> index 928d3ce4fd..a48b6d2921 100644
> --- a/src/mesa/main/uniform_query.cpp
> +++ b/src/mesa/main/uniform_query.cpp
> @@ -358,7 +358,8 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
> GLint location,
> */
>if (returnType == uni->type->base_type ||
>((returnType == GLSL_TYPE_INT || returnType == GLSL_TYPE_UINT) &&
> -   (uni->type->is_sampler() || uni->type->is_image( {
> +   (uni->type->is_sampler() || uni->type->is_image())) ||
> +  (returnType == GLSL_TYPE_UINT64 && uni->is_bindless)) {

Won't this mess things up for when returnType == INT and
uni->type->is_sampler() but uni->is_bindless is true? Or can that not
happen?

  -ilia

P.S. yes, that's a pre-existing issue in this code...
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[Mesa-dev] [PATCH] mesa: fix mismatch when returning 64-bit bindless uniform handles

[Samuel Pitoiset]

The slower convert-and-copy process performs a bad conversion
because it converts the value to signed 64-bit integer, but
bindless uniform handles are considered unsigned 64-bit.

This fixes "Check glUniform*() with mixed texture units/handles"
from arb_bindless_texture-uniform piglit.

Signed-off-by: Samuel Pitoiset 
Cc: "17.2" 
---
 src/mesa/main/uniform_query.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/mesa/main/uniform_query.cpp b/src/mesa/main/uniform_query.cpp
index 928d3ce4fd..a48b6d2921 100644
--- a/src/mesa/main/uniform_query.cpp
+++ b/src/mesa/main/uniform_query.cpp
@@ -358,7 +358,8 @@ _mesa_get_uniform(struct gl_context *ctx, GLuint program, 
GLint location,
*/
   if (returnType == uni->type->base_type ||
   ((returnType == GLSL_TYPE_INT || returnType == GLSL_TYPE_UINT) &&
-   (uni->type->is_sampler() || uni->type->is_image( {
+   (uni->type->is_sampler() || uni->type->is_image())) ||
+  (returnType == GLSL_TYPE_UINT64 && uni->is_bindless)) {
  memcpy(paramsOut, src, bytes);
   } else {
  union gl_constant_value *const dst =
-- 
2.13.3

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[Mesa-dev] [Bug 77449] Tracker bug for all bugs related to Steam titles

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=77449
Bug 77449 depends on bug 99136, which changed state.

Bug 99136 Summary: Blood Effects corrupt graphics in Total War: Warhammer
https://bugs.freedesktop.org/show_bug.cgi?id=99136

   What|Removed |Added

 Status|REOPENED|RESOLVED
 Resolution|--- |INVALID

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Re: [Mesa-dev] [PATCH] st/mesa: fix the unconditional return in st_framebuffer_iface_remove

[Bas Nieuwenhuizen]

Per  https://www.mesa3d.org/submittingpatches.html, just a Fixes tag
should be enough to get in all the stable branches that still get
updated and contain the commit that is referenced.

- Bas

On Tue, Jul 25, 2017 at 8:55 PM, Marek Olšák  wrote:
> I've already sent a patch for this bug, but in the future, please mark
> all patches that should be in stable by adding the proper Cc tag.
>
> Thanks,
> Marek
>
> On Tue, Jul 25, 2017 at 2:00 AM, Charmaine Lee  wrote:
>> Fixes: bbc29393d3beaf6344c7188547b4ff61b63946ae
>> Tested-by: Christoph Haag 
>> ---
>>  src/mesa/state_tracker/st_manager.c | 2 +-
>>  1 file changed, 1 insertion(+), 1 deletion(-)
>>
>> diff --git a/src/mesa/state_tracker/st_manager.c 
>> b/src/mesa/state_tracker/st_manager.c
>> index 834bcc9..6447403 100644
>> --- a/src/mesa/state_tracker/st_manager.c
>> +++ b/src/mesa/state_tracker/st_manager.c
>> @@ -560,7 +560,7 @@ st_framebuffer_iface_remove(struct st_manager *smapi,
>>(struct st_manager_private *)smapi->st_manager_private;
>> struct hash_entry *entry;
>>
>> -   if (!smPriv || !smPriv->stfbi_ht);
>> +   if (!smPriv || !smPriv->stfbi_ht)
>>return;
>>
>> mtx_lock(>st_mutex);
>> --
>> 1.9.1
>>
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Re: [Mesa-dev] threaded opengl

[Marek Olšák]

Hi,

What is your CPU, GPU, and how much improvement did you get?

Thanks,
Marek

On Tue, Jul 18, 2017 at 11:10 PM, siyia  wrote:
> sorry executable is "mb_warband_linux" start.sh or mb_warband.sh are local
> scripts to start the game so:
>
> 
>
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Re: [Mesa-dev] [PATCH] ac/surface: fix hybrid graphics where APU=GFX9, dGPU=older

[Alex Deucher]

On Tue, Jul 25, 2017 at 12:38 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> Cc: 17.2 

Reviewed-by: Alex Deucher 

> ---
>  src/amd/common/ac_surface.c | 11 +++
>  1 file changed, 11 insertions(+)
>
> diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
> index cd3d7b7..9e5390b 100644
> --- a/src/amd/common/ac_surface.c
> +++ b/src/amd/common/ac_surface.c
> @@ -250,20 +250,31 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
>   ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
>   ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
>  {
> struct legacy_surf_level *surf_level;
> ADDR_E_RETURNCODE ret;
>
> AddrSurfInfoIn->mipLevel = level;
> AddrSurfInfoIn->width = u_minify(config->info.width, level);
> AddrSurfInfoIn->height = u_minify(config->info.height, level);
>
> +   /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
> +* because GFX9 needs linear alignment of 256 bytes.
> +*/
> +   if (config->info.levels == 1 &&
> +   AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED) {
> +   unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
> +
> +   assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
> +   AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, 
> alignment);
> +   }
> +
> if (config->is_3d)
> AddrSurfInfoIn->numSlices = u_minify(config->info.depth, 
> level);
> else if (config->is_cube)
> AddrSurfInfoIn->numSlices = 6;
> else
> AddrSurfInfoIn->numSlices = config->info.array_size;
>
> if (level > 0) {
> /* Set the base level pitch. This is needed for calculation
>  * of non-zero levels. */
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] st/mesa: fix the unconditional return in st_framebuffer_iface_remove

[Marek Olšák]

I've already sent a patch for this bug, but in the future, please mark
all patches that should be in stable by adding the proper Cc tag.

Thanks,
Marek

On Tue, Jul 25, 2017 at 2:00 AM, Charmaine Lee  wrote:
> Fixes: bbc29393d3beaf6344c7188547b4ff61b63946ae
> Tested-by: Christoph Haag 
> ---
>  src/mesa/state_tracker/st_manager.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/mesa/state_tracker/st_manager.c 
> b/src/mesa/state_tracker/st_manager.c
> index 834bcc9..6447403 100644
> --- a/src/mesa/state_tracker/st_manager.c
> +++ b/src/mesa/state_tracker/st_manager.c
> @@ -560,7 +560,7 @@ st_framebuffer_iface_remove(struct st_manager *smapi,
>(struct st_manager_private *)smapi->st_manager_private;
> struct hash_entry *entry;
>
> -   if (!smPriv || !smPriv->stfbi_ht);
> +   if (!smPriv || !smPriv->stfbi_ht)
>return;
>
> mtx_lock(>st_mutex);
> --
> 1.9.1
>
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Re: [Mesa-dev] [PATCH v2 1/2] st/dri: Check get-handle return value in queryImage

[Daniel Stone]

On 25 July 2017 at 19:08, Emil Velikov  wrote:
> On 24 July 2017 at 16:46, Daniel Stone  wrote:
>> In the DRIImage queryImage hook, check if resource_get_handle() failed
>> and return FALSE if so.
>>
> Wanted to say huge thank you for sorting these out (sorry for being
> slow to actually review it).
>
> I think we'd want this patch in stable. Please "shout" if that's not the case.

Thanks Emil - for stable would be great please!

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH 5/5] radeonsi: bail out instead of crashing if the main shader part failed to compile

[Marek Olšák]

Patches 1, 3-5:

Reviewed: Marek Olšák 

Marek

On Mon, Jul 17, 2017 at 12:57 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> ---
>  src/gallium/drivers/radeonsi/si_shader.c | 3 +++
>  1 file changed, 3 insertions(+)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index af93ca1..30de03f 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -7359,20 +7359,23 @@ int si_shader_create(struct si_screen *sscreen, 
> LLVMTargetMachineRef tm,
>  * - the prolog part is inserted at the beginning
>  * - the epilog part is inserted at the end
>  *
>  * The prolog and epilog have many (but simple) variants.
>  *
>  * Starting with gfx9, geometry and tessellation control
>  * shaders also contain the prolog and user shader parts of
>  * the previous shader stage.
>  */
>
> +   if (!mainp)
> +   return -1;
> +
> /* Copy the compiled TGSI shader data over. */
> shader->is_binary_shared = true;
> shader->binary = mainp->binary;
> shader->config = mainp->config;
> shader->info.num_input_sgprs = mainp->info.num_input_sgprs;
> shader->info.num_input_vgprs = mainp->info.num_input_vgprs;
> shader->info.face_vgpr_index = mainp->info.face_vgpr_index;
> memcpy(shader->info.vs_output_param_offset,
>mainp->info.vs_output_param_offset,
>sizeof(mainp->info.vs_output_param_offset));
> --
> 2.9.3
>
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Re: [Mesa-dev] [Mesa-stable] [PATCH 2/5] radeonsi/gfx9: always wrap GS and TCS in an if-block

[Marek Olšák]

On Mon, Jul 17, 2017 at 12:57 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> With merged ESGS shaders, the GS part of a wave may be empty, and the
> hardware gets confused if any GS messages are sent from that wave. Since
> S_SENDMSG is executed even when EXEC = 0, we have to wrap even
> non-monolithic GS shaders in an if-block, so that the entire shader and
> hence the S_SENDMSG instructions are skipped in empty waves.
>
> This change is not required for TCS/HS, but applying it there as well
> simplifies the code a bit.
>
> Fixes GL45-CTS.geometry_shader.rendering.rendering.*
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/gallium/drivers/radeonsi/si_shader.c  | 74 
> +--
>  src/gallium/drivers/radeonsi/si_shader_internal.h |  3 +
>  2 files changed, 45 insertions(+), 32 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_shader.c 
> b/src/gallium/drivers/radeonsi/si_shader.c
> index 7a44e61..9aeda49 100644
> --- a/src/gallium/drivers/radeonsi/si_shader.c
> +++ b/src/gallium/drivers/radeonsi/si_shader.c
> @@ -2713,20 +2713,23 @@ si_insert_input_ptr_as_2xi32(struct si_shader_context 
> *ctx, LLVMValueRef ret,
>  }
>
>  /* This only writes the tessellation factor levels. */
>  static void si_llvm_emit_tcs_epilogue(struct lp_build_tgsi_context *bld_base)
>  {
> struct si_shader_context *ctx = si_shader_context(bld_base);
> LLVMValueRef rel_patch_id, invocation_id, tf_lds_offset;
>
> si_copy_tcs_inputs(bld_base);
>
> +   if (ctx->screen->b.chip_class >= GFX9)
> +   lp_build_endif(>merged_wrap_if_state);
> +
> rel_patch_id = get_rel_patch_id(ctx);
> invocation_id = unpack_param(ctx, ctx->param_tcs_rel_ids, 8, 5);
> tf_lds_offset = get_tcs_out_current_patch_data_offset(ctx);
>
> /* Return epilog parameters from this function. */
> LLVMBuilderRef builder = ctx->gallivm.builder;
> LLVMValueRef ret = ctx->return_value;
> unsigned vgpr;
>
> if (ctx->screen->b.chip_class >= GFX9) {
> @@ -2946,20 +2949,23 @@ static LLVMValueRef si_get_gs_wave_id(struct 
> si_shader_context *ctx)
> else
> return LLVMGetParam(ctx->main_fn, ctx->param_gs_wave_id);
>  }
>
>  static void si_llvm_emit_gs_epilogue(struct lp_build_tgsi_context *bld_base)
>  {
> struct si_shader_context *ctx = si_shader_context(bld_base);
>
> ac_build_sendmsg(>ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE,
>  si_get_gs_wave_id(ctx));
> +
> +   if (ctx->screen->b.chip_class >= GFX9)
> +   lp_build_endif(>merged_wrap_if_state);
>  }
>
>  static void si_llvm_emit_vs_epilogue(struct lp_build_tgsi_context *bld_base)
>  {
> struct si_shader_context *ctx = si_shader_context(bld_base);
> struct gallivm_state *gallivm = >gallivm;
> struct tgsi_shader_info *info = >shader->selector->info;
> struct si_shader_output_values *outputs = NULL;
> int i,j;
>
> @@ -5523,39 +5529,55 @@ static bool si_compile_tgsi_main(struct 
> si_shader_context *ctx,
> break;
> default:
> assert(!"Unsupported shader type");
> return false;
> }
>
> create_function(ctx);
> preload_ring_buffers(ctx);
>
> /* For GFX9 merged shaders:
> -* - Set EXEC. If the prolog is present, set EXEC there instead.
> +* - Set EXEC for the first shader. If the prolog is present, set
> +*   EXEC there instead.
>  * - Add a barrier before the second shader.
> +* - In the second shader, reset EXEC to ~0 and wrap the main part in
> +*   an if-statement. This is required for correctness in geometry
> +*   shaders, to ensure that empty GS waves do not send GS_EMIT and
> +*   GS_CUT messages.
>  *
> -* The same thing for monolithic shaders is done in
> -* si_build_wrapper_function.
> +* For monolithic merged shaders, the first shader is wrapped in an
> +* if-block together with its prolog in si_build_wrapper_function.
>  */
> -   if (ctx->screen->b.chip_class >= GFX9 && !is_monolithic) {
> -   if (sel->info.num_instructions > 1 && /* not empty shader */
> +   if (ctx->screen->b.chip_class >= GFX9) {
> +   if (!is_monolithic &&
> +   sel->info.num_instructions > 1 && /* not empty shader */
> (shader->key.as_es || shader->key.as_ls) &&
> (ctx->type == PIPE_SHADER_TESS_EVAL ||
>  (ctx->type == PIPE_SHADER_VERTEX &&
>   !sel->vs_needs_prolog))) {
> si_init_exec_from_input(ctx,
> ctx->param_merged_wave_info, 
> 0);
> } else if (ctx->type == PIPE_SHADER_TESS_CTRL ||
>ctx->type 

[Mesa-dev] [PATCH] st/mesa: fix the unconditional return in st_framebuffer_iface_remove

[Charmaine Lee]

Fixes: bbc29393d3beaf6344c7188547b4ff61b63946ae
Tested-by: Christoph Haag 
---
 src/mesa/state_tracker/st_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index 834bcc9..6447403 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -560,7 +560,7 @@ st_framebuffer_iface_remove(struct st_manager *smapi,
   (struct st_manager_private *)smapi->st_manager_private;
struct hash_entry *entry;
 
-   if (!smPriv || !smPriv->stfbi_ht);
+   if (!smPriv || !smPriv->stfbi_ht)
   return;
 
mtx_lock(>st_mutex);
-- 
1.9.1

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Re: [Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

[Christian König]

Am 25.07.2017 um 16:31 schrieb Julien Isorce:

The picture_is was assumed to be a frame number so in 0-31.


Typo in the commit message, that should read "picture_id", not "picture_is".


But the vaapi client gstreamer-vaapi uses the surfaces handles
as identifier which are unsigned int.

This bug can happen when using a lot of vaapi surfaces within
the same process. Indeed Mesa/st/va increments a counter for the
surface ID: mesa/util/u_handle_table.c::handle_table_add which
starts from 0 and incremented by 1 at each call.
So when creating above 32 surfaces it was a problem.

The following bug contains a test that reproduces the problem
by running a couple of vaapih264enc in the same process. The above
also explains why there was no pb when running them in separated
processes.

https://bugzilla.gnome.org/show_bug.cgi?id=785085


Apart from the type above, patch is Acked-by: Christian König 
.


Leo and Boyuan can you take a quick look as well? On first glance looks 
totally sane to me.


Christian.


---
  src/gallium/include/pipe/p_video_state.h   |  4 +++-
  src/gallium/state_trackers/va/context.c|  9 +++--
  src/gallium/state_trackers/va/picture.c| 11 ---
  src/gallium/state_trackers/va/va_private.h | 13 +
  4 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index 39b3905..53f9ab3 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -32,6 +32,7 @@
  #include "pipe/p_format.h"
  #include "pipe/p_state.h"
  #include "pipe/p_screen.h"
+#include "util/u_hash_table.h"
  #include "util/u_inlines.h"
  
  #ifdef __cplusplus

@@ -407,7 +408,8 @@ struct pipe_h264_enc_picture_desc
 bool not_referenced;
 bool is_idr;
 bool enable_vui;
-   unsigned int frame_idx[32];
+   struct util_hash_table *frame_idx;
+
  };
  
  struct pipe_h265_sps

diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index 186f5066..f2cb37a 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -280,8 +280,10 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID 
config_id, int picture_width,
  
 context->desc.base.profile = config->profile;

 context->desc.base.entry_point = config->entrypoint;
-   if (config->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
+   if (config->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
context->desc.h264enc.rate_ctrl.rate_ctrl_method = config->rc;
+  context->desc.h264enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+   }
  
 mtx_lock(>mutex);

 *context_id = handle_table_add(drv->htab, context);
@@ -308,7 +310,10 @@ vlVaDestroyContext(VADriverContextP ctx, VAContextID 
context_id)
 }
  
 if (context->decoder) {

-  if (context->desc.base.entry_point != PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+  if (context->desc.base.entry_point == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+ if (context->desc.h264enc.frame_idx)
+util_hash_table_destroy (context->desc.h264enc.frame_idx);
+  } else {
   if (u_reduce_video_profile(context->decoder->profile) ==
 PIPE_VIDEO_FORMAT_MPEG4_AVC) {
  FREE(context->desc.h264.pps->sps);
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 20fe750..338e090 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -427,7 +427,10 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
  PIPE_USAGE_STREAM, 
coded_buf->size);
 context->coded_buf = coded_buf;
  
-   context->desc.h264enc.frame_idx[h264->CurrPic.picture_id] = h264->frame_num;

+   util_hash_table_set(context->desc.h264enc.frame_idx,
+  UINT_TO_PTR(h264->CurrPic.picture_id),
+  UINT_TO_PTR(h264->frame_num));
+
 if (context->desc.h264enc.is_idr)
context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_IDR;
 else
@@ -455,11 +458,13 @@ handleVAEncSliceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlVaB
 for (int i = 0; i < 32; i++) {
if (h264->RefPicList0[i].picture_id != VA_INVALID_ID) {
   if (context->desc.h264enc.ref_idx_l0 == VA_INVALID_ID)
-context->desc.h264enc.ref_idx_l0 = 
context->desc.h264enc.frame_idx[h264->RefPicList0[i].picture_id];
+context->desc.h264enc.ref_idx_l0 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h264enc.frame_idx,
+  
UINT_TO_PTR(h264->RefPicList0[i].picture_id)));
}
if (h264->RefPicList1[i].picture_id != VA_INVALID_ID && 
h264->slice_type == 1) {
   if (context->desc.h264enc.ref_idx_l1 == VA_INVALID_ID)
-

Re: [Mesa-dev] [PATCH v2 1/2] st/dri: Check get-handle return value in queryImage

[Emil Velikov]

Hi Dan,

On 24 July 2017 at 16:46, Daniel Stone  wrote:
> In the DRIImage queryImage hook, check if resource_get_handle() failed
> and return FALSE if so.
>
Wanted to say huge thank you for sorting these out (sorry for being
slow to actually review it).

I think we'd want this patch in stable. Please "shout" if that's not the case.

Thanks
Emil
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Re: [Mesa-dev] [PATCH] st/mesa: create framebuffer iface hash table per st manager

[Charmaine Lee]

>From: James Legg 
>Sent: Tuesday, July 25, 2017 6:24 AM
>To: mesa-dev@lists.freedesktop.org; Charmaine Lee
>Subject: Re: [Mesa-dev] [PATCH] st/mesa: create framebuffer iface hash table 
>per st manager

>On Sun, 2017-07-23 at 16:37 -0700, Charmaine Lee wrote:
>> With this patch, framebuffer interface hash table is created
>> per state tracker manager.
>>
>> Fixes crash with steam.
>>
>> Bugzilla: 
>> https://urldefense.proofpoint.com/v2/url?u=https-3A__bugs.freedesktop.org_show-5Fbug.cgi-3Fid->3D101876=DwICaQ=uilaK90D4TOVoH58JNXRgQ=Ang1qmMo4GwCmRUnLE-f31kqPa6AOnoS->OAMUzQyM0M=2ysMQPCeR_vf9ch72ej4wehfJ99Mtt9hBTroMbybY_o=xmTbTiDE9mV_SwkzVM08KH23S6vuWlerjRkqriB3>QOg=
>> Fixes: 5124bf98239 ("st/mesa: add destroy_drawable interface")
>> Tested-by: Christoph Haag 

>> --- a/src/mesa/state_tracker/st_manager.c
>>
>> @@ -511,45 +515,63 @@ st_framebuffer_iface_equal(const void *a, const void 
>> *b)
>>
>>
>>  static boolean
>> -st_framebuffer_iface_lookup(const struct st_framebuffer_iface *stfbi)
>> +st_framebuffer_iface_lookup(struct st_manager *smapi,
>> +const struct st_framebuffer_iface *stfbi)
>>  {
>> +   struct st_manager_private *smPriv =
>> +  (struct st_manager_private *)smapi->st_manager_private;
>> struct hash_entry *entry;
>>
>> -   mtx_lock(_mutex);
>> -   entry = _mesa_hash_table_search(st_fbi_ht, stfbi);
>> -   mtx_unlock(_mutex);
>> +   assert(smPriv);
>> +   assert(smPriv->stfbi_ht);
>> +
>> +   mtx_lock(>st_mutex);
>> +   entry = _mesa_hash_table_search(smPriv->stfbi_ht, stfbi);
>> +   mtx_unlock(>st_mutex);
>>
>> return entry != NULL;
>>  }
>>
>>
>>  static boolean
>> -st_framebuffer_iface_insert(struct st_framebuffer_iface *stfbi)
>> +st_framebuffer_iface_insert(struct st_manager *smapi,
>> +struct st_framebuffer_iface *stfbi)
>>  {
>> +   struct st_manager_private *smPriv =
>> +  (struct st_manager_private *)smapi->st_manager_private;
>> struct hash_entry *entry;
>>
>> -   mtx_lock(_mutex);
>> -   entry = _mesa_hash_table_insert(st_fbi_ht, stfbi, stfbi);
>> -   mtx_unlock(_mutex);
>> +   assert(smPriv);
>> +   assert(smPriv->stfbi_ht);
>> +
>> +   mtx_lock(>st_mutex);
>> +   entry = _mesa_hash_table_insert(smPriv->stfbi_ht, stfbi, stfbi);
>> +   mtx_unlock(>st_mutex);
>>
>> return entry != NULL;
>>  }
>>
>>
>>  static void
>> -st_framebuffer_iface_remove(struct st_framebuffer_iface *stfbi)
>> +st_framebuffer_iface_remove(struct st_manager *smapi,
>> +struct st_framebuffer_iface *stfbi)
>>  {
>> +   struct st_manager_private *smPriv =
>> +  (struct st_manager_private *)smapi->st_manager_private;
>> struct hash_entry *entry;
>>
>> -   mtx_lock(_mutex);
>> -   entry = _mesa_hash_table_search(st_fbi_ht, stfbi);
>> +   if (!smPriv || !smPriv->stfbi_ht);
>> +  return;

>The semicolon after the if causes the return to execute
>unconditionally.

Ah, good catch.  Thanks.  Will fix it.

-Charmaine
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Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence for Android OS v4.2

[Marathe, Yogesh]

> -Original Message-
> From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
> Sent: Tuesday, July 25, 2017 11:22 PM
> To: Marathe, Yogesh 
> Cc: Wu, Zhongmin ; ML mesa-dev  d...@lists.freedesktop.org>; Kondapally, Kalyan
> ; Antognolli, Rafael
> ; Gao, Shuo ; Tomasz Figa
> ; Chris Wilson ; Eric
> Engestrom ; Rob Herring ; Daniel
> Stone ; Varad Gautam
> ; Liu, Zhiquan ; Frank
> Binns ; Brendan King ;
> Martin Peres 
> Subject: Re: [PATCH 2/2] i965: Queue the buffer with a sync fence for Android
> OS v4.2
> 
> On 25 July 2017 at 15:30, Marathe, Yogesh 
> wrote:
> > Emil,
> >
> >> -Original Message-
> >> From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
> >> Sent: Tuesday, July 25, 2017 7:46 PM
> >> To: Wu, Zhongmin 
> >> Cc: ML mesa-dev ; Kondapally, Kalyan
> >> ; Marathe, Yogesh
> >> ; Antognolli, Rafael
> >> ; Gao, Shuo ; Tomasz
> >> Figa ; Chris Wilson ;
> >> Eric Engestrom ; Rob Herring ;
> >> Daniel Stone ; Varad Gautam
> >> ; Liu, Zhiquan ;
> >> Frank Binns ; Brendan King
> >> ; Martin Peres
> >> 
> >> Subject: Re: [PATCH 2/2] i965: Queue the buffer with a sync fence for
> >> Android OS v4.2
> >>
> >> Hi Zhongmin,
> >>
> >> Thanks you for the update. There's a couple of important comments -
> >> dri2_make_current + droid_window_enqueue_buffer.
> >> The rest is just nitpiks.
> >>
> >> Tomasz, hats down for the immense help and guidance.
> >>
> >> On the potential performance hit (due to the extra fence), I think we
> >> could do some tests before adding extra infra.
> >> No obvious benchmarks come to mind - any suggestions?
> >>
> >
> > Sorry to jump in, flatland is the one native application on android
> > that tests this explicitly. It gives time required to render one frame
> > of particular resolution without other services running. It’s a native
> > app that comes with aosp. And we found this issue just because of that.
> >
> > App info -
> > https://android.googlesource.com/platform/frameworks/native/+/master/c
> > mds/flatland/README.txt Bug -
> > https://bugs.freedesktop.org/show_bug.cgi?id=101655
> >
> > I already tested this patch set with android and I can see scores not being 
> > that
> great.
> > May be this is the one we can use to profile this or I can continue to
> > profile based on guidance here.
> >
> I meant a completely different thing:
> 
> Don't bother with premature optimisations - see if/how much overhead of the
> patch itself adds (ideally on most platforms).
> Aka - test before/after. Which in the case of flatland is not possible, if I
> understood you correctly.

Yes, it won't be functional without patch.

> 
> About the performance numbers in question - I hope you've looked at my
> comment in 1/2.

Yes. I saw that.

> 
> -Emil
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[Mesa-dev] [PATCH 2/3] i965: Fix = vs == in MCS aux usage assert.

[Kenneth Graunke]

Caught by Coverity (CID 1415680).

Cc: "17.2" 
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index 36f7ed2a39d..a0f37780ef5 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -1103,7 +1103,7 @@ brw_blorp_mcs_partial_resolve(struct brw_context *brw,
DBG("%s to mt %p layers %u-%u\n", __FUNCTION__, mt,
start_layer, start_layer + num_layers - 1);
 
-   assert(mt->aux_usage = ISL_AUX_USAGE_MCS);
+   assert(mt->aux_usage == ISL_AUX_USAGE_MCS);
 
const mesa_format format = _mesa_get_srgb_format_linear(mt->format);
enum isl_format isl_format = brw_blorp_to_isl_format(brw, format, true);
-- 
2.13.3

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[Mesa-dev] [PATCH 1/3] i965: Fix offset addition in get_isl_surf.

[Kenneth Graunke]

Increase the value, not the pointer to the stack variable.

Caught by Coverity (CID 1415574).  Not shipped in a real release.

Cc: "17.2" 
---
 src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c 
b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 250806d28e4..a0ca6ddf985 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -101,9 +101,9 @@ get_isl_surf(struct brw_context *brw, struct 
intel_mipmap_tree *mt,
assert(view->levels == 1 && view->array_len == 1);
assert(*tile_x == 0 && *tile_y == 0);
 
-   offset += intel_miptree_get_tile_offsets(mt, view->base_level,
-view->base_array_layer,
-tile_x, tile_y);
+   *offset += intel_miptree_get_tile_offsets(mt, view->base_level,
+ view->base_array_layer,
+ tile_x, tile_y);
 
/* Minify the logical dimensions of the texture. */
const unsigned l = view->base_level - mt->first_level;
-- 
2.13.3

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[Mesa-dev] [PATCH 3/3] i965: Shut up Coverity warning about HiZ buffers.

[Kenneth Graunke]

Here the AUX_USAGE_* mode indicates that we have HiZ, so we will have
a HiZ buffer.  But Coverity doesn't know that, so it thinks it might
be NULL because we checked hiz_buf != NULL earlier.
---
 src/mesa/drivers/dri/i965/brw_blorp.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c 
b/src/mesa/drivers/dri/i965/brw_blorp.c
index a0f37780ef5..b2987ca4faf 100644
--- a/src/mesa/drivers/dri/i965/brw_blorp.c
+++ b/src/mesa/drivers/dri/i965/brw_blorp.c
@@ -184,6 +184,7 @@ blorp_surf_for_miptree(struct brw_context *brw,
  surf->aux_addr.buffer = mt->mcs_buf->bo;
  surf->aux_addr.offset = mt->mcs_buf->offset;
   } else {
+ assert(mt->hiz_buf);
  assert(surf->aux_usage == ISL_AUX_USAGE_HIZ);
 
  surf->aux_addr.buffer = mt->hiz_buf->bo;
-- 
2.13.3

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Re: [Mesa-dev] [PATCH 11/27] radeonsi: add basic memory object support v3

[Marek Olšák]

On Tue, Jul 18, 2017 at 5:06 AM, Andres Rodriguez  wrote:
> From: Dave Airlie 
>
> v2: also consider gfx9 metadata
> v3: ref/unref memobj->buf
>
> Signed-off-by: Andres Rodriguez 
> ---
>  src/gallium/drivers/radeon/r600_pipe_common.h |   7 ++
>  src/gallium/drivers/radeon/r600_texture.c | 111 
> ++
>  2 files changed, 118 insertions(+)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 5c761f3..c619b60 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -377,6 +377,13 @@ union r600_mmio_counters {
> unsigned array[0];
>  };
>
> +struct r600_memory_object {
> +   struct pipe_memory_object   b;
> +   struct pb_buffer*buf;
> +   uint32_tstride;
> +   uint32_toffset;
> +};
> +
>  struct r600_common_screen {
> struct pipe_screen  b;
> struct radeon_winsys*ws;
> diff --git a/src/gallium/drivers/radeon/r600_texture.c 
> b/src/gallium/drivers/radeon/r600_texture.c
> index c633141..667ed08 100644
> --- a/src/gallium/drivers/radeon/r600_texture.c
> +++ b/src/gallium/drivers/radeon/r600_texture.c
> @@ -2831,10 +2831,121 @@ void evergreen_do_fast_color_clear(struct 
> r600_common_context *rctx,
> }
>  }
>
> +static struct pipe_memory_object *
> +r600_memobj_from_handle(struct pipe_screen *screen,
> +   struct winsys_handle *whandle,
> +   bool dedicated)
> +{
> +   struct r600_common_screen *rscreen = (struct 
> r600_common_screen*)screen;
> +   struct r600_memory_object *memobj = CALLOC_STRUCT(r600_memory_object);
> +   struct pb_buffer *buf = NULL;
> +   uint32_t stride, offset;
> +
> +   if (!memobj)
> +   return NULL;
> +
> +   buf = rscreen->ws->buffer_from_handle(rscreen->ws, whandle,
> + , );
> +   if (!buf) {
> +   free(memobj);
> +   return NULL;
> +   }
> +
> +   memobj->b.dedicated = dedicated;
> +   memobj->buf = buf;
> +   memobj->stride = stride;
> +   memobj->offset = offset;
> +
> +   return (struct pipe_memory_object *)memobj;
> +
> +}
> +
> +static void
> +r600_memobj_destroy(struct pipe_screen *screen,
> +   struct pipe_memory_object *_memobj)
> +{
> +   struct r600_memory_object *memobj = (struct r600_memory_object 
> *)_memobj;
> +
> +   pb_reference(>buf, NULL);
> +   free(memobj);
> +}
> +
> +static struct pipe_resource *
> +r600_texture_from_memobj(struct pipe_screen *screen,
> +const struct pipe_resource *templ,
> +struct pipe_memory_object *_memobj,
> +uint64_t offset)
> +{
> +   int r;
> +   struct r600_common_screen *rscreen = (struct 
> r600_common_screen*)screen;
> +   struct r600_memory_object *memobj = (struct r600_memory_object 
> *)_memobj;
> +   struct r600_texture *rtex;
> +   struct radeon_surf surface;
> +   struct radeon_bo_metadata metadata = {};
> +   enum radeon_surf_mode array_mode;
> +   bool is_scanout;
> +   struct pb_buffer *buf = NULL;
> +
> +   if (memobj->b.dedicated) {
> +   rscreen->ws->buffer_get_metadata(memobj->buf, );
> +   r600_surface_import_metadata(rscreen, , ,
> +_mode, _scanout);
> +   } else {
> +   /**
> +* The bo metadata is unset for un-dedicated images. So we 
> fall
> +* back to linear. See answer to question 5 of the
> +* VK_KHX_external_memory spec for some details.
> +*
> +* It is possible that this case isn't going to work if the
> +* surface pitch isn't correctly aligned by default.
> +*
> +* In order to support it correctly we require multi-image
> +* metadata to be syncrhonized between radv and radeonsi. The
> +* semantics of associating multiple image metadata to a 
> memory
> +* object on the vulkan export side are not concretely defined
> +* either.
> +*
> +* All the use cases we are aware of at the moment for memory
> +* objects use dedicated allocations. So lets keep the initial
> +* implementation simple.
> +*
> +* A possible alternative is to attempt to reconstruct the
> +* tiling information when the TexParameter TEXTURE_TILING_EXT
> +* is set.
> +*/
> +   array_mode = RADEON_SURF_MODE_LINEAR_ALIGNED;
> +   is_scanout = false;
> +
> +   

Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence for Android OS v4.2

[Emil Velikov]

On 25 July 2017 at 15:30, Marathe, Yogesh  wrote:
> Emil,
>
>> -Original Message-
>> From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
>> Sent: Tuesday, July 25, 2017 7:46 PM
>> To: Wu, Zhongmin 
>> Cc: ML mesa-dev ; Kondapally, Kalyan
>> ; Marathe, Yogesh
>> ; Antognolli, Rafael
>> ; Gao, Shuo ; Tomasz Figa
>> ; Chris Wilson ; Eric
>> Engestrom ; Rob Herring ; Daniel
>> Stone ; Varad Gautam
>> ; Liu, Zhiquan ; Frank
>> Binns ; Brendan King ;
>> Martin Peres 
>> Subject: Re: [PATCH 2/2] i965: Queue the buffer with a sync fence for Android
>> OS v4.2
>>
>> Hi Zhongmin,
>>
>> Thanks you for the update. There's a couple of important comments -
>> dri2_make_current + droid_window_enqueue_buffer.
>> The rest is just nitpiks.
>>
>> Tomasz, hats down for the immense help and guidance.
>>
>> On the potential performance hit (due to the extra fence), I think we could 
>> do
>> some tests before adding extra infra.
>> No obvious benchmarks come to mind - any suggestions?
>>
>
> Sorry to jump in, flatland is the one native application on android that 
> tests this
> explicitly. It gives time required to render one frame of particular 
> resolution without
> other services running. It’s a native app that comes with aosp. And we found 
> this
> issue just because of that.
>
> App info - 
> https://android.googlesource.com/platform/frameworks/native/+/master/cmds/flatland/README.txt
> Bug - https://bugs.freedesktop.org/show_bug.cgi?id=101655
>
> I already tested this patch set with android and I can see scores not being 
> that great.
> May be this is the one we can use to profile this or I can continue to 
> profile based on
> guidance here.
>
I meant a completely different thing:

Don't bother with premature optimisations - see if/how much overhead
of the patch itself adds (ideally on most platforms).
Aka - test before/after. Which in the case of flatland is not
possible, if I understood you correctly.

About the performance numbers in question - I hope you've looked at my
comment in 1/2.

-Emil
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Re: [Mesa-dev] [PATCH v2 2/2] st/dri2: Return invalid modifier when no driver support

[Daniel Stone]

On 25 July 2017 at 17:43, Marek Olšák  wrote:
> For the series:
>
> Reviewed-by: Marek Olšák 

Thanks Marek! I've fixed the idiotic dropping of the 'return GL_FALSE'
for the modifiers path in 1/2 (bad rebase) and pushed now.

Cheers,
Daniel
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Re: [Mesa-dev] [PATCH] i965: perf: flush batchbuffers at the beginning of queries

[Kenneth Graunke]

On Tuesday, July 25, 2017 9:49:22 AM PDT Lionel Landwerlin wrote:
> As Chris commented, it makes more sense to have batch buffer flushes
> before the query. Usually applications like frame_retrace do a series
> of queries and in that case, with flushes at the end of the queries,
> we might still have the first query contained in 2 different batchs.
> More generally it would be quite usual to have the query contained in
> 2 batch buffers because we never now what's the fill rate of the
> current batch buffer.
> 
> If we move the flushing at the beginning of the queries, it's pretty
> much guaranteed that queries will be contained in a single batch
> buffer (unless the amount of commands is huge, but then it's only fair
> to include reloading request times in the measurements).
> 
> Fixes: adafe4b733c02 ("i965: perf: minimize the chances to spread queries 
> across batchbuffers")
> Reported-by: Chris Wilson 
> Signed-off-by: Lionel Landwerlin 
> Cc: 17.1 

17.2 branched, so:

Cc: "17.1 17.2" 
Reviewed-by: Kenneth Graunke 

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Re: [Mesa-dev] [PATCH 4/6] st/dri: use correct __DRI2_CONFIG_QUERY extension

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Fri, Jul 7, 2017 at 8:47 PM, Emil Velikov  wrote:
> From: Emil Velikov 
>
> If device supports robustness (AKA PIPE_CAP_DEVICE_RESET_STATUS_QUERY)
> then we're using dri_robust_screen_extensions.
> Hence for such cases the DRI loader was not able to query the driver
> options.
>
> This went unnoticed since only r600/radeonsi drivers have the feature.
> At the same time neither of them has a local option that the loader
> cares about.
>
> Fixes: ff2978b4494 ("st/dri: Allow dri users to query also driver
> options")
> Cc: Thomas Hellstrom 
> Cc: Marek Olšák 
> Signed-off-by: Emil Velikov 
> ---
> Perhaps we might want to use it in swrast? If so we'll need to move the
> extension to dri_extensions.[ch] first.
> ---
>  src/gallium/state_trackers/dri/dri2.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/src/gallium/state_trackers/dri/dri2.c 
> b/src/gallium/state_trackers/dri/dri2.c
> index 60ec38d8e44..6a977636ea8 100644
> --- a/src/gallium/state_trackers/dri/dri2.c
> +++ b/src/gallium/state_trackers/dri/dri2.c
> @@ -1995,7 +1995,7 @@ static const __DRIextension 
> *dri_robust_screen_extensions[] = {
> ,
> ,
> ,
> -   ,
> +   ,
> ,
> ,
> ,
> --
> 2.13.0
>
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Re: [Mesa-dev] [PATCH v2] st/dri: add 32-bit RGBX/RGBA formats

[Rob Herring]

On Tue, Jul 25, 2017 at 10:15 AM, Emil Velikov  wrote:
> On 25 July 2017 at 03:46, Chih-Wei Huang  wrote:
>> On Tue 11 Jul 2017, Rob Herring wrote:
 From: Marek Olšák 

 Add support for 32-bit RGBX/RGBA formats which are required for Android.

 The original patch (commit ccdcf91104a5) was reverted (commit
 c0c6ca40a25e) in mesa as it broke GLX resulting in swapped colors. Based
 on further investigation by Chad Versace, moving the RGBX/RGBA configs
 to the end is enough to prevent breaking GLX.

 The handling of RGBA/RGBX in dri_fill_st_visual is a fix from Marek
 Olšák.

 Cc: Eric Anholt 
 Cc: Chad Versace 
 Cc: Mauro Rossi 
 Reviewed-by: Marek Olšák 
 Signed-off-by: Rob Herring 
 ---
 v2:
 - Incorporated dri_fill_st_visual RGBA/X handling from Marek
 - Handle RGBA/X in dri2_drawable_get_buffers for completeness
>>
>> Hi Rob,
>> I'm testing this patch with your gbm_gralloc and mesa 17.1.5.
>> Before applying this patch, the SurfaceFlinger sees
>> the alpha=8 in RenderEngine::chooseEglConfig()
>>
> May want to check for patches in the Android EGL (meta) library.
> I think, in does/did have a handful of workarounds.
>
> Is the Android-x86 one in sync with the one RobH uses?

I double checked and I get 8-8-8-8. I'm have HWC2 enabled and
SurfaceFlinger is unpatched master branch.

Rob
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Re: [Mesa-dev] [PATCH] r600: Add support for B5G5R5A1.

[Marek Olšák]

Pushed, thanks!

Marek

On Mon, Jul 17, 2017 at 9:34 AM,   wrote:
> From: Michal Srb 
>
> Fixes rendercheck errors when using glamor acceleration in X server.
> ---
>
> Fixes rendercheck errors on tests with r5g5b5 and b5g5r5. For example
> `rendercheck -t blend -f r5g5b5,a8r8g8b8`.
>
> I am not completely sure if it is correct. I wasn't able to run all piglit
> tests because most glsl tests were crashing my X server, but I ran the 'gpu'
> set and there were no regression.
>
>  src/gallium/drivers/r600/r600_asm.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/src/gallium/drivers/r600/r600_asm.c 
> b/src/gallium/drivers/r600/r600_asm.c
> index 9e00528c5c..be2a086594 100644
> --- a/src/gallium/drivers/r600/r600_asm.c
> +++ b/src/gallium/drivers/r600/r600_asm.c
> @@ -2380,6 +2380,12 @@ void r600_vertex_data_type(enum pipe_format pformat,
> return;
> }
>
> +   if (pformat == PIPE_FORMAT_B5G5R5A1_UNORM) {
> +   *format = FMT_1_5_5_5;
> +   *endian = r600_endian_swap(16);
> +   return;
> +   }
> +
> desc = util_format_description(pformat);
> if (desc->layout != UTIL_FORMAT_LAYOUT_PLAIN) {
> goto out_unknown;
> --
> 2.12.3
>
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Re: [Mesa-dev] [PATCH] amdgpu/addrlib: use initialization list in addrobject

[Jeremy Newton]

Dully noted, thanks for the heads up.

On July 25, 2017 12:50:22 PM EDT, "Marek Olšák"  wrote:
>Hi Jeremy,
>
>Note that addrlib is imported from our internal repository. Any
>changes to addrlib in Mesa may make later updates from the internal
>repository more difficult. It would be preferable to apply changes to
>the internal addrlib first and Mesa would get them on the next addrlib
>update.
>
>I personally don't bother cleaning up addrlib in Mesa except maybe
>fixing warnings.
>
>Marek
>
>On Mon, Jul 24, 2017 at 7:17 PM, Jeremy Newton 
>wrote:
>> Fair enough.
>>
>> Although from my tests with x86-64 GCC 6.3 (Fedora 25), it did
>produce a
>> slightly smaller binary with this patch.
>>
>> With that said, I only used whatever the default optimization flags
>are, and
>> I didn't do a diff on a disasm to see what actually changed.
>>
>> On Mon, Jul 24, 2017 at 1:03 PM, Nicolai Hähnle 
>wrote:
>>>
>>> On 23.07.2017 18:24, Mystro256 wrote:
>>> > ---
>>> >   src/amd/addrlib/core/addrobject.cpp | 4 ++--
>>> >   1 file changed, 2 insertions(+), 2 deletions(-)
>>> >
>>> > diff --git a/src/amd/addrlib/core/addrobject.cpp
>>> > b/src/amd/addrlib/core/addrobject.cpp
>>> > index dcdb1bf..ee2d9a9 100644
>>> > --- a/src/amd/addrlib/core/addrobject.cpp
>>> > +++ b/src/amd/addrlib/core/addrobject.cpp
>>> > @@ -61,9 +61,9 @@ Object::Object()
>>> >   *   Constructor for the Object class.
>>> >
>>> >
>
>>> >   */
>>> > -Object::Object(const Client* pClient)
>>> > +Object::Object(const Client* pClient):
>>> > +m_client (*pClient)
>>> >   {
>>> > -m_client = *pClient;
>>> >   }
>>>
>>> Thanks, but this is really a matter of taste and coding style. It
>should
>>> make no difference for the generated code, and I believe addrlib
>>> generally prefers not to use the initializer list, so NAK on this
>patch.
>>>
>>> Cheers,
>>> Nicolai
>>>
>>>
>>> >
>>> >   /**
>>> >
>>>
>>>
>>> --
>>> Lerne, wie die Welt wirklich ist,
>>> Aber vergiss niemals, wie sie sein sollte.
>>
>>
>>
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Re: [Mesa-dev] [PATCH 3/3] mesa/st: fix unused variable warnings

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Thu, Jul 20, 2017 at 2:07 AM, Timothy Arceri  wrote:
> ---
>  src/mesa/state_tracker/st_cb_bitmap.c | 5 +++--
>  src/mesa/state_tracker/st_cb_drawpixels.c | 9 -
>  src/mesa/state_tracker/st_cb_texture.c| 2 +-
>  src/mesa/state_tracker/st_format.c| 5 +++--
>  4 files changed, 11 insertions(+), 10 deletions(-)
>
> diff --git a/src/mesa/state_tracker/st_cb_bitmap.c 
> b/src/mesa/state_tracker/st_cb_bitmap.c
> index 7ba6d82..a5c7ed0 100644
> --- a/src/mesa/state_tracker/st_cb_bitmap.c
> +++ b/src/mesa/state_tracker/st_cb_bitmap.c
> @@ -301,8 +301,9 @@ draw_bitmap_quad(struct gl_context *ctx, GLint x, GLint 
> y, GLfloat z,
>/* XXX if the bitmap is larger than the max texture size, break
> * it up into chunks.
> */
> -  GLuint maxSize = 1 << (pipe->screen->get_param(pipe->screen,
> -PIPE_CAP_MAX_TEXTURE_2D_LEVELS) - 1);
> +  GLuint MAYBE_UNUSED maxSize =
> + 1 << (pipe->screen->get_param(pipe->screen,
> +   PIPE_CAP_MAX_TEXTURE_2D_LEVELS) - 1);
>assert(width <= (GLsizei) maxSize);
>assert(height <= (GLsizei) maxSize);
> }
> diff --git a/src/mesa/state_tracker/st_cb_drawpixels.c 
> b/src/mesa/state_tracker/st_cb_drawpixels.c
> index 384f965..1d88976 100644
> --- a/src/mesa/state_tracker/st_cb_drawpixels.c
> +++ b/src/mesa/state_tracker/st_cb_drawpixels.c
> @@ -464,7 +464,6 @@ make_texture(struct st_context *st,
>
> {
>struct pipe_transfer *transfer;
> -  GLboolean success;
>GLubyte *dest;
>const GLbitfield imageTransferStateSave = ctx->_ImageTransferState;
>
> @@ -497,9 +496,9 @@ make_texture(struct st_context *st,
>format, type, /* src format/type */
>pixels,   /* data source */
>unpack);
> - success = GL_TRUE;
>}
>else {
> + bool MAYBE_UNUSED success;
>   success = _mesa_texstore(ctx, 2,   /* dims */
>baseInternalFormat, /* baseInternalFormat 
> */
>mformat,  /* mesa_format */
> @@ -509,13 +508,13 @@ make_texture(struct st_context *st,
>format, type, /* src format/type */
>pixels,   /* data source */
>unpack);
> +
> + assert(success);
>}
>
>/* unmap */
>pipe_transfer_unmap(pipe, transfer);
>
> -  assert(success);
> -
>/* restore */
>ctx->_ImageTransferState = imageTransferStateSave;
> }
> @@ -570,7 +569,7 @@ draw_textured_quad(struct gl_context *ctx, GLint x, GLint 
> y, GLfloat z,
> const unsigned fb_width = _mesa_geometric_width(ctx->DrawBuffer);
> const unsigned fb_height = _mesa_geometric_height(ctx->DrawBuffer);
> GLfloat x0, y0, x1, y1;
> -   GLsizei maxSize;
> +   GLsizei MAYBE_UNUSED maxSize;
> boolean normalized = sv[0]->texture->target == PIPE_TEXTURE_2D;
> unsigned cso_state_mask;
>
> diff --git a/src/mesa/state_tracker/st_cb_texture.c 
> b/src/mesa/state_tracker/st_cb_texture.c
> index c6a5e63..b1abef3 100644
> --- a/src/mesa/state_tracker/st_cb_texture.c
> +++ b/src/mesa/state_tracker/st_cb_texture.c
> @@ -2396,7 +2396,7 @@ copy_image_data_to_texture(struct st_context *st,
>  {
> /* debug checks */
> {
> -  const struct gl_texture_image *dstImage =
> +  const struct gl_texture_image MAYBE_UNUSED *dstImage =
>   stObj->base.Image[stImage->base.Face][dstLevel];
>assert(dstImage);
>assert(dstImage->Width == stImage->base.Width);
> diff --git a/src/mesa/state_tracker/st_format.c 
> b/src/mesa/state_tracker/st_format.c
> index 64a3a81..348853a 100644
> --- a/src/mesa/state_tracker/st_format.c
> +++ b/src/mesa/state_tracker/st_format.c
> @@ -1028,7 +1028,7 @@ test_format_conversion(struct st_context *st)
>
>pf = st_mesa_format_to_pipe_format(st, i);
>if (pf != PIPE_FORMAT_NONE) {
> - mesa_format mf = st_pipe_format_to_mesa_format(pf);
> + mesa_format MAYBE_UNUSED mf = st_pipe_format_to_mesa_format(pf);
>   assert(mf == i);
>}
> }
> @@ -1044,7 +1044,8 @@ test_format_conversion(struct st_context *st)
>   continue;
>
>if (mf != MESA_FORMAT_NONE) {
> - enum pipe_format pf = st_mesa_format_to_pipe_format(st, mf);
> + enum pipe_format MAYBE_UNUSED pf =
> +st_mesa_format_to_pipe_format(st, mf);
>   assert(pf == i);
>}
> }
> --
> 2.9.4
>
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Re: [Mesa-dev] [PATCH 1/4] ac/gpu: add code to detect if kernel supports sync objects.

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Thu, Jul 20, 2017 at 5:38 AM, Dave Airlie  wrote:
> From: Dave Airlie 
>
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/common/ac_gpu_info.c | 9 +
>  src/amd/common/ac_gpu_info.h | 1 +
>  2 files changed, 10 insertions(+)
>
> diff --git a/src/amd/common/ac_gpu_info.c b/src/amd/common/ac_gpu_info.c
> index ced7183..929dfd2 100644
> --- a/src/amd/common/ac_gpu_info.c
> +++ b/src/amd/common/ac_gpu_info.c
> @@ -84,6 +84,14 @@ static unsigned cik_get_num_tile_pipes(struct 
> amdgpu_gpu_info *info)
> }
>  }
>
> +static bool has_syncobj(int fd)
> +{
> +   uint64_t value;
> +   if (drmGetCap(fd, DRM_CAP_SYNCOBJ, ))
> +   return false;
> +   return value ? true : false;
> +}
> +
>  bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
>struct radeon_info *info,
>struct amdgpu_gpu_info *amdinfo)
> @@ -258,6 +266,7 @@ bool ac_query_gpu_info(int fd, amdgpu_device_handle dev,
> info->vce_fw_version =
> vce.available_rings ? vce_version : 0;
> info->has_userptr = true;
> +   info->has_syncobj = has_syncobj(fd);
> info->num_render_backends = amdinfo->rb_pipes;
> info->clock_crystal_freq = amdinfo->gpu_counter_freq;
> if (!info->clock_crystal_freq) {
> diff --git a/src/amd/common/ac_gpu_info.h b/src/amd/common/ac_gpu_info.h
> index 72a8506..20907c2 100644
> --- a/src/amd/common/ac_gpu_info.h
> +++ b/src/amd/common/ac_gpu_info.h
> @@ -76,6 +76,7 @@ struct radeon_info {
> uint32_tdrm_minor;
> uint32_tdrm_patchlevel;
> boolhas_userptr;
> +   boolhas_syncobj;
>
> /* Shader cores. */
> uint32_tr600_max_quad_pipes; /* wave size / 16 */
> --
> 2.9.4
>
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Re: [Mesa-dev] [PATCH] st/mesa: also clamp and quantize per-unit lod bias

[Samuel Pitoiset]

This should probably go to stable too.

Reviewed-by: Samuel Pitoiset 

On 07/25/2017 05:36 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/mesa/state_tracker/st_atom_sampler.c | 7 ---
  src/mesa/state_tracker/st_cb_texture.c   | 2 +-
  src/mesa/state_tracker/st_texture.h  | 1 +
  3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_sampler.c 
b/src/mesa/state_tracker/st_atom_sampler.c
index 208b6f7..d9e8de3 100644
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -98,35 +98,36 @@ gl_filter_to_img_filter(GLenum filter)
  }
  
  
  /**

   * Convert a gl_sampler_object to a pipe_sampler_state object.
   */
  void
  st_convert_sampler(const struct st_context *st,
 const struct gl_texture_object *texobj,
 const struct gl_sampler_object *msamp,
+   float tex_unit_lod_bias,
 struct pipe_sampler_state *sampler)
  {
 memset(sampler, 0, sizeof(*sampler));
 sampler->wrap_s = gl_wrap_xlate(msamp->WrapS);
 sampler->wrap_t = gl_wrap_xlate(msamp->WrapT);
 sampler->wrap_r = gl_wrap_xlate(msamp->WrapR);
  
 sampler->min_img_filter = gl_filter_to_img_filter(msamp->MinFilter);

 sampler->min_mip_filter = gl_filter_to_mip_filter(msamp->MinFilter);
 sampler->mag_img_filter = gl_filter_to_img_filter(msamp->MagFilter);
  
 if (texobj->Target != GL_TEXTURE_RECTANGLE_ARB)

sampler->normalized_coords = 1;
  
-   sampler->lod_bias = msamp->LodBias;

+   sampler->lod_bias = msamp->LodBias + tex_unit_lod_bias;
 /* Reduce the number of states by allowing only the values that AMD GCN
  * can represent. Apps use lod_bias for smooth transitions to bigger mipmap
  * levels.
  */
 sampler->lod_bias = CLAMP(sampler->lod_bias, -16, 16);
 sampler->lod_bias = floorf(sampler->lod_bias * 256) / 256;
  
 sampler->min_lod = MAX2(msamp->MinLod, 0.0f);

 sampler->max_lod = msamp->MaxLod;
 if (sampler->max_lod < sampler->min_lod) {
@@ -234,23 +235,23 @@ st_convert_sampler_from_unit(const struct st_context *st,
 const struct gl_texture_object *texobj;
 struct gl_context *ctx = st->ctx;
 const struct gl_sampler_object *msamp;
  
 texobj = ctx->Texture.Unit[texUnit]._Current;

 assert(texobj);
 assert(texobj->Target != GL_TEXTURE_BUFFER);
  
 msamp = _mesa_get_samplerobj(ctx, texUnit);
  
-   st_convert_sampler(st, texobj, msamp, sampler);

+   st_convert_sampler(st, texobj, msamp, ctx->Texture.Unit[texUnit].LodBias,
+  sampler);
  
-   sampler->lod_bias += ctx->Texture.Unit[texUnit].LodBias;

 sampler->seamless_cube_map |= ctx->Texture.CubeMapSeamless;
  }
  
  
  /**

   * Update the gallium driver's sampler state for fragment, vertex or
   * geometry shader stage.
   */
  static void
  update_shader_samplers(struct st_context *st,
diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index f66e1bd..eba9c30 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2965,21 +2965,21 @@ st_NewTextureHandle(struct gl_context *ctx, struct 
gl_texture_object *texObj,
 struct st_context *st = st_context(ctx);
 struct st_texture_object *stObj = st_texture_object(texObj);
 struct pipe_context *pipe = st->pipe;
 struct pipe_sampler_view *view;
 struct pipe_sampler_state sampler = {0};
  
 if (texObj->Target != GL_TEXTURE_BUFFER) {

if (!st_finalize_texture(ctx, pipe, texObj, 0))
   return 0;
  
-  st_convert_sampler(st, texObj, sampObj, );

+  st_convert_sampler(st, texObj, sampObj, 0, );
view = st_get_texture_sampler_view_from_stobj(st, stObj, sampObj, 0);
 } else {
view = st_get_buffer_sampler_view_from_stobj(st, stObj);
 }
  
 return pipe->create_texture_handle(pipe, view, );

  }
  
  
  static void

diff --git a/src/mesa/state_tracker/st_texture.h 
b/src/mesa/state_tracker/st_texture.h
index a6f6ee8..8448f4c 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tracker/st_texture.h
@@ -274,20 +274,21 @@ st_convert_image(const struct st_context *st, const 
struct gl_image_unit *u,
  
  void

  st_convert_image_from_unit(const struct st_context *st,
 struct pipe_image_view *img,
 GLuint imgUnit);
  
  void

  st_convert_sampler(const struct st_context *st,
 const struct gl_texture_object *texobj,
 const struct gl_sampler_object *msamp,
+   float tex_unit_lod_bias,
 struct pipe_sampler_state *sampler);
  
  void

  st_convert_sampler_from_unit(const struct st_context *st,
   struct pipe_sampler_state *sampler,
   GLuint texUnit);
  
  void

  

Re: [Mesa-dev] [PATCH] amdgpu/addrlib: use initialization list in addrobject

[Marek Olšák]

Hi Jeremy,

Note that addrlib is imported from our internal repository. Any
changes to addrlib in Mesa may make later updates from the internal
repository more difficult. It would be preferable to apply changes to
the internal addrlib first and Mesa would get them on the next addrlib
update.

I personally don't bother cleaning up addrlib in Mesa except maybe
fixing warnings.

Marek

On Mon, Jul 24, 2017 at 7:17 PM, Jeremy Newton  wrote:
> Fair enough.
>
> Although from my tests with x86-64 GCC 6.3 (Fedora 25), it did produce a
> slightly smaller binary with this patch.
>
> With that said, I only used whatever the default optimization flags are, and
> I didn't do a diff on a disasm to see what actually changed.
>
> On Mon, Jul 24, 2017 at 1:03 PM, Nicolai Hähnle  wrote:
>>
>> On 23.07.2017 18:24, Mystro256 wrote:
>> > ---
>> >   src/amd/addrlib/core/addrobject.cpp | 4 ++--
>> >   1 file changed, 2 insertions(+), 2 deletions(-)
>> >
>> > diff --git a/src/amd/addrlib/core/addrobject.cpp
>> > b/src/amd/addrlib/core/addrobject.cpp
>> > index dcdb1bf..ee2d9a9 100644
>> > --- a/src/amd/addrlib/core/addrobject.cpp
>> > +++ b/src/amd/addrlib/core/addrobject.cpp
>> > @@ -61,9 +61,9 @@ Object::Object()
>> >   *   Constructor for the Object class.
>> >
>> > 
>> >   */
>> > -Object::Object(const Client* pClient)
>> > +Object::Object(const Client* pClient):
>> > +m_client (*pClient)
>> >   {
>> > -m_client = *pClient;
>> >   }
>>
>> Thanks, but this is really a matter of taste and coding style. It should
>> make no difference for the generated code, and I believe addrlib
>> generally prefers not to use the initializer list, so NAK on this patch.
>>
>> Cheers,
>> Nicolai
>>
>>
>> >
>> >   /**
>> >
>>
>>
>> --
>> Lerne, wie die Welt wirklich ist,
>> Aber vergiss niemals, wie sie sein sollte.
>
>
>
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[Mesa-dev] [PATCH] i965: perf: flush batchbuffers at the beginning of queries

[Lionel Landwerlin]

As Chris commented, it makes more sense to have batch buffer flushes
before the query. Usually applications like frame_retrace do a series
of queries and in that case, with flushes at the end of the queries,
we might still have the first query contained in 2 different batchs.
More generally it would be quite usual to have the query contained in
2 batch buffers because we never now what's the fill rate of the
current batch buffer.

If we move the flushing at the beginning of the queries, it's pretty
much guaranteed that queries will be contained in a single batch
buffer (unless the amount of commands is huge, but then it's only fair
to include reloading request times in the measurements).

Fixes: adafe4b733c02 ("i965: perf: minimize the chances to spread queries 
across batchbuffers")
Reported-by: Chris Wilson 
Signed-off-by: Lionel Landwerlin 
Cc: 17.1 
---
 src/mesa/drivers/dri/i965/brw_performance_query.c | 16 
 1 file changed, 8 insertions(+), 8 deletions(-)

diff --git a/src/mesa/drivers/dri/i965/brw_performance_query.c 
b/src/mesa/drivers/dri/i965/brw_performance_query.c
index d7902de836c..d8680b48793 100644
--- a/src/mesa/drivers/dri/i965/brw_performance_query.c
+++ b/src/mesa/drivers/dri/i965/brw_performance_query.c
@@ -1212,6 +1212,14 @@ brw_begin_perf_query(struct gl_context *ctx,
   obj->oa.begin_report_id = brw->perfquery.next_query_start_report_id;
   brw->perfquery.next_query_start_report_id += 2;
 
+  /* We flush the batchbuffer here to minimize the chances that MI_RPC
+   * delimiting commands end up in different batchbuffers. If that's the
+   * case, the measurement will include the time it takes for the kernel
+   * scheduler to load a new request into the hardware. This is manifested 
in
+   * tools like frameretrace by spikes in the "GPU Core Clocks" counter.
+   */
+  intel_batchbuffer_flush(brw);
+
   /* Take a starting OA counter snapshot. */
   brw->vtbl.emit_mi_report_perf_count(brw, obj->oa.bo, 0,
   obj->oa.begin_report_id);
@@ -1298,14 +1306,6 @@ brw_end_perf_query(struct gl_context *ctx,
  obj->oa.begin_report_id + 1);
   }
 
-  /* We flush the batchbuffer here to minimize the chances that MI_RPC
-   * delimiting commands end up in different batchbuffers. If that's the
-   * case, the measurement will include the time it takes for the kernel
-   * scheduler to load a new request into the hardware. This is manifested
-   * in tools like frameretrace by spikes in the "GPU Core Clocks"
-   * counter.
-   */
-  intel_batchbuffer_flush(brw);
   --brw->perfquery.n_active_oa_queries;
 
   /* NB: even though the query has now ended, it can't be accumulated
-- 
2.13.3

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Re: [Mesa-dev] [PATCH] st/mesa: fix unconditional return in st_framebuffer_iface_remove

[Samuel Pitoiset]

Reviewed-by: Samuel Pitoiset 

On 07/25/2017 06:30 PM, Marek Olšák wrote:

From: Marek Olšák 

Cc: 17.2 
---
  src/mesa/state_tracker/st_manager.c | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index ede5439..78093ac 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -553,21 +553,21 @@ st_framebuffer_iface_insert(struct st_manager *smapi,
  
  
  static void

  st_framebuffer_iface_remove(struct st_manager *smapi,
  struct st_framebuffer_iface *stfbi)
  {
 struct st_manager_private *smPriv =
(struct st_manager_private *)smapi->st_manager_private;
 struct hash_entry *entry;
  
-   if (!smPriv || !smPriv->stfbi_ht);

+   if (!smPriv || !smPriv->stfbi_ht)
return;
  
 mtx_lock(>st_mutex);

 entry = _mesa_hash_table_search(smPriv->stfbi_ht, stfbi);
 if (!entry)
goto unlock;
  
 _mesa_hash_table_remove(smPriv->stfbi_ht, entry);
  
  unlock:



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Re: [Mesa-dev] [PATCH v2 2/2] st/dri2: Return invalid modifier when no driver support

[Marek Olšák]

For the series:

Reviewed-by: Marek Olšák 

Marek

On Mon, Jul 24, 2017 at 5:46 PM, Daniel Stone  wrote:
> Always initialise whandle.modifier for DRIImage modifier queries, so if
> the driver doesn't support it then we return false for the query.
>
> Signed-off-by: Daniel Stone 
> Cc: Varad Gautam 
> Fixes: d33fe8b84e45 ("st/dri: enable DRIimage modifier queries")
> ---
>  src/gallium/state_trackers/dri/dri2.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/src/gallium/state_trackers/dri/dri2.c 
> b/src/gallium/state_trackers/dri/dri2.c
> index 151fa5312a..688db8835b 100644
> --- a/src/gallium/state_trackers/dri/dri2.c
> +++ b/src/gallium/state_trackers/dri/dri2.c
> @@ -1239,14 +1239,20 @@ dri2_query_image(__DRIimage *image, int attrib, int 
> *value)
>return GL_TRUE;
> case __DRI_IMAGE_ATTRIB_MODIFIER_UPPER:
>whandle.type = DRM_API_HANDLE_TYPE_KMS;
> +  whandle.modifier = DRM_FORMAT_MOD_INVALID;
>if 
> (!image->texture->screen->resource_get_handle(image->texture->screen,
>  NULL, image->texture, , usage))
> +  if (whandle.modifier == DRM_FORMAT_MOD_INVALID)
> + return GL_FALSE;
>*value = (whandle.modifier >> 32) & 0x;
>return GL_TRUE;
> case __DRI_IMAGE_ATTRIB_MODIFIER_LOWER:
>whandle.type = DRM_API_HANDLE_TYPE_KMS;
> +  whandle.modifier = DRM_FORMAT_MOD_INVALID;
>if 
> (!image->texture->screen->resource_get_handle(image->texture->screen,
>  NULL, image->texture, , usage))
> +  if (whandle.modifier == DRM_FORMAT_MOD_INVALID)
> + return GL_FALSE;
>*value = whandle.modifier & 0x;
>return GL_TRUE;
> default:
> --
> 2.13.2
>
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Re: [Mesa-dev] [PATCH 1/2] gallium/radeon: make S_FIXED function signed and move it to shared code

[Kenneth Graunke]

On Tuesday, July 25, 2017 8:36:36 AM PDT Marek Olšák wrote:
> From: Marek Olšák 
> 
> This fixes a bug uncovered by:
> 2412c4c81ea0488df865817a0de91ec46e359b72
> util: Make CLAMP turn NaN into MIN.
> ---
>  src/gallium/drivers/r600/r600_pipe.h  | 4 
>  src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
>  src/gallium/drivers/radeonsi/si_state.c   | 5 -
>  3 files changed, 5 insertions(+), 9 deletions(-)

You might want to use int32_t to match the copy in src/mesa/main/macros.h.
Longer term, we might want to move those to src/util/*.h, which would let
you drop your extra copy.

Either way,
Reviewed-by: Kenneth Graunke 

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[Mesa-dev] [PATCH] ac/surface: fix hybrid graphics where APU=GFX9, dGPU=older

[Marek Olšák]

From: Marek Olšák 

Cc: 17.2 
---
 src/amd/common/ac_surface.c | 11 +++
 1 file changed, 11 insertions(+)

diff --git a/src/amd/common/ac_surface.c b/src/amd/common/ac_surface.c
index cd3d7b7..9e5390b 100644
--- a/src/amd/common/ac_surface.c
+++ b/src/amd/common/ac_surface.c
@@ -250,20 +250,31 @@ static int gfx6_compute_level(ADDR_HANDLE addrlib,
  ADDR_COMPUTE_HTILE_INFO_INPUT *AddrHtileIn,
  ADDR_COMPUTE_HTILE_INFO_OUTPUT *AddrHtileOut)
 {
struct legacy_surf_level *surf_level;
ADDR_E_RETURNCODE ret;
 
AddrSurfInfoIn->mipLevel = level;
AddrSurfInfoIn->width = u_minify(config->info.width, level);
AddrSurfInfoIn->height = u_minify(config->info.height, level);
 
+   /* Make GFX6 linear surfaces compatible with GFX9 for hybrid graphics,
+* because GFX9 needs linear alignment of 256 bytes.
+*/
+   if (config->info.levels == 1 &&
+   AddrSurfInfoIn->tileMode == ADDR_TM_LINEAR_ALIGNED) {
+   unsigned alignment = 256 / (AddrSurfInfoIn->bpp / 8);
+
+   assert(util_is_power_of_two(AddrSurfInfoIn->bpp));
+   AddrSurfInfoIn->width = align(AddrSurfInfoIn->width, alignment);
+   }
+
if (config->is_3d)
AddrSurfInfoIn->numSlices = u_minify(config->info.depth, level);
else if (config->is_cube)
AddrSurfInfoIn->numSlices = 6;
else
AddrSurfInfoIn->numSlices = config->info.array_size;
 
if (level > 0) {
/* Set the base level pitch. This is needed for calculation
 * of non-zero levels. */
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 1/2] gallium/radeon: make S_FIXED function signed and move it to shared code

[Roland Scheidegger]

Reviewed-by: Roland Scheidegger 

Am 25.07.2017 um 17:36 schrieb Marek Olšák:
> From: Marek Olšák 
> 
> This fixes a bug uncovered by:
> 2412c4c81ea0488df865817a0de91ec46e359b72
> util: Make CLAMP turn NaN into MIN.
> ---
>  src/gallium/drivers/r600/r600_pipe.h  | 4 
>  src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
>  src/gallium/drivers/radeonsi/si_state.c   | 5 -
>  3 files changed, 5 insertions(+), 9 deletions(-)
> 
> diff --git a/src/gallium/drivers/r600/r600_pipe.h 
> b/src/gallium/drivers/r600/r600_pipe.h
> index 3fa7d77..c9294a7 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -918,24 +918,20 @@ static inline void radeon_set_context_reg_flag(struct 
> radeon_winsys_cs *cs, unsi
>  
>  static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, 
> unsigned reg, unsigned value)
>  {
>   radeon_set_ctl_const_seq(cs, reg, 1);
>   radeon_emit(cs, value);
>  }
>  
>  /*
>   * common helpers
>   */
> -static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
> -{
> - return value * (1 << frac_bits);
> -}
>  
>  /* 12.4 fixed-point */
>  static inline unsigned r600_pack_float_12p4(float x)
>  {
>   return x <= 0? 0 :
>  x >= 4096 ? 0x : x * 16;
>  }
>  
>  static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
>  {
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 5c761f3..c2fb369 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -999,11 +999,16 @@ vi_dcc_enabled(struct r600_texture *tex, unsigned level)
>  #define R600_ERR(fmt, args...) \
>   fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, 
> ##args)
>  
>  /* For MSAA sample positions. */
>  #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
>   (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |  \
>   (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |  
>\
>   (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | 
>\
>(((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
>  
> +static inline int S_FIXED(float value, unsigned frac_bits)
> +{
> + return value * (1 << frac_bits);
> +}
> +
>  #endif
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index 7e3d1a0..42d81e7 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -67,25 +67,20 @@ static unsigned si_map_swizzle(unsigned swizzle)
>   return V_008F0C_SQ_SEL_W;
>   case PIPE_SWIZZLE_0:
>   return V_008F0C_SQ_SEL_0;
>   case PIPE_SWIZZLE_1:
>   return V_008F0C_SQ_SEL_1;
>   default: /* PIPE_SWIZZLE_X */
>   return V_008F0C_SQ_SEL_X;
>   }
>  }
>  
> -static uint32_t S_FIXED(float value, uint32_t frac_bits)
> -{
> - return value * (1 << frac_bits);
> -}
> -
>  /* 12.4 fixed-point */
>  static unsigned si_pack_float_12p4(float x)
>  {
>   return x <= 0? 0 :
>  x >= 4096 ? 0x : x * 16;
>  }
>  
>  /*
>   * Inferred framebuffer and blender state.
>   *
> 

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Re: [Mesa-dev] [PATCH 2/2] radeonsi: decrease the number of compiler threads

[Marek Olšák]

This will also go to stable.

Marek

On Tue, Jul 25, 2017 at 5:36 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> ---
>  src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
>  src/gallium/drivers/radeonsi/si_pipe.h | 9 +++--
>  2 files changed, 8 insertions(+), 3 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 0bc3002..234469f 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -963,21 +963,21 @@ struct pipe_screen *radeonsi_screen_create(struct 
> radeon_winsys *ws,
> if (!util_queue_init(>shader_compiler_queue, "si_shader",
>  32, num_compiler_threads,
>  UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
> si_destroy_shader_cache(sscreen);
> FREE(sscreen);
> return NULL;
> }
>
> if (!util_queue_init(>shader_compiler_queue_low_priority,
>  "si_shader_low",
> -32, num_compiler_threads,
> +32, num_compiler_threads_lowprio,
>  UTIL_QUEUE_INIT_RESIZE_IF_FULL |
>  UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
>si_destroy_shader_cache(sscreen);
>FREE(sscreen);
>return NULL;
> }
>
> si_handle_env_var_force_family(sscreen);
>
> if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
> b/src/gallium/drivers/radeonsi/si_pipe.h
> index c028aba..d25705b 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.h
> +++ b/src/gallium/drivers/radeonsi/si_pipe.h
> @@ -106,24 +106,29 @@ struct si_screen {
>  * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
>  *   variants of VS and TES are cached, so LS and ES aren't.
>  * - GS and CS aren't cached, but it's certainly possible to cache
>  *   those as well.
>  */
> mtx_t   shader_cache_mutex;
> struct hash_table   *shader_cache;
>
> /* Shader compiler queue for multithreaded compilation. */
> struct util_queue   shader_compiler_queue;
> -   LLVMTargetMachineReftm[4]; /* used by the queue only */
> +   /* Use at most 3 normal compiler threads on quadcore and better.
> +* Hyperthreaded CPUs report the number of threads, but we want
> +* the number of cores. */
> +   LLVMTargetMachineReftm[3]; /* used by the queue only */
>
> struct util_queue   shader_compiler_queue_low_priority;
> -   LLVMTargetMachineReftm_low_priority[4];
> +   /* Use at most 2 low priority threads on quadcore and better.
> +* We want to minimize the impact on multithreaded Mesa. */
> +   LLVMTargetMachineReftm_low_priority[2]; /* at most 2 
> threads */
>  };
>
>  struct si_blend_color {
> struct r600_atomatom;
> struct pipe_blend_color state;
>  };
>
>  struct si_sampler_view {
> struct pipe_sampler_viewbase;
>  /* [0..7] = image descriptor
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] st/mesa: always unconditionally revalidate main framebuffer after SwapBuffers

[Marek Olšák]

This will also go to stable.

Marek

On Tue, Jul 25, 2017 at 5:39 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> This fixes the black Feral launcher window.
>
> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867
> ---
>  src/mesa/state_tracker/st_manager.c | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/src/mesa/state_tracker/st_manager.c 
> b/src/mesa/state_tracker/st_manager.c
> index 834bcc9..ede5439 100644
> --- a/src/mesa/state_tracker/st_manager.c
> +++ b/src/mesa/state_tracker/st_manager.c
> @@ -635,20 +635,26 @@ st_context_flush(struct st_context_iface *stctxi, 
> unsigned flags,
> st_flush(st, fence, pipe_flags);
>
> if ((flags & ST_FLUSH_WAIT) && fence) {
>st->pipe->screen->fence_finish(st->pipe->screen, NULL, *fence,
>   PIPE_TIMEOUT_INFINITE);
>st->pipe->screen->fence_reference(st->pipe->screen, fence, NULL);
> }
>
> if (flags & ST_FLUSH_FRONT)
>st_manager_flush_frontbuffer(st);
> +
> +   /* Enter st_validate_state in the next draw call to revalidate
> +* the framebuffer.
> +*/
> +   if (flags & ST_FLUSH_END_OF_FRAME)
> +  st->gfx_shaders_may_be_dirty = true;
>  }
>
>  static boolean
>  st_context_teximage(struct st_context_iface *stctxi,
>  enum st_texture_type tex_type,
>  int level, enum pipe_format pipe_format,
>  struct pipe_resource *tex, boolean mipmap)
>  {
> struct st_context *st = (struct st_context *) stctxi;
> struct gl_context *ctx = st->ctx;
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH 1/2] gallium/radeon: make S_FIXED function signed and move it to shared code

[Marek Olšák]

This will also go to stable.

Marek

On Tue, Jul 25, 2017 at 5:36 PM, Marek Olšák  wrote:
> From: Marek Olšák 
>
> This fixes a bug uncovered by:
> 2412c4c81ea0488df865817a0de91ec46e359b72
> util: Make CLAMP turn NaN into MIN.
> ---
>  src/gallium/drivers/r600/r600_pipe.h  | 4 
>  src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
>  src/gallium/drivers/radeonsi/si_state.c   | 5 -
>  3 files changed, 5 insertions(+), 9 deletions(-)
>
> diff --git a/src/gallium/drivers/r600/r600_pipe.h 
> b/src/gallium/drivers/r600/r600_pipe.h
> index 3fa7d77..c9294a7 100644
> --- a/src/gallium/drivers/r600/r600_pipe.h
> +++ b/src/gallium/drivers/r600/r600_pipe.h
> @@ -918,24 +918,20 @@ static inline void radeon_set_context_reg_flag(struct 
> radeon_winsys_cs *cs, unsi
>
>  static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, 
> unsigned reg, unsigned value)
>  {
> radeon_set_ctl_const_seq(cs, reg, 1);
> radeon_emit(cs, value);
>  }
>
>  /*
>   * common helpers
>   */
> -static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
> -{
> -   return value * (1 << frac_bits);
> -}
>
>  /* 12.4 fixed-point */
>  static inline unsigned r600_pack_float_12p4(float x)
>  {
> return x <= 0? 0 :
>x >= 4096 ? 0x : x * 16;
>  }
>
>  static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
>  {
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
> b/src/gallium/drivers/radeon/r600_pipe_common.h
> index 5c761f3..c2fb369 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.h
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.h
> @@ -999,11 +999,16 @@ vi_dcc_enabled(struct r600_texture *tex, unsigned level)
>  #define R600_ERR(fmt, args...) \
> fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, 
> ##args)
>
>  /* For MSAA sample positions. */
>  #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
> (((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |  \
> (((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |
>  \
> (((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) |   
>  \
>  (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
>
> +static inline int S_FIXED(float value, unsigned frac_bits)
> +{
> +   return value * (1 << frac_bits);
> +}
> +
>  #endif
> diff --git a/src/gallium/drivers/radeonsi/si_state.c 
> b/src/gallium/drivers/radeonsi/si_state.c
> index 7e3d1a0..42d81e7 100644
> --- a/src/gallium/drivers/radeonsi/si_state.c
> +++ b/src/gallium/drivers/radeonsi/si_state.c
> @@ -67,25 +67,20 @@ static unsigned si_map_swizzle(unsigned swizzle)
> return V_008F0C_SQ_SEL_W;
> case PIPE_SWIZZLE_0:
> return V_008F0C_SQ_SEL_0;
> case PIPE_SWIZZLE_1:
> return V_008F0C_SQ_SEL_1;
> default: /* PIPE_SWIZZLE_X */
> return V_008F0C_SQ_SEL_X;
> }
>  }
>
> -static uint32_t S_FIXED(float value, uint32_t frac_bits)
> -{
> -   return value * (1 << frac_bits);
> -}
> -
>  /* 12.4 fixed-point */
>  static unsigned si_pack_float_12p4(float x)
>  {
> return x <= 0? 0 :
>x >= 4096 ? 0x : x * 16;
>  }
>
>  /*
>   * Inferred framebuffer and blender state.
>   *
> --
> 2.7.4
>
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Re: [Mesa-dev] [PATCH] radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jul 25, 2017 at 4:51 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> The firmware version numbers for SI were wrong. The new numbers are probably
> too conservative (we don't have a definitive answer by the firmware team),
> but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
> Tahiti (by Gustaw) and on Verde (by myself).
>
> While this is technically adding a feature, it's a feature we thought we had
> for a long time. The change is small enough and we're early enough in the 17.2
> release cycle that it should still go in.
>
> Reported-by: Gustaw Smolarczyk 
> Cc: 17.2 
> ---
>  src/gallium/drivers/radeonsi/si_pipe.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 0bc3002..2b0f9d3 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -1002,8 +1002,8 @@ struct pipe_screen *radeonsi_screen_create(struct 
> radeon_winsys *ws,
>  sscreen->b.info.pfp_fw_version >= 211 &&
>  sscreen->b.info.me_fw_version >= 173) ||
> (sscreen->b.chip_class == SI &&
> -sscreen->b.info.pfp_fw_version >= 121 &&
> -sscreen->b.info.me_fw_version >= 87);
> +sscreen->b.info.pfp_fw_version >= 79 &&
> +sscreen->b.info.me_fw_version >= 142);
>
> sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
> sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= 
> CHIP_POLARIS10 &&
> --
> 2.9.3
>
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[Mesa-dev] [PATCH] st/mesa: fix unconditional return in st_framebuffer_iface_remove

[Marek Olšák]

From: Marek Olšák 

Cc: 17.2 
---
 src/mesa/state_tracker/st_manager.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index ede5439..78093ac 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -553,21 +553,21 @@ st_framebuffer_iface_insert(struct st_manager *smapi,
 
 
 static void
 st_framebuffer_iface_remove(struct st_manager *smapi,
 struct st_framebuffer_iface *stfbi)
 {
struct st_manager_private *smPriv =
   (struct st_manager_private *)smapi->st_manager_private;
struct hash_entry *entry;
 
-   if (!smPriv || !smPriv->stfbi_ht);
+   if (!smPriv || !smPriv->stfbi_ht)
   return;
 
mtx_lock(>st_mutex);
entry = _mesa_hash_table_search(smPriv->stfbi_ht, stfbi);
if (!entry)
   goto unlock;
 
_mesa_hash_table_remove(smPriv->stfbi_ht, entry);
 
 unlock:
-- 
2.7.4

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Re: [Mesa-dev] [Mesa-stable] [PATCH] radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+

[Marek Olšák]

Reviewed-by: Marek Olšák 

Marek

On Tue, Jul 25, 2017 at 4:46 PM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> The number of supported waves per thread group has been officially
> reduced to 16 with gfx9 (and trying to use 32 waves causes hangs).
>
> Cc: mesa-sta...@lists.freedesktop.org
> ---
>  src/gallium/drivers/radeon/r600_pipe_common.c | 39 
> ---
>  1 file changed, 24 insertions(+), 15 deletions(-)
>
> diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
> b/src/gallium/drivers/radeon/r600_pipe_common.c
> index fd67d9a..cc52d6b 100644
> --- a/src/gallium/drivers/radeon/r600_pipe_common.c
> +++ b/src/gallium/drivers/radeon/r600_pipe_common.c
> @@ -1024,6 +1024,25 @@ const char *r600_get_llvm_processor_name(enum 
> radeon_family family)
> }
>  }
>
> +static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
> + enum pipe_shader_ir ir_type)
> +{
> +   if (ir_type != PIPE_SHADER_IR_TGSI)
> +   return 256;
> +
> +   /* Only 16 waves per thread-group on gfx9. */
> +   if (screen->chip_class >= GFX9)
> +   return 1024;
> +
> +   /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
> +* round number.
> +*/
> +   if (screen->chip_class >= SI)
> +   return 2048;
> +
> +   return 256;
> +}
> +
>  static int r600_get_compute_param(struct pipe_screen *screen,
>  enum pipe_shader_ir ir_type,
>  enum pipe_compute_cap param,
> @@ -1078,27 +1097,17 @@ static int r600_get_compute_param(struct pipe_screen 
> *screen,
> case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
> if (ret) {
> uint64_t *block_size = ret;
> -   if (rscreen->chip_class >= SI &&
> -   ir_type == PIPE_SHADER_IR_TGSI) {
> -   block_size[0] = 2048;
> -   block_size[1] = 2048;
> -   block_size[2] = 2048;
> -   } else {
> -   block_size[0] = 256;
> -   block_size[1] = 256;
> -   block_size[2] = 256;
> -   }
> +   unsigned threads_per_block = 
> get_max_threads_per_block(rscreen, ir_type);
> +   block_size[0] = threads_per_block;
> +   block_size[1] = threads_per_block;
> +   block_size[2] = threads_per_block;
> }
> return 3 * sizeof(uint64_t);
>
> case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
> if (ret) {
> uint64_t *max_threads_per_block = ret;
> -   if (rscreen->chip_class >= SI &&
> -   ir_type == PIPE_SHADER_IR_TGSI)
> -   *max_threads_per_block = 2048;
> -   else
> -   *max_threads_per_block = 256;
> +   *max_threads_per_block = 
> get_max_threads_per_block(rscreen, ir_type);
> }
> return sizeof(uint64_t);
> case PIPE_COMPUTE_CAP_ADDRESS_BITS:
> --
> 2.9.3
>
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Re: [Mesa-dev] [PATCH] radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI

[Alex Deucher]

On Tue, Jul 25, 2017 at 10:51 AM, Nicolai Hähnle  wrote:
> From: Nicolai Hähnle 
>
> The firmware version numbers for SI were wrong. The new numbers are probably
> too conservative (we don't have a definitive answer by the firmware team),
> but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
> Tahiti (by Gustaw) and on Verde (by myself).
>
> While this is technically adding a feature, it's a feature we thought we had
> for a long time. The change is small enough and we're early enough in the 17.2
> release cycle that it should still go in.
>
> Reported-by: Gustaw Smolarczyk 
> Cc: 17.2 

Acked-by: Alex Deucher 

> ---
>  src/gallium/drivers/radeonsi/si_pipe.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
> b/src/gallium/drivers/radeonsi/si_pipe.c
> index 0bc3002..2b0f9d3 100644
> --- a/src/gallium/drivers/radeonsi/si_pipe.c
> +++ b/src/gallium/drivers/radeonsi/si_pipe.c
> @@ -1002,8 +1002,8 @@ struct pipe_screen *radeonsi_screen_create(struct 
> radeon_winsys *ws,
>  sscreen->b.info.pfp_fw_version >= 211 &&
>  sscreen->b.info.me_fw_version >= 173) ||
> (sscreen->b.chip_class == SI &&
> -sscreen->b.info.pfp_fw_version >= 121 &&
> -sscreen->b.info.me_fw_version >= 87);
> +sscreen->b.info.pfp_fw_version >= 79 &&
> +sscreen->b.info.me_fw_version >= 142);
>
> sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
> sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= 
> CHIP_POLARIS10 &&
> --
> 2.9.3
>
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Re: [Mesa-dev] [shader-db 0/3] Small README clean ups

[Chema Casanova]

On 25/07/17 13:58, Rhys Kidd wrote:
> On 24 July 2017 at 23:42, Rhys Kidd  > wrote:
>
> Update or fix a few small items that I noticed when running
> through piglit
> setup on a new development environment.
>
>
> Ah, whoops. The subject prefix for this series should be [piglit] not
> [shader-db].
>  

Piglit project has his own list, it would be better to submit your
patches to

pig...@lists.freedesktop.org

and subscribe to the mailing list at

 https://lists.freedesktop.org/mailman/listinfo/piglit

Chema Casanova

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Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence for Android OS v4.2

[Rafael Antognolli]

On Tue, Jul 25, 2017 at 10:07:23AM +0800, Zhongmin Wu wrote:
> Before we queued the buffer with a invalid fence (-1), it will
> make some benchmarks failed to test such as flatland.
> 
> Now we get the out fence during the flushing buffer and then pass
> it to SurfaceFlinger in eglSwapbuffer function.
> 
> v2: a) Also implement the fence in cancelBuffer.
> b) The last sync fence is stored in drawable object
>rather than brw context.
> c) format clear.
> 
> v3: a) Save the last fence fd in DRI Context object.
> b) Return the last fence if the batch buffer is empty and
>nothing to be flushed when _intel_batchbuffer_flush_fence
> c) Add the new interface in vbtl to set the retrieve fence
> 
> v3.1 a) close fd in the new vbtl interface on none Android platform
> 
> v4: a) The last fence is saved in brw context.
> b) The retrieve fd is for all the platform but not just Android
> c) Add a uniform dri2 interface to initialize the surface.
> 
> v4.1: a) make some changes of variable name.
>   b) the patch is breaked into two patches.
> 
> v4.2: a) Add a deinit interface for surface to clear the out fence

Hi Zhongmin,

The patch is indeed looking better. I agree with Tomasz, it would be good to
have a way for the platform to inform whether it is interested in fences or
not. What about some flag that you pass to dri2_surf_init? (I'm not sure
that's the best place, though).

Please see other comments below.

> Change-Id: Ided54d2e193cde73a6f0feb36ac1c0056e4958f2
> Signed-off-by: Zhongmin Wu 
> ---
>  src/egl/drivers/dri2/egl_dri2.c |   51 
> +++
>  src/egl/drivers/dri2/egl_dri2.h |8 +
>  src/egl/drivers/dri2/platform_android.c |   12 ---
>  src/egl/drivers/dri2/platform_drm.c |3 +-
>  src/egl/drivers/dri2/platform_surfaceless.c |3 +-
>  src/egl/drivers/dri2/platform_wayland.c |3 +-
>  src/egl/drivers/dri2/platform_x11.c |3 +-
>  src/egl/drivers/dri2/platform_x11_dri3.c|3 +-
>  8 files changed, 77 insertions(+), 9 deletions(-)
> 
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index 020a0bc..ffd3a8a 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -1307,6 +1307,32 @@ dri2_destroy_context(_EGLDriver *drv, _EGLDisplay 
> *disp, _EGLContext *ctx)
> return EGL_TRUE;
>  }
>  
> +EGLBoolean
> +dri2_surf_init(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
> +_EGLConfig *conf, const EGLint *attrib_list)
> +{
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +   dri2_surf->out_fence_fd = -1;
> +   return _eglInitSurface(surf, dpy, type, conf, attrib_list);
> +}
> +
> +static void
> +dri2_surface_set_out_fence( _EGLSurface *surf, int fence_fd)
> +{
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +   if (dri2_surf->out_fence_fd >=0)
> +  close(dri2_surf->out_fence_fd);
> +
> +   dri2_surf->out_fence_fd = fence_fd;
> +}
> +
> +void
> +dri2_surf_deinit(_EGLSurface *surf)
> +{
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +   dri2_surface_set_out_fence(surf, -1);
> +}
> +
>  static EGLBoolean
>  dri2_destroy_surface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf)
>  {
> @@ -1318,6 +1344,22 @@ dri2_destroy_surface(_EGLDriver *drv, _EGLDisplay 
> *dpy, _EGLSurface *surf)
> return dri2_dpy->vtbl->destroy_surface(drv, dpy, surf);
>  }
>  
> +static void
> +dri2_surf_get_fence_fd(_EGLContext *ctx,

Maybe it's just me but every time I read this code I get confused by the name
of this function, since it says "get_fence_fd" but doesn't really return
anything. How about dri2_surf_update_fence_fd?

> +   _EGLDisplay *dpy, _EGLSurface *surf)
> +{
> +   struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> +   int fence_fd = -1;
> +   __DRIcontext *dri_ctx = dri2_egl_context(ctx)->dri_context;
> +   void * fence = dri2_dpy->fence->create_fence_fd(dri_ctx, -1);

Before calling any of the dri2 fence extension, shouldn't we check whether it
is available? I think you had these checks in earlier versions of this patch,
but maybe it got lost along the way.

> +   if (fence) {
> +  fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen,
> +   fence);
> +  dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
> +   }
> +   dri2_surface_set_out_fence(surf, fence_fd);
> +}
> +
>  /**
>   * Called via eglMakeCurrent(), drv->API.MakeCurrent().
>   */
> @@ -1352,8 +1394,11 @@ dri2_make_current(_EGLDriver *drv, _EGLDisplay *disp, 
> _EGLSurface *dsurf,
> rdraw = (rsurf) ? dri2_dpy->vtbl->get_dri_drawable(rsurf) : NULL;
> cctx = (dri2_ctx) ? dri2_ctx->dri_context : NULL;
>  
> +   int fence_fd = -1;
> if (old_ctx) {
>__DRIcontext *old_cctx = dri2_egl_context(old_ctx)->dri_context;
> +  if 

[Mesa-dev] [Bug 101867] Launch options window renders black in Feral Games in current Mesa trunk

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=101867

--- Comment #10 from Marc Di Luzio  ---
(In reply to James Legg from comment #6)
> traces from builds of recent Feral titles available on Steam will be
> difficult as we've tried to avoid Steam injecting its overlay in the options
> window when glXSwapBuffer is called, and this also prevents apitrace from
> capturing those calls (which are important for this bug).

Unknown to James at the time we do have a way of disabling this in live builds.

I'll note it here so that someone else who stumbles on a similar issue can know
how to grab a working trace of our options window.

In ~/.local/share/feral-interactive/{GAMENAME}/preferences there'll be a key
called "AvoidSwapInjectionDuringPGOW" that basically does what it says on the
tin - setting it to 0 will prevent our steam overlay avoidance occurring.

If that key doesn't exist then it's an older game without the swap hack.

I've seen the mesa-dev patch mail, thanks Marek!

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Re: [Mesa-dev] [RFC PATCH] radeonsi: flush DB caches when a Z/stencil buffer is attached

[Samuel Pitoiset]

On 07/25/2017 05:51 PM, Nicolai Hähnle wrote:

On 25.07.2017 15:29, Samuel Pitoiset wrote:

This is a workaround which fixes a rendering issue with Dawn
Of War III in full bindless mode because a depth texture most
likely doesn't invoke the decompression pass when it should.


So do I understand correctly that the previous depth target is used 
bindless, and for whatever reason the si_decompress_depth doesn't 
properly trigger for bindless? Why doesn't it trigger?


Exactly, but I still don't know why it is not triggered correctly.



Cheers,
Nicolai



Performance drops by 1% which doesn't really matter.

Fixes: 2263610827 ("radeonsi: flush DB caches only when transitioning 
from DB to texturing")

Signed-off-by: Samuel Pitoiset 
Cc: "17.2" 
---
  src/gallium/drivers/radeonsi/si_state.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c

index 7e3d1a02e0..675b61ad7f 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2546,6 +2546,16 @@ static void si_set_framebuffer_state(struct 
pipe_context *ctx,

  }
  sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
+/* Flush DB caches when a Z/stencil buffer is attached to the
+ * framebuffer. This is a workaround which fixes a rendering 
issue with
+ * Dawn Of War III in full bindless mode because a depth texture 
most

+ * likely doesn't invoke the decompression pass when it should.
+ *
+ * TODO: Figure out a better fix.
+ */
+if (sctx->framebuffer.state.zsbuf)
+sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
+
  /* u_blitter doesn't invoke depth decompression when it does 
multiple

   * blits in a row, but the only case when it matters for DB is when
   * doing generate_mipmap. So here we flush DB manually between





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Re: [Mesa-dev] [RFC PATCH] radeonsi: flush DB caches when a Z/stencil buffer is attached

[Nicolai Hähnle]

On 25.07.2017 15:29, Samuel Pitoiset wrote:

This is a workaround which fixes a rendering issue with Dawn
Of War III in full bindless mode because a depth texture most
likely doesn't invoke the decompression pass when it should.


So do I understand correctly that the previous depth target is used 
bindless, and for whatever reason the si_decompress_depth doesn't 
properly trigger for bindless? Why doesn't it trigger?


Cheers,
Nicolai



Performance drops by 1% which doesn't really matter.

Fixes: 2263610827 ("radeonsi: flush DB caches only when transitioning from DB to 
texturing")
Signed-off-by: Samuel Pitoiset 
Cc: "17.2" 
---
  src/gallium/drivers/radeonsi/si_state.c | 10 ++
  1 file changed, 10 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 7e3d1a02e0..675b61ad7f 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2546,6 +2546,16 @@ static void si_set_framebuffer_state(struct pipe_context 
*ctx,
}
sctx->b.flags |= SI_CONTEXT_CS_PARTIAL_FLUSH;
  
+	/* Flush DB caches when a Z/stencil buffer is attached to the

+* framebuffer. This is a workaround which fixes a rendering issue with
+* Dawn Of War III in full bindless mode because a depth texture most
+* likely doesn't invoke the decompression pass when it should.
+*
+* TODO: Figure out a better fix.
+*/
+   if (sctx->framebuffer.state.zsbuf)
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
+
/* u_blitter doesn't invoke depth decompression when it does multiple
 * blits in a row, but the only case when it matters for DB is when
 * doing generate_mipmap. So here we flush DB manually between




--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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[Mesa-dev] [PATCH] st/mesa: always unconditionally revalidate main framebuffer after SwapBuffers

[Marek Olšák]

From: Marek Olšák 

This fixes the black Feral launcher window.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=101867
---
 src/mesa/state_tracker/st_manager.c | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/mesa/state_tracker/st_manager.c 
b/src/mesa/state_tracker/st_manager.c
index 834bcc9..ede5439 100644
--- a/src/mesa/state_tracker/st_manager.c
+++ b/src/mesa/state_tracker/st_manager.c
@@ -635,20 +635,26 @@ st_context_flush(struct st_context_iface *stctxi, 
unsigned flags,
st_flush(st, fence, pipe_flags);
 
if ((flags & ST_FLUSH_WAIT) && fence) {
   st->pipe->screen->fence_finish(st->pipe->screen, NULL, *fence,
  PIPE_TIMEOUT_INFINITE);
   st->pipe->screen->fence_reference(st->pipe->screen, fence, NULL);
}
 
if (flags & ST_FLUSH_FRONT)
   st_manager_flush_frontbuffer(st);
+
+   /* Enter st_validate_state in the next draw call to revalidate
+* the framebuffer.
+*/
+   if (flags & ST_FLUSH_END_OF_FRAME)
+  st->gfx_shaders_may_be_dirty = true;
 }
 
 static boolean
 st_context_teximage(struct st_context_iface *stctxi,
 enum st_texture_type tex_type,
 int level, enum pipe_format pipe_format,
 struct pipe_resource *tex, boolean mipmap)
 {
struct st_context *st = (struct st_context *) stctxi;
struct gl_context *ctx = st->ctx;
-- 
2.7.4

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Re: [Mesa-dev] [PATCH 2/2] util: Make CLAMP turn NaN into MIN.

[Marek Olšák]

On Tue, Jul 25, 2017 at 8:12 AM, Roland Scheidegger  wrote:
> Am 24.07.2017 um 11:44 schrieb Michel Dänzer:
>> On 14/07/17 10:01 PM, Marek Olšák wrote:
>>> Reviewed-by: Marek Olšák >
>>
>> This change broke piglit spec@ext_texture_lod_bias@lodbias for me with
>> radeonsi (but not with llvmpipe).
>>
>>
>
> The S_FIXED function needs some fixing (for r600 too). The compiler
> takes full advantage of the fact that float to unsigned conversion is
> undefined for negative floats, apparently.
> The previous CLAMP would have used the state->lod_bias value if that was
> equal to the MIN value (-16) (so no way for the compiler to screw it up)
> whereas now it will use the -16 value.
> (This also means it was probably broken before, for values which were
> smaller than the min, albeit possibly noone cared as that would have
> been outside the advertized lod bias limits.)
> FWIW gcc generates a really terrible code for this (but that's not
> really dependent on the new or old macro...)
> (There's the same macro in mesa/main macros, but with signed numbers.)

https://patchwork.freedesktop.org/patch/168931/

Marek
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[Mesa-dev] [PATCH 1/2] gallium/radeon: make S_FIXED function signed and move it to shared code

[Marek Olšák]

From: Marek Olšák 

This fixes a bug uncovered by:
2412c4c81ea0488df865817a0de91ec46e359b72
util: Make CLAMP turn NaN into MIN.
---
 src/gallium/drivers/r600/r600_pipe.h  | 4 
 src/gallium/drivers/radeon/r600_pipe_common.h | 5 +
 src/gallium/drivers/radeonsi/si_state.c   | 5 -
 3 files changed, 5 insertions(+), 9 deletions(-)

diff --git a/src/gallium/drivers/r600/r600_pipe.h 
b/src/gallium/drivers/r600/r600_pipe.h
index 3fa7d77..c9294a7 100644
--- a/src/gallium/drivers/r600/r600_pipe.h
+++ b/src/gallium/drivers/r600/r600_pipe.h
@@ -918,24 +918,20 @@ static inline void radeon_set_context_reg_flag(struct 
radeon_winsys_cs *cs, unsi
 
 static inline void radeon_set_ctl_const(struct radeon_winsys_cs *cs, unsigned 
reg, unsigned value)
 {
radeon_set_ctl_const_seq(cs, reg, 1);
radeon_emit(cs, value);
 }
 
 /*
  * common helpers
  */
-static inline uint32_t S_FIXED(float value, uint32_t frac_bits)
-{
-   return value * (1 << frac_bits);
-}
 
 /* 12.4 fixed-point */
 static inline unsigned r600_pack_float_12p4(float x)
 {
return x <= 0? 0 :
   x >= 4096 ? 0x : x * 16;
 }
 
 static inline unsigned r600_get_flush_flags(enum r600_coherency coher)
 {
diff --git a/src/gallium/drivers/radeon/r600_pipe_common.h 
b/src/gallium/drivers/radeon/r600_pipe_common.h
index 5c761f3..c2fb369 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.h
+++ b/src/gallium/drivers/radeon/r600_pipe_common.h
@@ -999,11 +999,16 @@ vi_dcc_enabled(struct r600_texture *tex, unsigned level)
 #define R600_ERR(fmt, args...) \
fprintf(stderr, "EE %s:%d %s - " fmt, __FILE__, __LINE__, __func__, 
##args)
 
 /* For MSAA sample positions. */
 #define FILL_SREG(s0x, s0y, s1x, s1y, s2x, s2y, s3x, s3y)  \
(((s0x) & 0xf) | (((unsigned)(s0y) & 0xf) << 4) |  \
(((unsigned)(s1x) & 0xf) << 8) | (((unsigned)(s1y) & 0xf) << 12) |  
   \
(((unsigned)(s2x) & 0xf) << 16) | (((unsigned)(s2y) & 0xf) << 20) | 
   \
 (((unsigned)(s3x) & 0xf) << 24) | (((unsigned)(s3y) & 0xf) << 28))
 
+static inline int S_FIXED(float value, unsigned frac_bits)
+{
+   return value * (1 << frac_bits);
+}
+
 #endif
diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 7e3d1a0..42d81e7 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -67,25 +67,20 @@ static unsigned si_map_swizzle(unsigned swizzle)
return V_008F0C_SQ_SEL_W;
case PIPE_SWIZZLE_0:
return V_008F0C_SQ_SEL_0;
case PIPE_SWIZZLE_1:
return V_008F0C_SQ_SEL_1;
default: /* PIPE_SWIZZLE_X */
return V_008F0C_SQ_SEL_X;
}
 }
 
-static uint32_t S_FIXED(float value, uint32_t frac_bits)
-{
-   return value * (1 << frac_bits);
-}
-
 /* 12.4 fixed-point */
 static unsigned si_pack_float_12p4(float x)
 {
return x <= 0? 0 :
   x >= 4096 ? 0x : x * 16;
 }
 
 /*
  * Inferred framebuffer and blender state.
  *
-- 
2.7.4

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[Mesa-dev] [PATCH 2/2] radeonsi: decrease the number of compiler threads

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_pipe.c | 2 +-
 src/gallium/drivers/radeonsi/si_pipe.h | 9 +++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 0bc3002..234469f 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -963,21 +963,21 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
if (!util_queue_init(>shader_compiler_queue, "si_shader",
 32, num_compiler_threads,
 UTIL_QUEUE_INIT_RESIZE_IF_FULL)) {
si_destroy_shader_cache(sscreen);
FREE(sscreen);
return NULL;
}
 
if (!util_queue_init(>shader_compiler_queue_low_priority,
 "si_shader_low",
-32, num_compiler_threads,
+32, num_compiler_threads_lowprio,
 UTIL_QUEUE_INIT_RESIZE_IF_FULL |
 UTIL_QUEUE_INIT_USE_MINIMUM_PRIORITY)) {
   si_destroy_shader_cache(sscreen);
   FREE(sscreen);
   return NULL;
}
 
si_handle_env_var_force_family(sscreen);
 
if (!debug_get_bool_option("RADEON_DISABLE_PERFCOUNTERS", false))
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index c028aba..d25705b 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -106,24 +106,29 @@ struct si_screen {
 * - Only VS, TCS, TES, PS are cached, out of which only the hw VS
 *   variants of VS and TES are cached, so LS and ES aren't.
 * - GS and CS aren't cached, but it's certainly possible to cache
 *   those as well.
 */
mtx_t   shader_cache_mutex;
struct hash_table   *shader_cache;
 
/* Shader compiler queue for multithreaded compilation. */
struct util_queue   shader_compiler_queue;
-   LLVMTargetMachineReftm[4]; /* used by the queue only */
+   /* Use at most 3 normal compiler threads on quadcore and better.
+* Hyperthreaded CPUs report the number of threads, but we want
+* the number of cores. */
+   LLVMTargetMachineReftm[3]; /* used by the queue only */
 
struct util_queue   shader_compiler_queue_low_priority;
-   LLVMTargetMachineReftm_low_priority[4];
+   /* Use at most 2 low priority threads on quadcore and better.
+* We want to minimize the impact on multithreaded Mesa. */
+   LLVMTargetMachineReftm_low_priority[2]; /* at most 2 
threads */
 };
 
 struct si_blend_color {
struct r600_atomatom;
struct pipe_blend_color state;
 };
 
 struct si_sampler_view {
struct pipe_sampler_viewbase;
 /* [0..7] = image descriptor
-- 
2.7.4

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[Mesa-dev] [PATCH] st/mesa: also clamp and quantize per-unit lod bias

[Marek Olšák]

From: Marek Olšák 

---
 src/mesa/state_tracker/st_atom_sampler.c | 7 ---
 src/mesa/state_tracker/st_cb_texture.c   | 2 +-
 src/mesa/state_tracker/st_texture.h  | 1 +
 3 files changed, 6 insertions(+), 4 deletions(-)

diff --git a/src/mesa/state_tracker/st_atom_sampler.c 
b/src/mesa/state_tracker/st_atom_sampler.c
index 208b6f7..d9e8de3 100644
--- a/src/mesa/state_tracker/st_atom_sampler.c
+++ b/src/mesa/state_tracker/st_atom_sampler.c
@@ -98,35 +98,36 @@ gl_filter_to_img_filter(GLenum filter)
 }
 
 
 /**
  * Convert a gl_sampler_object to a pipe_sampler_state object.
  */
 void
 st_convert_sampler(const struct st_context *st,
const struct gl_texture_object *texobj,
const struct gl_sampler_object *msamp,
+   float tex_unit_lod_bias,
struct pipe_sampler_state *sampler)
 {
memset(sampler, 0, sizeof(*sampler));
sampler->wrap_s = gl_wrap_xlate(msamp->WrapS);
sampler->wrap_t = gl_wrap_xlate(msamp->WrapT);
sampler->wrap_r = gl_wrap_xlate(msamp->WrapR);
 
sampler->min_img_filter = gl_filter_to_img_filter(msamp->MinFilter);
sampler->min_mip_filter = gl_filter_to_mip_filter(msamp->MinFilter);
sampler->mag_img_filter = gl_filter_to_img_filter(msamp->MagFilter);
 
if (texobj->Target != GL_TEXTURE_RECTANGLE_ARB)
   sampler->normalized_coords = 1;
 
-   sampler->lod_bias = msamp->LodBias;
+   sampler->lod_bias = msamp->LodBias + tex_unit_lod_bias;
/* Reduce the number of states by allowing only the values that AMD GCN
 * can represent. Apps use lod_bias for smooth transitions to bigger mipmap
 * levels.
 */
sampler->lod_bias = CLAMP(sampler->lod_bias, -16, 16);
sampler->lod_bias = floorf(sampler->lod_bias * 256) / 256;
 
sampler->min_lod = MAX2(msamp->MinLod, 0.0f);
sampler->max_lod = msamp->MaxLod;
if (sampler->max_lod < sampler->min_lod) {
@@ -234,23 +235,23 @@ st_convert_sampler_from_unit(const struct st_context *st,
const struct gl_texture_object *texobj;
struct gl_context *ctx = st->ctx;
const struct gl_sampler_object *msamp;
 
texobj = ctx->Texture.Unit[texUnit]._Current;
assert(texobj);
assert(texobj->Target != GL_TEXTURE_BUFFER);
 
msamp = _mesa_get_samplerobj(ctx, texUnit);
 
-   st_convert_sampler(st, texobj, msamp, sampler);
+   st_convert_sampler(st, texobj, msamp, ctx->Texture.Unit[texUnit].LodBias,
+  sampler);
 
-   sampler->lod_bias += ctx->Texture.Unit[texUnit].LodBias;
sampler->seamless_cube_map |= ctx->Texture.CubeMapSeamless;
 }
 
 
 /**
  * Update the gallium driver's sampler state for fragment, vertex or
  * geometry shader stage.
  */
 static void
 update_shader_samplers(struct st_context *st,
diff --git a/src/mesa/state_tracker/st_cb_texture.c 
b/src/mesa/state_tracker/st_cb_texture.c
index f66e1bd..eba9c30 100644
--- a/src/mesa/state_tracker/st_cb_texture.c
+++ b/src/mesa/state_tracker/st_cb_texture.c
@@ -2965,21 +2965,21 @@ st_NewTextureHandle(struct gl_context *ctx, struct 
gl_texture_object *texObj,
struct st_context *st = st_context(ctx);
struct st_texture_object *stObj = st_texture_object(texObj);
struct pipe_context *pipe = st->pipe;
struct pipe_sampler_view *view;
struct pipe_sampler_state sampler = {0};
 
if (texObj->Target != GL_TEXTURE_BUFFER) {
   if (!st_finalize_texture(ctx, pipe, texObj, 0))
  return 0;
 
-  st_convert_sampler(st, texObj, sampObj, );
+  st_convert_sampler(st, texObj, sampObj, 0, );
   view = st_get_texture_sampler_view_from_stobj(st, stObj, sampObj, 0);
} else {
   view = st_get_buffer_sampler_view_from_stobj(st, stObj);
}
 
return pipe->create_texture_handle(pipe, view, );
 }
 
 
 static void
diff --git a/src/mesa/state_tracker/st_texture.h 
b/src/mesa/state_tracker/st_texture.h
index a6f6ee8..8448f4c 100644
--- a/src/mesa/state_tracker/st_texture.h
+++ b/src/mesa/state_tracker/st_texture.h
@@ -274,20 +274,21 @@ st_convert_image(const struct st_context *st, const 
struct gl_image_unit *u,
 
 void
 st_convert_image_from_unit(const struct st_context *st,
struct pipe_image_view *img,
GLuint imgUnit);
 
 void
 st_convert_sampler(const struct st_context *st,
const struct gl_texture_object *texobj,
const struct gl_sampler_object *msamp,
+   float tex_unit_lod_bias,
struct pipe_sampler_state *sampler);
 
 void
 st_convert_sampler_from_unit(const struct st_context *st,
  struct pipe_sampler_state *sampler,
  GLuint texUnit);
 
 void
 st_update_single_texture(struct st_context *st,
  struct pipe_sampler_view **sampler_view,
-- 
2.7.4

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Re: [Mesa-dev] [PATCH] genxml: Remove a redundant identical code for different branches

[Jason Ekstrand]

Does the redundancy ends up mattering in any way?  A decent optimizing 
compiler should easily be able to get rid of that for you.


--Jason


On July 25, 2017 2:51:31 AM Gwan-gyeong Mun  wrote:


Before, it generates functions like this,

static inline uint32_t ATTRIBUTE_PURE
RENDER_SURFACE_STATE_RedClearColor_start(const struct gen_device_info *devinfo)
{
   switch (devinfo->gen) {
   case 10: return 384;
   case 9: return 384;
   case 8: return 255;
   case 7:
  if (devinfo->is_haswell) {
 return 255;
  } else {
 return 255;
  }
   case 6: return 0;
   case 5: return 0;
   case 4:
  if (devinfo->is_g4x) {
 return 0;
  } else {
 return 0;
  }
   default:
  unreachable("Invalid hardware generation");
   }
}

After, it generates fuctions without a redundant identical code for different
branches.

static inline uint32_t ATTRIBUTE_PURE
RENDER_SURFACE_STATE_RedClearColor_start(const struct gen_device_info *devinfo)
{
   switch (devinfo->gen) {
   case 10: return 384;
   case 9: return 384;
   case 8: return 255;
   case 7: return 255;
   case 6: return 0;
   case 5: return 0;
   case 4: return 0;
   default:
  unreachable("Invalid hardware generation");
   }
}

Signed-off-by: Mun Gwan-gyeong 
---
 src/intel/genxml/gen_bits_header.py | 8 
 1 file changed, 8 insertions(+)

diff --git a/src/intel/genxml/gen_bits_header.py 
b/src/intel/genxml/gen_bits_header.py

index 1b3504073b..8084facdb7 100644
--- a/src/intel/genxml/gen_bits_header.py
+++ b/src/intel/genxml/gen_bits_header.py
@@ -83,20 +83,28 @@ ${item.token_name}_${prop}(const struct gen_device_info 
*devinfo)

case 10: return ${item.get_prop(prop, 10)};
case 9: return ${item.get_prop(prop, 9)};
case 8: return ${item.get_prop(prop, 8)};
+% if item.get_prop(prop, 7) == item.get_prop(prop, 7.5):
+   case 7: return ${item.get_prop(prop, 7)};
+% else:
case 7:
   if (devinfo->is_haswell) {
  return ${item.get_prop(prop, 7.5)};
   } else {
  return ${item.get_prop(prop, 7)};
   }
+% endif
case 6: return ${item.get_prop(prop, 6)};
case 5: return ${item.get_prop(prop, 5)};
+% if item.get_prop(prop, 4) == item.get_prop(prop, 4.5):
+   case 4: return ${item.get_prop(prop, 4)};
+% else:
case 4:
   if (devinfo->is_g4x) {
  return ${item.get_prop(prop, 4.5)};
   } else {
  return ${item.get_prop(prop, 4)};
   }
+% endif
default:
   unreachable("Invalid hardware generation");
}
--
2.13.3




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Re: [Mesa-dev] [PATCH 1/2] mesa: add bind_program_pipeline() helper

[Samuel Pitoiset]

On 07/25/2017 04:54 PM, Nicolai Hähnle wrote:

On 25.07.2017 15:44, Ilia Mirkin wrote:

On Tue, Jul 25, 2017 at 9:09 AM, Samuel Pitoiset
 wrote:



On 07/25/2017 03:08 PM, Brian Paul wrote:


On 07/25/2017 02:04 AM, Nicolai Hähnle wrote:


On 21.07.2017 15:16, Samuel Pitoiset wrote:


To reduce code duplication.

Signed-off-by: Samuel Pitoiset 
---
   src/mesa/main/pipelineobj.c | 62
++---
   1 file changed, 25 insertions(+), 37 deletions(-)

diff --git a/src/mesa/main/pipelineobj.c 
b/src/mesa/main/pipelineobj.c

index f4008c..79d97c2211 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -429,44 +429,11 @@ _mesa_ActiveShaderProgram(GLuint pipeline,
GLuint program)
  _mesa_reference_shader_program(ctx, >ActiveProgram, 
shProg);

   }
-void GLAPIENTRY
-_mesa_BindProgramPipeline_no_error(GLuint pipeline)
-{
-   GET_CURRENT_CONTEXT(ctx);
-   struct gl_pipeline_object *newObj = NULL;
-
-   /* Rebinding the same pipeline object: no change.
-*/
-   if (ctx->_Shader->Name == pipeline)
-  return;
-
-   /* Get pointer to new pipeline object (newObj)
-*/
-   if (pipeline) {
-  /* non-default pipeline object */
-  newObj = _mesa_lookup_pipeline_object(ctx, pipeline);
-
-  /* Object is created by any Pipeline call but
glGenProgramPipelines,
-   * glIsProgramPipeline and GetProgramPipelineInfoLog
-   */
-  newObj->EverBound = GL_TRUE;
-   }
-
-   _mesa_bind_pipeline(ctx, newObj);
-}
-
-/**
- * Make program of the pipeline current
- */
-void GLAPIENTRY
-_mesa_BindProgramPipeline(GLuint pipeline)
+static ALWAYS_INLINE void
+bind_program_pipeline(struct gl_context *ctx, GLuint pipeline, bool
no_error)
   {
-   GET_CURRENT_CONTEXT(ctx);
  struct gl_pipeline_object *newObj = NULL;
-   if (MESA_VERBOSE & VERBOSE_API)
-  _mesa_debug(ctx, "glBindProgramPipeline(%u)\n", pipeline);



Personally, I would leave the debug print here instead of moving 
it. In
release builds it is compiled away anyway. An analogous comment 
applies

to the second patch.



I think the whole MESA_VERBOSE stuff could be removed, actually. 
Nowadays
we have apitrace to log/examine API calls.  I haven't used 
MESA_VERBOSE in

years.  Anyone else?



I don't use it either, but I remember someone else attempted to 
remove it

(maybe Emil?), without success.


I've used it on rare occasions, although it's a lot less helpful than
it might be. I think ultimately it's done in the wrong place. If we
want such a thing, it should hook into the dispatch logic and
automated.


Yeah, with all those no_error changes, it seems we're repeating this 
discussion every few months ;)


I'd be willing to review patches that move this into auto-generated 
dispatch logic.


Yeah, that seems better. I will think about this. :)

Samuel.



Cheers,
Nicolai

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Re: [Mesa-dev] [PATCH 1/3] mesa: don't try to re-generate the default buffer

[Samuel Pitoiset]

We could also remove that useless assert in 
_mesa_handle_bind_buffer_gen() because NewBufferObj() is called when the 
shared state is allocated. I don't think it can be NULL here. :-)


The same change can be applied to bind_buffer_range() though.

With that fixed, series is:

Reviewed-by: Samuel Pitoiset 

On 07/25/2017 04:11 PM, Timothy Arceri wrote:

It should have been created by this point.
---
  src/mesa/main/bufferobj.c | 6 +++---
  1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 419972e..e9bb492 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -4139,10 +4139,10 @@ _mesa_BindBufferBase(GLenum target, GLuint index, 
GLuint buffer)
bufObj = ctx->Shared->NullBufferObj;
 } else {
bufObj = _mesa_lookup_bufferobj(ctx, buffer);
+  if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
+, "glBindBufferBase"))
+ return;
 }
-   if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
- , "glBindBufferBase"))
-  return;
  
 if (!bufObj) {

_mesa_error(ctx, GL_INVALID_OPERATION,


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Re: [Mesa-dev] [PATCH v2] st/dri: add 32-bit RGBX/RGBA formats

[Emil Velikov]

On 25 July 2017 at 03:46, Chih-Wei Huang  wrote:
> On Tue 11 Jul 2017, Rob Herring wrote:
>>> From: Marek Olšák 
>>>
>>> Add support for 32-bit RGBX/RGBA formats which are required for Android.
>>>
>>> The original patch (commit ccdcf91104a5) was reverted (commit
>>> c0c6ca40a25e) in mesa as it broke GLX resulting in swapped colors. Based
>>> on further investigation by Chad Versace, moving the RGBX/RGBA configs
>>> to the end is enough to prevent breaking GLX.
>>>
>>> The handling of RGBA/RGBX in dri_fill_st_visual is a fix from Marek
>>> Olšák.
>>>
>>> Cc: Eric Anholt 
>>> Cc: Chad Versace 
>>> Cc: Mauro Rossi 
>>> Reviewed-by: Marek Olšák 
>>> Signed-off-by: Rob Herring 
>>> ---
>>> v2:
>>> - Incorporated dri_fill_st_visual RGBA/X handling from Marek
>>> - Handle RGBA/X in dri2_drawable_get_buffers for completeness
>
> Hi Rob,
> I'm testing this patch with your gbm_gralloc and mesa 17.1.5.
> Before applying this patch, the SurfaceFlinger sees
> the alpha=8 in RenderEngine::chooseEglConfig()
>
May want to check for patches in the Android EGL (meta) library.
I think, in does/did have a handful of workarounds.

Is the Android-x86 one in sync with the one RobH uses?

If there's some problems, I'd check that first.

-Emil
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Re: [Mesa-dev] [PATCH 1/2] mesa: add bind_program_pipeline() helper

[Nicolai Hähnle]

On 25.07.2017 15:44, Ilia Mirkin wrote:

On Tue, Jul 25, 2017 at 9:09 AM, Samuel Pitoiset
 wrote:



On 07/25/2017 03:08 PM, Brian Paul wrote:


On 07/25/2017 02:04 AM, Nicolai Hähnle wrote:


On 21.07.2017 15:16, Samuel Pitoiset wrote:


To reduce code duplication.

Signed-off-by: Samuel Pitoiset 
---
   src/mesa/main/pipelineobj.c | 62
++---
   1 file changed, 25 insertions(+), 37 deletions(-)

diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
index f4008c..79d97c2211 100644
--- a/src/mesa/main/pipelineobj.c
+++ b/src/mesa/main/pipelineobj.c
@@ -429,44 +429,11 @@ _mesa_ActiveShaderProgram(GLuint pipeline,
GLuint program)
  _mesa_reference_shader_program(ctx, >ActiveProgram, shProg);
   }
-void GLAPIENTRY
-_mesa_BindProgramPipeline_no_error(GLuint pipeline)
-{
-   GET_CURRENT_CONTEXT(ctx);
-   struct gl_pipeline_object *newObj = NULL;
-
-   /* Rebinding the same pipeline object: no change.
-*/
-   if (ctx->_Shader->Name == pipeline)
-  return;
-
-   /* Get pointer to new pipeline object (newObj)
-*/
-   if (pipeline) {
-  /* non-default pipeline object */
-  newObj = _mesa_lookup_pipeline_object(ctx, pipeline);
-
-  /* Object is created by any Pipeline call but
glGenProgramPipelines,
-   * glIsProgramPipeline and GetProgramPipelineInfoLog
-   */
-  newObj->EverBound = GL_TRUE;
-   }
-
-   _mesa_bind_pipeline(ctx, newObj);
-}
-
-/**
- * Make program of the pipeline current
- */
-void GLAPIENTRY
-_mesa_BindProgramPipeline(GLuint pipeline)
+static ALWAYS_INLINE void
+bind_program_pipeline(struct gl_context *ctx, GLuint pipeline, bool
no_error)
   {
-   GET_CURRENT_CONTEXT(ctx);
  struct gl_pipeline_object *newObj = NULL;
-   if (MESA_VERBOSE & VERBOSE_API)
-  _mesa_debug(ctx, "glBindProgramPipeline(%u)\n", pipeline);



Personally, I would leave the debug print here instead of moving it. In
release builds it is compiled away anyway. An analogous comment applies
to the second patch.



I think the whole MESA_VERBOSE stuff could be removed, actually. Nowadays
we have apitrace to log/examine API calls.  I haven't used MESA_VERBOSE in
years.  Anyone else?



I don't use it either, but I remember someone else attempted to remove it
(maybe Emil?), without success.


I've used it on rare occasions, although it's a lot less helpful than
it might be. I think ultimately it's done in the wrong place. If we
want such a thing, it should hook into the dispatch logic and
automated.


Yeah, with all those no_error changes, it seems we're repeating this 
discussion every few months ;)


I'd be willing to review patches that move this into auto-generated 
dispatch logic.


Cheers,
Nicolai
--
Lerne, wie die Welt wirklich ist,
Aber vergiss niemals, wie sie sein sollte.
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[Mesa-dev] [PATCH] radeonsi: fix detection of DRAW_INDIRECT_MULTI on SI

[Nicolai Hähnle]

From: Nicolai Hähnle 

The firmware version numbers for SI were wrong. The new numbers are probably
too conservative (we don't have a definitive answer by the firmware team),
but DRAW_INDIRECT_MULTI has been confirmed to work with these versions on
Tahiti (by Gustaw) and on Verde (by myself).

While this is technically adding a feature, it's a feature we thought we had
for a long time. The change is small enough and we're early enough in the 17.2
release cycle that it should still go in.

Reported-by: Gustaw Smolarczyk 
Cc: 17.2 
---
 src/gallium/drivers/radeonsi/si_pipe.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 0bc3002..2b0f9d3 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1002,8 +1002,8 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 sscreen->b.info.pfp_fw_version >= 211 &&
 sscreen->b.info.me_fw_version >= 173) ||
(sscreen->b.chip_class == SI &&
-sscreen->b.info.pfp_fw_version >= 121 &&
-sscreen->b.info.me_fw_version >= 87);
+sscreen->b.info.pfp_fw_version >= 79 &&
+sscreen->b.info.me_fw_version >= 142);
 
sscreen->has_ds_bpermute = sscreen->b.chip_class >= VI;
sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 
&&
-- 
2.9.3

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Re: [Mesa-dev] [EGL android: accquire fence implementation 1/2] i965: Return the last fence if the batch buffer is empty and nothing to be flushed when _intel_batchbuffer_flush_fence.

[Emil Velikov]

Hi Zhongmin,

Is the issue resolved by the EGL patch alone? Worth sticking with that for now?

I think this patch will cause some noticeable overhead - see below for details.


On 21 July 2017 at 04:08, Zhongmin Wu  wrote:
> Always save the last fence in the brw context when flushing
> buffer. If the buffer is nothing to be flushed, then return
> the last fence when asked for.
>
> Change-Id: Ic47035bcd1a27e402609afd9e2d1e3972548b97d
> Signed-off-by: Zhongmin Wu 
> ---
>  src/mesa/drivers/dri/i965/brw_context.c   |5 +
>  src/mesa/drivers/dri/i965/brw_context.h   |1 +
>  src/mesa/drivers/dri/i965/intel_batchbuffer.c |   16 ++--
>  3 files changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/src/mesa/drivers/dri/i965/brw_context.c 
> b/src/mesa/drivers/dri/i965/brw_context.c
> index 5433f90..ed0b056 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.c
> +++ b/src/mesa/drivers/dri/i965/brw_context.c
> @@ -1086,6 +1086,8 @@ brwCreateContext(gl_api api,
> ctx->VertexProgram._MaintainTnlProgram = true;
> ctx->FragmentProgram._MaintainTexEnvProgram = true;
>
> +   brw->out_fence_fd = -1;
> +
> brw_draw_init( brw );
>
> if ((flags & __DRI_CTX_FLAG_DEBUG) != 0) {
> @@ -1169,6 +1171,9 @@ intelDestroyContext(__DRIcontext * driContextPriv)
> brw->throttle_batch[1] = NULL;
> brw->throttle_batch[0] = NULL;
>
> +   if (brw->out_fence_fd >= 0)
> +  close(brw->out_fence_fd);
> +
> driDestroyOptionCache(>optionCache);
>
> /* free the Mesa context */
> diff --git a/src/mesa/drivers/dri/i965/brw_context.h 
> b/src/mesa/drivers/dri/i965/brw_context.h
> index dc4bc8f..692ea2c 100644
> --- a/src/mesa/drivers/dri/i965/brw_context.h
> +++ b/src/mesa/drivers/dri/i965/brw_context.h
> @@ -1217,6 +1217,7 @@ struct brw_context
>
> __DRIcontext *driContext;
> struct intel_screen *screen;
> +   int out_fence_fd;
>  };
>
>  /* brw_clear.c */
> diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c 
> b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> index 62d2fe8..d342e5d 100644
> --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
> @@ -648,9 +648,18 @@ do_flush_locked(struct brw_context *brw, int 
> in_fence_fd, int *out_fence_fd)
>   /* Add the batch itself to the end of the validation list */
>   add_exec_bo(batch, batch->bo);
>
> + if (brw->out_fence_fd >= 0) {
> +close(brw->out_fence_fd);
> +brw->out_fence_fd = -1;
> + }
> +
> + int fd = -1;
>   ret = execbuffer(dri_screen->fd, batch, hw_ctx,
>4 * USED_BATCH(*batch),
> -  in_fence_fd, out_fence_fd, flags);
> +  in_fence_fd, , flags);
execbuffer() creates an out fence if the "out_fence_fd" pointer is non-NULL.
Hence with this patch we'will create a fence for each
_intel_batchbuffer_flush_fence() invocation...

Not sure how costly that will be though :-\

-Emil
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[Mesa-dev] [PATCH] radeonsi/gfx9: reduce max threads per block to 1024 on gfx9+

[Nicolai Hähnle]

From: Nicolai Hähnle 

The number of supported waves per thread group has been officially
reduced to 16 with gfx9 (and trying to use 32 waves causes hangs).

Cc: mesa-sta...@lists.freedesktop.org
---
 src/gallium/drivers/radeon/r600_pipe_common.c | 39 ---
 1 file changed, 24 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeon/r600_pipe_common.c 
b/src/gallium/drivers/radeon/r600_pipe_common.c
index fd67d9a..cc52d6b 100644
--- a/src/gallium/drivers/radeon/r600_pipe_common.c
+++ b/src/gallium/drivers/radeon/r600_pipe_common.c
@@ -1024,6 +1024,25 @@ const char *r600_get_llvm_processor_name(enum 
radeon_family family)
}
 }
 
+static unsigned get_max_threads_per_block(struct r600_common_screen *screen,
+ enum pipe_shader_ir ir_type)
+{
+   if (ir_type != PIPE_SHADER_IR_TGSI)
+   return 256;
+
+   /* Only 16 waves per thread-group on gfx9. */
+   if (screen->chip_class >= GFX9)
+   return 1024;
+
+   /* Up to 40 waves per thread-group on GCN < gfx9. Expose a nice
+* round number.
+*/
+   if (screen->chip_class >= SI)
+   return 2048;
+
+   return 256;
+}
+
 static int r600_get_compute_param(struct pipe_screen *screen,
 enum pipe_shader_ir ir_type,
 enum pipe_compute_cap param,
@@ -1078,27 +1097,17 @@ static int r600_get_compute_param(struct pipe_screen 
*screen,
case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE:
if (ret) {
uint64_t *block_size = ret;
-   if (rscreen->chip_class >= SI &&
-   ir_type == PIPE_SHADER_IR_TGSI) {
-   block_size[0] = 2048;
-   block_size[1] = 2048;
-   block_size[2] = 2048;
-   } else {
-   block_size[0] = 256;
-   block_size[1] = 256;
-   block_size[2] = 256;
-   }
+   unsigned threads_per_block = 
get_max_threads_per_block(rscreen, ir_type);
+   block_size[0] = threads_per_block;
+   block_size[1] = threads_per_block;
+   block_size[2] = threads_per_block;
}
return 3 * sizeof(uint64_t);
 
case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK:
if (ret) {
uint64_t *max_threads_per_block = ret;
-   if (rscreen->chip_class >= SI &&
-   ir_type == PIPE_SHADER_IR_TGSI)
-   *max_threads_per_block = 2048;
-   else
-   *max_threads_per_block = 256;
+   *max_threads_per_block = 
get_max_threads_per_block(rscreen, ir_type);
}
return sizeof(uint64_t);
case PIPE_COMPUTE_CAP_ADDRESS_BITS:
-- 
2.9.3

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[Mesa-dev] [PATCH] st/va: change frame_idx from array to hash table

[Julien Isorce]

The picture_is was assumed to be a frame number so in 0-31.
But the vaapi client gstreamer-vaapi uses the surfaces handles
as identifier which are unsigned int.

This bug can happen when using a lot of vaapi surfaces within
the same process. Indeed Mesa/st/va increments a counter for the
surface ID: mesa/util/u_handle_table.c::handle_table_add which
starts from 0 and incremented by 1 at each call.
So when creating above 32 surfaces it was a problem.

The following bug contains a test that reproduces the problem
by running a couple of vaapih264enc in the same process. The above
also explains why there was no pb when running them in separated
processes.

https://bugzilla.gnome.org/show_bug.cgi?id=785085
---
 src/gallium/include/pipe/p_video_state.h   |  4 +++-
 src/gallium/state_trackers/va/context.c|  9 +++--
 src/gallium/state_trackers/va/picture.c| 11 ---
 src/gallium/state_trackers/va/va_private.h | 13 +
 4 files changed, 31 insertions(+), 6 deletions(-)

diff --git a/src/gallium/include/pipe/p_video_state.h 
b/src/gallium/include/pipe/p_video_state.h
index 39b3905..53f9ab3 100644
--- a/src/gallium/include/pipe/p_video_state.h
+++ b/src/gallium/include/pipe/p_video_state.h
@@ -32,6 +32,7 @@
 #include "pipe/p_format.h"
 #include "pipe/p_state.h"
 #include "pipe/p_screen.h"
+#include "util/u_hash_table.h"
 #include "util/u_inlines.h"
 
 #ifdef __cplusplus
@@ -407,7 +408,8 @@ struct pipe_h264_enc_picture_desc
bool not_referenced;
bool is_idr;
bool enable_vui;
-   unsigned int frame_idx[32];
+   struct util_hash_table *frame_idx;
+
 };
 
 struct pipe_h265_sps
diff --git a/src/gallium/state_trackers/va/context.c 
b/src/gallium/state_trackers/va/context.c
index 186f5066..f2cb37a 100644
--- a/src/gallium/state_trackers/va/context.c
+++ b/src/gallium/state_trackers/va/context.c
@@ -280,8 +280,10 @@ vlVaCreateContext(VADriverContextP ctx, VAConfigID 
config_id, int picture_width,
 
context->desc.base.profile = config->profile;
context->desc.base.entry_point = config->entrypoint;
-   if (config->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE)
+   if (config->entrypoint == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
   context->desc.h264enc.rate_ctrl.rate_ctrl_method = config->rc;
+  context->desc.h264enc.frame_idx = util_hash_table_create(handle_hash, 
handle_compare);
+   }
 
mtx_lock(>mutex);
*context_id = handle_table_add(drv->htab, context);
@@ -308,7 +310,10 @@ vlVaDestroyContext(VADriverContextP ctx, VAContextID 
context_id)
}
 
if (context->decoder) {
-  if (context->desc.base.entry_point != PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+  if (context->desc.base.entry_point == PIPE_VIDEO_ENTRYPOINT_ENCODE) {
+ if (context->desc.h264enc.frame_idx)
+util_hash_table_destroy (context->desc.h264enc.frame_idx);
+  } else {
  if (u_reduce_video_profile(context->decoder->profile) ==
PIPE_VIDEO_FORMAT_MPEG4_AVC) {
 FREE(context->desc.h264.pps->sps);
diff --git a/src/gallium/state_trackers/va/picture.c 
b/src/gallium/state_trackers/va/picture.c
index 20fe750..338e090 100644
--- a/src/gallium/state_trackers/va/picture.c
+++ b/src/gallium/state_trackers/va/picture.c
@@ -427,7 +427,10 @@ handleVAEncPictureParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlV
 PIPE_USAGE_STREAM, 
coded_buf->size);
context->coded_buf = coded_buf;
 
-   context->desc.h264enc.frame_idx[h264->CurrPic.picture_id] = h264->frame_num;
+   util_hash_table_set(context->desc.h264enc.frame_idx,
+  UINT_TO_PTR(h264->CurrPic.picture_id),
+  UINT_TO_PTR(h264->frame_num));
+
if (context->desc.h264enc.is_idr)
   context->desc.h264enc.picture_type = PIPE_H264_ENC_PICTURE_TYPE_IDR;
else
@@ -455,11 +458,13 @@ handleVAEncSliceParameterBufferType(vlVaDriver *drv, 
vlVaContext *context, vlVaB
for (int i = 0; i < 32; i++) {
   if (h264->RefPicList0[i].picture_id != VA_INVALID_ID) {
  if (context->desc.h264enc.ref_idx_l0 == VA_INVALID_ID)
-context->desc.h264enc.ref_idx_l0 = 
context->desc.h264enc.frame_idx[h264->RefPicList0[i].picture_id];
+context->desc.h264enc.ref_idx_l0 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h264enc.frame_idx,
+  
UINT_TO_PTR(h264->RefPicList0[i].picture_id)));
   }
   if (h264->RefPicList1[i].picture_id != VA_INVALID_ID && h264->slice_type 
== 1) {
  if (context->desc.h264enc.ref_idx_l1 == VA_INVALID_ID)
-context->desc.h264enc.ref_idx_l1 = 
context->desc.h264enc.frame_idx[h264->RefPicList1[i].picture_id];
+context->desc.h264enc.ref_idx_l1 = 
PTR_TO_UINT(util_hash_table_get(context->desc.h264enc.frame_idx,
+  
UINT_TO_PTR(h264->RefPicList1[i].picture_id)));
   }
}
 
diff --git 

Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence for Android OS v4.2

[Marathe, Yogesh]

Emil, 

> -Original Message-
> From: Emil Velikov [mailto:emil.l.veli...@gmail.com]
> Sent: Tuesday, July 25, 2017 7:46 PM
> To: Wu, Zhongmin 
> Cc: ML mesa-dev ; Kondapally, Kalyan
> ; Marathe, Yogesh
> ; Antognolli, Rafael
> ; Gao, Shuo ; Tomasz Figa
> ; Chris Wilson ; Eric
> Engestrom ; Rob Herring ; Daniel
> Stone ; Varad Gautam
> ; Liu, Zhiquan ; Frank
> Binns ; Brendan King ;
> Martin Peres 
> Subject: Re: [PATCH 2/2] i965: Queue the buffer with a sync fence for Android
> OS v4.2
> 
> Hi Zhongmin,
> 
> Thanks you for the update. There's a couple of important comments -
> dri2_make_current + droid_window_enqueue_buffer.
> The rest is just nitpiks.
> 
> Tomasz, hats down for the immense help and guidance.
> 
> On the potential performance hit (due to the extra fence), I think we could do
> some tests before adding extra infra.
> No obvious benchmarks come to mind - any suggestions?
> 

Sorry to jump in, flatland is the one native application on android that tests 
this
explicitly. It gives time required to render one frame of particular resolution 
without
other services running. It’s a native app that comes with aosp. And we found 
this
issue just because of that.

App info - 
https://android.googlesource.com/platform/frameworks/native/+/master/cmds/flatland/README.txt
Bug - https://bugs.freedesktop.org/show_bug.cgi?id=101655

I already tested this patch set with android and I can see scores not being 
that great.
May be this is the one we can use to profile this or I can continue to profile 
based on
guidance here.

> On 25 July 2017 at 03:07, Zhongmin Wu  wrote:
> > Before we queued the buffer with a invalid fence (-1), it will make
> > some benchmarks failed to test such as flatland.
> >
> > Now we get the out fence during the flushing buffer and then pass it
> > to SurfaceFlinger in eglSwapbuffer function.
> >
> > v2: a) Also implement the fence in cancelBuffer.
> > b) The last sync fence is stored in drawable object
> >rather than brw context.
> > c) format clear.
> >
> > v3: a) Save the last fence fd in DRI Context object.
> > b) Return the last fence if the batch buffer is empty and
> >nothing to be flushed when _intel_batchbuffer_flush_fence
> > c) Add the new interface in vbtl to set the retrieve fence
> >
> > v3.1 a) close fd in the new vbtl interface on none Android platform
> >
> > v4: a) The last fence is saved in brw context.
> > b) The retrieve fd is for all the platform but not just Android
> > c) Add a uniform dri2 interface to initialize the surface.
> >
> > v4.1: a) make some changes of variable name.
> >   b) the patch is breaked into two patches.
> >
> > v4.2: a) Add a deinit interface for surface to clear the out fence
> >
> > Change-Id: Ided54d2e193cde73a6f0feb36ac1c0056e4958f2
> > Signed-off-by: Zhongmin Wu 
> > ---
> >  src/egl/drivers/dri2/egl_dri2.c |   51 
> > +++
> >  src/egl/drivers/dri2/egl_dri2.h |8 +
> >  src/egl/drivers/dri2/platform_android.c |   12 ---
> >  src/egl/drivers/dri2/platform_drm.c |3 +-
> >  src/egl/drivers/dri2/platform_surfaceless.c |3 +-
> >  src/egl/drivers/dri2/platform_wayland.c |3 +-
> >  src/egl/drivers/dri2/platform_x11.c |3 +-
> >  src/egl/drivers/dri2/platform_x11_dri3.c|3 +-
> >  8 files changed, 77 insertions(+), 9 deletions(-)
> >
> > diff --git a/src/egl/drivers/dri2/egl_dri2.c
> > b/src/egl/drivers/dri2/egl_dri2.c index 020a0bc..ffd3a8a 100644
> > --- a/src/egl/drivers/dri2/egl_dri2.c
> > +++ b/src/egl/drivers/dri2/egl_dri2.c
> > @@ -1307,6 +1307,32 @@ dri2_destroy_context(_EGLDriver *drv,
> _EGLDisplay *disp, _EGLContext *ctx)
> > return EGL_TRUE;
> >  }
> >
> > +EGLBoolean
> > +dri2_surf_init(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
> nit: s/dri2_surf_init/dri2_init_surface/
> 
> > +_EGLConfig *conf, const EGLint *attrib_list) {
> > +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> > +   dri2_surf->out_fence_fd = -1;
> > +   return _eglInitSurface(surf, dpy, type, conf, attrib_list); }
> > +
> > +static void
> > +dri2_surface_set_out_fence( _EGLSurface *surf, int fence_fd)
> nit: s/dri2_surface_set_out_fence/dri2_surface_set_out_fence_fd/
> 
> > +{
> > +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> > +   if (dri2_surf->out_fence_fd >=0)
> nit: space between = and 0
> 
> > +  close(dri2_surf->out_fence_fd);
> > +
> > +   dri2_surf->out_fence_fd = fence_fd; }
> > +
> > +void
> > 

Re: [Mesa-dev] [PATCH V3] i965 : Optimize atom state flag checks

[Marathe, Yogesh]

Hi Matt, Sorry for late reply, please see below.

> -Original Message-
> From: mesa-dev [mailto:mesa-dev-boun...@lists.freedesktop.org] On Behalf
> Of Matt Turner
> Sent: Saturday, July 22, 2017 12:12 AM
> To: Muthukumar, Aravindan 
> Cc: mesa-dev@lists.freedesktop.org; Marathe, Yogesh
> 
> Subject: Re: [Mesa-dev] [PATCH V3] i965 : Optimize atom state flag checks
> 
> On 07/21, aravindan.muthuku...@intel.com wrote:
> >From: Aravindan Muthukumar 
> >
> >This patch improves CPI Rate(Cycles per Instruction) and branch miss
> >predict for i965. The function check_state() was showing CPI retired rate.
> >
> >Performance stats with android:
> >- CPI retired lowered by 28% (lower is better)
> >- Branch missprediction lowered by 13% (lower is better)
> >- 3DMark improved by 2%
> >
> >The dissassembly doesn't show difference, although above results were
> >observed with patch.
> 

Yes this is true for V3 where we removed the function based on a review comment.

> If there's no difference in the assembly then whatever measurements you have
> taken must be noise.
>

No that's not guaranteed either. Lot of things still depend on how instructions 
are
aligned, sometimes even changing linking order gives different results where
disassemblies of individual functions remain same.
 
> I applied the patch and inspected brw_state_upload.o. There are assembly
> differences. I can produce the same assembly as this patch by just pulling 
> the if
> statement out of check_and_emit_atom() and into the caller. The replacement
> of check_state() with a macro is completely unnecessary.
> 
> 
> diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c
> b/src/mesa/drivers/dri/i965/brw_state_upload.c
> index acaa97ee7d..b163e1490d 100644
> --- a/src/mesa/drivers/dri/i965/brw_state_upload.c
> +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c
> @@ -439,14 +439,12 @@ merge_ctx_state(struct brw_context *brw,  }
> 
>  static inline void
> -check_and_emit_atom(struct brw_context *brw,
> -struct brw_state_flags *state,
> -const struct brw_tracked_state *atom)
> +emit_atom(struct brw_context *brw,
> +  struct brw_state_flags *state,
> +  const struct brw_tracked_state *atom)
>  {
> -   if (check_state(state, >dirty)) {
> -  atom->emit(brw);
> -  merge_ctx_state(brw, state);
> -   }
> +   atom->emit(brw);
> +   merge_ctx_state(brw, state);
>  }
> 
>  static inline void
> @@ -541,7 +539,9 @@ brw_upload_pipeline_state(struct brw_context *brw,
>const struct brw_tracked_state *atom = [i];
>struct brw_state_flags generated;
> 
> - check_and_emit_atom(brw, , atom);
> + if (check_state(, >dirty)) {
> +emit_atom(brw, , atom);
> + }
> 
>accumulate_state(, >dirty);
> 
> @@ -558,7 +558,9 @@ brw_upload_pipeline_state(struct brw_context *brw,
>for (i = 0; i < num_atoms; i++) {
>const struct brw_tracked_state *atom = [i];
> 
> - check_and_emit_atom(brw, , atom);
> + if (check_state(, >dirty)) {
> +emit_atom(brw, , atom);
> + }
>}
> }
> 
> 
> With that said, the assembly differences are not understandable to me.
> Why should extracting an if statement from a static inline function into the 
> caller
> of that function cause any difference whatsoever?

Agreed, it shouldn't in case of static inline.

> 
> I'm viewing the assembly differences with:
> 
> wdiff -n \
> -w $'\033[30;41m' -x $'\033[0m' \
> -y $'\033[30;42m' -z $'\033[0m' \
> <(objdump -d brw_state_upload.o.before | sed -e 's/^.*\t//') \
> <(objdump -d brw_state_upload.o.wtf| sed -e 's/^.*\t//') | less -R
> 
> and the only real difference is the movement of some call and jmp 
> instructions.
> 
> I cannot take the patch without some reasonable explanation for the change.

Ok I think this has been discussed already and we agree that there is no big 
visible difference
in disassembly which can be pointed out for improvement. Although, as you said 
this movement
of instructions can cause this. If with this patch instructions get cache 
aligned that too can show
improvement.  This is a busy function with bad CPI. Hence chosen for 
optimization. Branch miss
predict is another metric.  Do we want to consider all these or just 
disassembly?

Let me make one more attempt, we clearly see icache misses for 
brw_upload_pipeline_state also
reduced with patch against without patch. Do you think that too is noise with 
*.o.wtf?
I would be happy to learn if that's the case to understand all this better.

I believe there are two reasons why this should go in
1. It consistently benefits android (we are ok to rename it), helps reduce 
overhead
2. It doesn't harm other platforms

We are ok to drop it if above two claims can be negated with someone else other 
than us testing
this. Otherwise can you please reconsider?

Re: [Mesa-dev] [PATCH 2/2] i965: Queue the buffer with a sync fence for Android OS v4.2

[Emil Velikov]

Hi Zhongmin,

Thanks you for the update. There's a couple of important comments -
dri2_make_current + droid_window_enqueue_buffer.
The rest is just nitpiks.

Tomasz, hats down for the immense help and guidance.

On the potential performance hit (due to the extra fence), I think we
could do some tests before adding extra infra.
No obvious benchmarks come to mind - any suggestions?

On 25 July 2017 at 03:07, Zhongmin Wu  wrote:
> Before we queued the buffer with a invalid fence (-1), it will
> make some benchmarks failed to test such as flatland.
>
> Now we get the out fence during the flushing buffer and then pass
> it to SurfaceFlinger in eglSwapbuffer function.
>
> v2: a) Also implement the fence in cancelBuffer.
> b) The last sync fence is stored in drawable object
>rather than brw context.
> c) format clear.
>
> v3: a) Save the last fence fd in DRI Context object.
> b) Return the last fence if the batch buffer is empty and
>nothing to be flushed when _intel_batchbuffer_flush_fence
> c) Add the new interface in vbtl to set the retrieve fence
>
> v3.1 a) close fd in the new vbtl interface on none Android platform
>
> v4: a) The last fence is saved in brw context.
> b) The retrieve fd is for all the platform but not just Android
> c) Add a uniform dri2 interface to initialize the surface.
>
> v4.1: a) make some changes of variable name.
>   b) the patch is breaked into two patches.
>
> v4.2: a) Add a deinit interface for surface to clear the out fence
>
> Change-Id: Ided54d2e193cde73a6f0feb36ac1c0056e4958f2
> Signed-off-by: Zhongmin Wu 
> ---
>  src/egl/drivers/dri2/egl_dri2.c |   51 
> +++
>  src/egl/drivers/dri2/egl_dri2.h |8 +
>  src/egl/drivers/dri2/platform_android.c |   12 ---
>  src/egl/drivers/dri2/platform_drm.c |3 +-
>  src/egl/drivers/dri2/platform_surfaceless.c |3 +-
>  src/egl/drivers/dri2/platform_wayland.c |3 +-
>  src/egl/drivers/dri2/platform_x11.c |3 +-
>  src/egl/drivers/dri2/platform_x11_dri3.c|3 +-
>  8 files changed, 77 insertions(+), 9 deletions(-)
>
> diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
> index 020a0bc..ffd3a8a 100644
> --- a/src/egl/drivers/dri2/egl_dri2.c
> +++ b/src/egl/drivers/dri2/egl_dri2.c
> @@ -1307,6 +1307,32 @@ dri2_destroy_context(_EGLDriver *drv, _EGLDisplay 
> *disp, _EGLContext *ctx)
> return EGL_TRUE;
>  }
>
> +EGLBoolean
> +dri2_surf_init(_EGLSurface *surf, _EGLDisplay *dpy, EGLint type,
nit: s/dri2_surf_init/dri2_init_surface/

> +_EGLConfig *conf, const EGLint *attrib_list)
> +{
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +   dri2_surf->out_fence_fd = -1;
> +   return _eglInitSurface(surf, dpy, type, conf, attrib_list);
> +}
> +
> +static void
> +dri2_surface_set_out_fence( _EGLSurface *surf, int fence_fd)
nit: s/dri2_surface_set_out_fence/dri2_surface_set_out_fence_fd/

> +{
> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +   if (dri2_surf->out_fence_fd >=0)
nit: space between = and 0

> +  close(dri2_surf->out_fence_fd);
> +
> +   dri2_surf->out_fence_fd = fence_fd;
> +}
> +
> +void
> +dri2_surf_deinit(_EGLSurface *surf)
> +{
nit: s/dri2_surf_deinit/dri2_fini_surface/

> +   struct dri2_egl_surface *dri2_surf = dri2_egl_surface(surf);
> +   dri2_surface_set_out_fence(surf, -1);
> +}
> +
>  static EGLBoolean
>  dri2_destroy_surface(_EGLDriver *drv, _EGLDisplay *dpy, _EGLSurface *surf)
>  {
> @@ -1318,6 +1344,22 @@ dri2_destroy_surface(_EGLDriver *drv, _EGLDisplay 
> *dpy, _EGLSurface *surf)
> return dri2_dpy->vtbl->destroy_surface(drv, dpy, surf);
>  }
>
> +static void
> +dri2_surf_get_fence_fd(_EGLContext *ctx,
> +   _EGLDisplay *dpy, _EGLSurface *surf)
> +{
> +   struct dri2_egl_display *dri2_dpy = dri2_egl_display(dpy);
> +   int fence_fd = -1;
> +   __DRIcontext *dri_ctx = dri2_egl_context(ctx)->dri_context;
> +   void * fence = dri2_dpy->fence->create_fence_fd(dri_ctx, -1);
Add blank line between declarations and code.

> +   if (fence) {
> +  fence_fd = dri2_dpy->fence->get_fence_fd(dri2_dpy->dri_screen,
> +   fence);
> +  dri2_dpy->fence->destroy_fence(dri2_dpy->dri_screen, fence);
> +   }
> +   dri2_surface_set_out_fence(surf, fence_fd);
> +}
> +
>  /**
>   * Called via eglMakeCurrent(), drv->API.MakeCurrent().
>   */
> @@ -1352,8 +1394,11 @@ dri2_make_current(_EGLDriver *drv, _EGLDisplay *disp, 
> _EGLSurface *dsurf,
> rdraw = (rsurf) ? dri2_dpy->vtbl->get_dri_drawable(rsurf) : NULL;
> cctx = (dri2_ctx) ? dri2_ctx->dri_context : NULL;
>
> +   int fence_fd = -1;
Unused variable?

> if (old_ctx) {
>__DRIcontext *old_cctx = dri2_egl_context(old_ctx)->dri_context;
> +  if (old_dsurf)
> + dri2_surf_get_fence_fd(old_ctx, disp, old_dsurf);
Are you sure 

Re: [Mesa-dev] [PATCH 065/101] mesa: add KHR_no_error support to glDeleteBuffers()

[Timothy Arceri]

56-65:

Reviewed-by: Timothy Arceri 

I've just sent a small series to remove some extra error paths from here 
that I noticed while reviewing this [1]


[1] https://patchwork.freedesktop.org/series/27863/

On 22/07/17 03:40, Samuel Pitoiset wrote:

Signed-off-by: Samuel Pitoiset 
---
  src/mapi/glapi/gen/gl_API.xml | 2 +-
  src/mesa/main/bufferobj.c | 8 
  src/mesa/main/bufferobj.h | 3 +++
  3 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/src/mapi/glapi/gen/gl_API.xml b/src/mapi/glapi/gen/gl_API.xml
index 60505e57b9..6f4d02d07d 100644
--- a/src/mapi/glapi/gen/gl_API.xml
+++ b/src/mapi/glapi/gen/gl_API.xml
@@ -5062,7 +5062,7 @@
  
  
  
-

+
  
  
  
diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index a3b871f0ad..c698cc9213 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1404,6 +1404,14 @@ delete_buffers(struct gl_context *ctx, GLsizei n, const 
GLuint *ids)
  
  
  void GLAPIENTRY

+_mesa_DeleteBuffers_no_error(GLsizei n, const GLuint *ids)
+{
+   GET_CURRENT_CONTEXT(ctx);
+   delete_buffers(ctx, n, ids);
+}
+
+
+void GLAPIENTRY
  _mesa_DeleteBuffers(GLsizei n, const GLuint *ids)
  {
 GET_CURRENT_CONTEXT(ctx);
diff --git a/src/mesa/main/bufferobj.h b/src/mesa/main/bufferobj.h
index 662ceba8a6..69e8549818 100644
--- a/src/mesa/main/bufferobj.h
+++ b/src/mesa/main/bufferobj.h
@@ -162,6 +162,9 @@ void GLAPIENTRY
  _mesa_BindBuffer(GLenum target, GLuint buffer);
  
  void GLAPIENTRY

+_mesa_DeleteBuffers_no_error(GLsizei n, const GLuint * buffer);
+
+void GLAPIENTRY
  _mesa_DeleteBuffers(GLsizei n, const GLuint * buffer);
  
  void GLAPIENTRY



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[Mesa-dev] [PATCH 2/3] mesa: move static binding functions above _mesa_DeleteBuffers()

[Timothy Arceri]

---
 src/mesa/main/bufferobj.c | 412 +++---
 1 file changed, 205 insertions(+), 207 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index e9bb492..6ed2800 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1258,6 +1258,211 @@ _mesa_BindBuffer(GLenum target, GLuint buffer)
bind_buffer_object(ctx, bindTarget, buffer);
 }
 
+/**
+ * Binds a buffer object to an atomic buffer binding point.
+ *
+ * The caller is responsible for validating the offset,
+ * flushing the vertices and updating NewDriverState.
+ */
+static void
+set_atomic_buffer_binding(struct gl_context *ctx,
+  struct gl_atomic_buffer_binding *binding,
+  struct gl_buffer_object *bufObj,
+  GLintptr offset,
+  GLsizeiptr size)
+{
+   _mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
+
+   if (bufObj == ctx->Shared->NullBufferObj) {
+  binding->Offset = 0;
+  binding->Size = 0;
+   } else {
+  binding->Offset = offset;
+  binding->Size = size;
+  bufObj->UsageHistory |= USAGE_ATOMIC_COUNTER_BUFFER;
+   }
+}
+
+/**
+ * Binds a buffer object to a uniform buffer binding point.
+ *
+ * The caller is responsible for flushing vertices and updating
+ * NewDriverState.
+ */
+static void
+set_ubo_binding(struct gl_context *ctx,
+struct gl_uniform_buffer_binding *binding,
+struct gl_buffer_object *bufObj,
+GLintptr offset,
+GLsizeiptr size,
+GLboolean autoSize)
+{
+   _mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
+
+   binding->Offset = offset;
+   binding->Size = size;
+   binding->AutomaticSize = autoSize;
+
+   /* If this is a real buffer object, mark it has having been used
+* at some point as a UBO.
+*/
+   if (size >= 0)
+  bufObj->UsageHistory |= USAGE_UNIFORM_BUFFER;
+}
+
+/**
+ * Binds a buffer object to a shader storage buffer binding point.
+ *
+ * The caller is responsible for flushing vertices and updating
+ * NewDriverState.
+ */
+static void
+set_ssbo_binding(struct gl_context *ctx,
+ struct gl_shader_storage_buffer_binding *binding,
+ struct gl_buffer_object *bufObj,
+ GLintptr offset,
+ GLsizeiptr size,
+ GLboolean autoSize)
+{
+   _mesa_reference_buffer_object(ctx, >BufferObject, bufObj);
+
+   binding->Offset = offset;
+   binding->Size = size;
+   binding->AutomaticSize = autoSize;
+
+   /* If this is a real buffer object, mark it has having been used
+* at some point as a SSBO.
+*/
+   if (size >= 0)
+  bufObj->UsageHistory |= USAGE_SHADER_STORAGE_BUFFER;
+}
+
+/**
+ * Binds a buffer object to a uniform buffer binding point.
+ *
+ * Unlike set_ubo_binding(), this function also flushes vertices
+ * and updates NewDriverState.  It also checks if the binding
+ * has actually changed before updating it.
+ */
+static void
+bind_uniform_buffer(struct gl_context *ctx,
+GLuint index,
+struct gl_buffer_object *bufObj,
+GLintptr offset,
+GLsizeiptr size,
+GLboolean autoSize)
+{
+   struct gl_uniform_buffer_binding *binding =
+  >UniformBufferBindings[index];
+
+   if (binding->BufferObject == bufObj &&
+   binding->Offset == offset &&
+   binding->Size == size &&
+   binding->AutomaticSize == autoSize) {
+  return;
+   }
+
+   FLUSH_VERTICES(ctx, 0);
+   ctx->NewDriverState |= ctx->DriverFlags.NewUniformBuffer;
+
+   set_ubo_binding(ctx, binding, bufObj, offset, size, autoSize);
+}
+
+/**
+ * Binds a buffer object to a shader storage buffer binding point.
+ *
+ * Unlike set_ssbo_binding(), this function also flushes vertices
+ * and updates NewDriverState.  It also checks if the binding
+ * has actually changed before updating it.
+ */
+static void
+bind_shader_storage_buffer(struct gl_context *ctx,
+   GLuint index,
+   struct gl_buffer_object *bufObj,
+   GLintptr offset,
+   GLsizeiptr size,
+   GLboolean autoSize)
+{
+   struct gl_shader_storage_buffer_binding *binding =
+  >ShaderStorageBufferBindings[index];
+
+   if (binding->BufferObject == bufObj &&
+   binding->Offset == offset &&
+   binding->Size == size &&
+   binding->AutomaticSize == autoSize) {
+  return;
+   }
+
+   FLUSH_VERTICES(ctx, 0);
+   ctx->NewDriverState |= ctx->DriverFlags.NewShaderStorageBuffer;
+
+   set_ssbo_binding(ctx, binding, bufObj, offset, size, autoSize);
+}
+
+/**
+ * Bind a buffer object to a uniform block binding point.
+ * As above, but offset = 0.
+ */
+static void
+bind_buffer_base_uniform_buffer(struct gl_context *ctx,
+   GLuint index,
+   

[Mesa-dev] [PATCH 1/3] mesa: don't try to re-generate the default buffer

[Timothy Arceri]

It should have been created by this point.
---
 src/mesa/main/bufferobj.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 419972e..e9bb492 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -4139,10 +4139,10 @@ _mesa_BindBufferBase(GLenum target, GLuint index, 
GLuint buffer)
   bufObj = ctx->Shared->NullBufferObj;
} else {
   bufObj = _mesa_lookup_bufferobj(ctx, buffer);
+  if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
+, "glBindBufferBase"))
+ return;
}
-   if (!_mesa_handle_bind_buffer_gen(ctx, buffer,
- , "glBindBufferBase"))
-  return;
 
if (!bufObj) {
   _mesa_error(ctx, GL_INVALID_OPERATION,
-- 
2.9.4

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[Mesa-dev] [PATCH 3/3] mesa: call binding functions directly from glDeleteBuffers

[Timothy Arceri]

---
 src/mesa/main/bufferobj.c | 12 +---
 1 file changed, 9 insertions(+), 3 deletions(-)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 6ed2800..dc8df19 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -1536,14 +1536,18 @@ _mesa_DeleteBuffers(GLsizei n, const GLuint *ids)
  }
  for (j = 0; j < MAX_FEEDBACK_BUFFERS; j++) {
 if (ctx->TransformFeedback.CurrentObject->Buffers[j] == bufObj) {
-   _mesa_BindBufferBase( GL_TRANSFORM_FEEDBACK_BUFFER, j, 0 );
+   _mesa_bind_buffer_base_transform_feedback(ctx,
+   
ctx->TransformFeedback.CurrentObject,
+   j, ctx->Shared->NullBufferObj,
+   false);
 }
  }
 
  /* unbind UBO binding points */
  for (j = 0; j < ctx->Const.MaxUniformBufferBindings; j++) {
 if (ctx->UniformBufferBindings[j].BufferObject == bufObj) {
-   _mesa_BindBufferBase( GL_UNIFORM_BUFFER, j, 0 );
+   bind_buffer_base_uniform_buffer(ctx, j,
+   ctx->Shared->NullBufferObj);
 }
  }
 
@@ -1554,7 +1558,8 @@ _mesa_DeleteBuffers(GLsizei n, const GLuint *ids)
  /* unbind SSBO binding points */
  for (j = 0; j < ctx->Const.MaxShaderStorageBufferBindings; j++) {
 if (ctx->ShaderStorageBufferBindings[j].BufferObject == bufObj) {
-   _mesa_BindBufferBase(GL_SHADER_STORAGE_BUFFER, j, 0);
+   bind_buffer_base_shader_storage_buffer(ctx, j,
+
ctx->Shared->NullBufferObj);
 }
  }
 
@@ -1566,6 +1571,7 @@ _mesa_DeleteBuffers(GLsizei n, const GLuint *ids)
  for (j = 0; j < ctx->Const.MaxAtomicBufferBindings; j++) {
 if (ctx->AtomicBufferBindings[j].BufferObject == bufObj) {
_mesa_BindBufferBase( GL_ATOMIC_COUNTER_BUFFER, j, 0 );
+   bind_atomic_buffer(ctx, j, ctx->Shared->NullBufferObj, 0, 0);
 }
  }
 
-- 
2.9.4

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Re: [Mesa-dev] [PATCH v2] st/dri: add 32-bit RGBX/RGBA formats

[Rob Herring]

On Mon, Jul 24, 2017 at 9:46 PM, Chih-Wei Huang  wrote:
> On Tue 11 Jul 2017, Rob Herring wrote:
>>> From: Marek Olšák 
>>>
>>> Add support for 32-bit RGBX/RGBA formats which are required for Android.
>>>
>>> The original patch (commit ccdcf91104a5) was reverted (commit
>>> c0c6ca40a25e) in mesa as it broke GLX resulting in swapped colors. Based
>>> on further investigation by Chad Versace, moving the RGBX/RGBA configs
>>> to the end is enough to prevent breaking GLX.
>>>
>>> The handling of RGBA/RGBX in dri_fill_st_visual is a fix from Marek
>>> Olšák.
>>>
>>> Cc: Eric Anholt 
>>> Cc: Chad Versace 
>>> Cc: Mauro Rossi 
>>> Reviewed-by: Marek Olšák 
>>> Signed-off-by: Rob Herring 
>>> ---
>>> v2:
>>> - Incorporated dri_fill_st_visual RGBA/X handling from Marek
>>> - Handle RGBA/X in dri2_drawable_get_buffers for completeness
>
> Hi Rob,
> I'm testing this patch with your gbm_gralloc and mesa 17.1.5.
> Before applying this patch, the SurfaceFlinger sees
> the alpha=8 in RenderEngine::chooseEglConfig()
>
> 07-25 02:19:13.188  1125  1125 I SurfaceFlinger: EGL information: format=0x1
> 07-25 02:19:13.188  1125  1125 I SurfaceFlinger: vendor: Android
> 07-25 02:19:13.188  1125  1125 I SurfaceFlinger: version   : 1.4
> Android META-EGL
> 07-25 02:19:13.188  1125  1125 I SurfaceFlinger: extensions:
> EGL_KHR_get_all_proc_addresses EGL_ANDROID_presentation_time
> EGL_KHR_swap_buffers_with_damage EGL_ANDROID_create_native_cli
> ent_buffer EGL_ANDROID_front_buffer_auto_refresh EGL_KHR_image_base
> EGL_KHR_gl_texture_2D_image EGL_KHR_gl_texture_3D_image
> EGL_KHR_gl_texture_cubemap_image EGL_KHR_gl_renderbuffer_ima
> ge EGL_KHR_reusable_sync EGL_KHR_fence_sync EGL_KHR_create_context
> EGL_KHR_config_attribs EGL_KHR_surfaceless_context
> EGL_ANDROID_image_native_buffer EGL_KHR_wait_sync EGL_ANDROID_reco
> rdable EGL_EXT_buffer_age
> 07-25 02:19:13.188  1125  1125 I SurfaceFlinger: Client API: OpenGL_ES
> 07-25 02:19:13.188  1125  1125 I SurfaceFlinger: EGLSurface: 8-8-8-8,
> config=0xa5485880
>
>  (r-b-g-a)
> 07-25 02:19:13.211  1125  1125 I SurfaceFlinger: OpenGL ES
> informations: format=0x1
> 07-25 02:19:13.211  1125  1125 I SurfaceFlinger: vendor: Red Hat
> 07-25 02:19:13.211  1125  1125 I SurfaceFlinger: renderer  : Gallium
> 0.4 on virgl
> 07-25 02:19:13.211  1125  1125 I SurfaceFlinger: version   : OpenGL ES
> 3.0 Mesa 17.1.5 (git-317b5bd)
>
> After applying the patch, however, alpha becomes 0
>
> 07-25 02:34:46.522  1125  1125 I SurfaceFlinger: EGL information: format=0x1
> 07-25 02:34:46.522  1125  1125 I SurfaceFlinger: vendor: Android
> 07-25 02:34:46.522  1125  1125 I SurfaceFlinger: version   : 1.4
> Android META-EGL
> 07-25 02:34:46.522  1125  1125 I SurfaceFlinger: extensions:
> EGL_KHR_get_all_proc_addresses EGL_ANDROID_presentation_time
> EGL_KHR_swap_buffers_with_damage
> EGL_ANDROID_create_native_client_buffer
> EGL_ANDROID_front_buffer_auto_refresh EGL_KHR_image_base
> EGL_KHR_gl_texture_2D_image EGL_KHR_gl_texture_3D_image
> EGL_KHR_gl_texture_cubemap_image EGL_KHR_gl_renderbuffer_image
> EGL_KHR_reusable_sync EGL_KHR_fence_sync EGL_KHR_create_context
> EGL_KHR_config_attribs EGL_KHR_surfaceless_context
> EGL_ANDROID_image_native_buffer EGL_KHR_wait_sync
> EGL_ANDROID_recordable EGL_EXT_buffer_age
> 07-25 02:34:46.522  1125  1125 I SurfaceFlinger: Client API: OpenGL_ES
> 07-25 02:34:46.522  1125  1125 I SurfaceFlinger: EGLSurface: 8-8-8-0,
> config=0xabc24d80
>
> 
> 07-25 02:34:46.574  1125  1125 I SurfaceFlinger: OpenGL ES
> informations: format=0x1
> 07-25 02:34:46.574  1125  1125 I SurfaceFlinger: vendor: Red Hat
> 07-25 02:34:46.574  1125  1125 I SurfaceFlinger: renderer  : Gallium
> 0.4 on virgl
> 07-25 02:34:46.574  1125  1125 I SurfaceFlinger: version   : OpenGL ES
> 3.0 Mesa 17.1.5 (git-317b5bd)
>
>
> Therefore, eglCreateWindowSurface() finally chose
> HAL_PIXEL_FORMAT_RGBX_ instead of
> HAL_PIXEL_FORMAT_RGBA_.
> Is that expected?

Yes. I believe the client requested a config without alpha, so RGBX
satisfies that.

Do you observe any problems because of the change?

Rob
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Re: [Mesa-dev] [PATCH] radeon/vcn: move message buffer to vram for now

[Leo Liu]

On 07/25/2017 05:19 AM, Christian König wrote:

Am 25.07.2017 um 08:27 schrieb Michel Dänzer:

On 25/07/17 02:54 AM, Leo Liu wrote:

To workaround an unknown bug.

Signed-off-by: Leo Liu 
---
  src/gallium/drivers/radeon/radeon_vcn_dec.c | 3 ++-
  1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/gallium/drivers/radeon/radeon_vcn_dec.c 
b/src/gallium/drivers/radeon/radeon_vcn_dec.c

index bd93b849db..a60b969a27 100644
--- a/src/gallium/drivers/radeon/radeon_vcn_dec.c
+++ b/src/gallium/drivers/radeon/radeon_vcn_dec.c
@@ -1237,8 +1237,9 @@ struct pipe_video_codec 
*radeon_create_decoder(struct pipe_context *context,

  unsigned msg_fb_it_size = FB_BUFFER_OFFSET + FB_BUFFER_SIZE;
  if (have_it(dec))
  msg_fb_it_size += IT_SCALING_TABLE_SIZE;
+/* use vram to improve performance, workaround an unknown 
bug */
  if (!rvid_create_buffer(dec->screen, 
>msg_fb_it_buffers[i],

-msg_fb_it_size, PIPE_USAGE_STAGING)) {
+msg_fb_it_size, PIPE_USAGE_DEFAULT)) {
  RVID_ERR("Can't allocated message buffers.\n");
  goto error;
  }


Does PIPE_USAGE_STREAM help as well? That would be system memory but
with write-combined CPU access, whereas PIPE_USAGE_STAGING is cacheable.


No, unfortunately not. It's a hardware bug which is independent of the 
caching mode.


Leo can you limit this workaround to APUs? Shouldn't matter for dGPUs.


This change is on vcn_dec, and that is for Raven only now.



Additional to that I would rather like to have that in the kernel, so 
that we can easily remove it when the correct workaround from the 
hardware guys for this issue lands.


Do you mean disabling Gart Cacheable completely in kernel, and using 
VRAM globally instead? if that's the case, not sure if it would have 
side effect on other part of the driver.


On the current issue, Msg buffer and Bitstream buffer are both in Gart, 
but only Msg buffer affect the performance, since it interacts more 
often with GPU.



Leo



Christian.



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Re: [Mesa-dev] [PATCH 1/2] mesa: add bind_program_pipeline() helper

[Ilia Mirkin]

On Tue, Jul 25, 2017 at 9:09 AM, Samuel Pitoiset
 wrote:
>
>
> On 07/25/2017 03:08 PM, Brian Paul wrote:
>>
>> On 07/25/2017 02:04 AM, Nicolai Hähnle wrote:
>>>
>>> On 21.07.2017 15:16, Samuel Pitoiset wrote:

 To reduce code duplication.

 Signed-off-by: Samuel Pitoiset 
 ---
   src/mesa/main/pipelineobj.c | 62
 ++---
   1 file changed, 25 insertions(+), 37 deletions(-)

 diff --git a/src/mesa/main/pipelineobj.c b/src/mesa/main/pipelineobj.c
 index f4008c..79d97c2211 100644
 --- a/src/mesa/main/pipelineobj.c
 +++ b/src/mesa/main/pipelineobj.c
 @@ -429,44 +429,11 @@ _mesa_ActiveShaderProgram(GLuint pipeline,
 GLuint program)
  _mesa_reference_shader_program(ctx, >ActiveProgram, shProg);
   }
 -void GLAPIENTRY
 -_mesa_BindProgramPipeline_no_error(GLuint pipeline)
 -{
 -   GET_CURRENT_CONTEXT(ctx);
 -   struct gl_pipeline_object *newObj = NULL;
 -
 -   /* Rebinding the same pipeline object: no change.
 -*/
 -   if (ctx->_Shader->Name == pipeline)
 -  return;
 -
 -   /* Get pointer to new pipeline object (newObj)
 -*/
 -   if (pipeline) {
 -  /* non-default pipeline object */
 -  newObj = _mesa_lookup_pipeline_object(ctx, pipeline);
 -
 -  /* Object is created by any Pipeline call but
 glGenProgramPipelines,
 -   * glIsProgramPipeline and GetProgramPipelineInfoLog
 -   */
 -  newObj->EverBound = GL_TRUE;
 -   }
 -
 -   _mesa_bind_pipeline(ctx, newObj);
 -}
 -
 -/**
 - * Make program of the pipeline current
 - */
 -void GLAPIENTRY
 -_mesa_BindProgramPipeline(GLuint pipeline)
 +static ALWAYS_INLINE void
 +bind_program_pipeline(struct gl_context *ctx, GLuint pipeline, bool
 no_error)
   {
 -   GET_CURRENT_CONTEXT(ctx);
  struct gl_pipeline_object *newObj = NULL;
 -   if (MESA_VERBOSE & VERBOSE_API)
 -  _mesa_debug(ctx, "glBindProgramPipeline(%u)\n", pipeline);
>>>
>>>
>>> Personally, I would leave the debug print here instead of moving it. In
>>> release builds it is compiled away anyway. An analogous comment applies
>>> to the second patch.
>>
>>
>> I think the whole MESA_VERBOSE stuff could be removed, actually. Nowadays
>> we have apitrace to log/examine API calls.  I haven't used MESA_VERBOSE in
>> years.  Anyone else?
>
>
> I don't use it either, but I remember someone else attempted to remove it
> (maybe Emil?), without success.

I've used it on rare occasions, although it's a lot less helpful than
it might be. I think ultimately it's done in the wrong place. If we
want such a thing, it should hook into the dispatch logic and
automated.
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