Re: [Mesa-dev] [PATCH 1/7] egl: Support IMG_context_priority

[Tapani Pälli]

FYI I've tested this series using your 'preemption' branch on KBL and 
'egl-context-priority' test passes. The other Piglit test I sent 
('egl-context-priority-runtime') does not always pass but I think the 
problem is actually in the test itself, it's making assumptions that are 
not true. I will eventually try to get that working as well, it seems 
likely that it would require GL_TIMESTAMP query support though and for 
that I'd need to enable 'GL_EXT_disjoint_timer_query' first.



On 09/29/2017 01:25 PM, Chris Wilson wrote:

IMG_context_priority
https://www.khronos.org/registry/egl/extensions/IMG/EGL_IMG_context_priority.txt

 "This extension allows an EGLContext to be created with a priority
 hint. It is possible that an implementation will not honour the
 hint, especially if there are constraints on the number of high
 priority contexts available in the system, or system policy limits
 access to high priority contexts to appropriate system privilege
 level. A query is provided to find the real priority level assigned
 to the context after creation."

The extension adds a new eglCreateContext attribute for choosing a
priority hint. This stub parses the attribute and copies into the base
struct _egl_context, and hooks up the query similarly.

Since the attribute is purely a hint, I have no qualms about the lack of
implementation before reporting back the value the user gave!

v2: Remember to set the default ContextPriority value to medium.
v3: Use the driRendererQuery interface to probe the backend for
supported priority values and use those to mask the EGL interface.
v4: Treat the priority attrib as a hint and gracefully mask any requests
not supported by the driver, the EGLContext will remain at medium
priority.

Signed-off-by: Chris Wilson 
Cc: Rob Clark 
Reviewed-by: Ben Widawsky 
Reviewed-by: Emil Velikov 
Reviewed-by: Eric Engestrom 
---
  include/GL/internal/dri_interface.h |  8 +
  src/egl/drivers/dri2/egl_dri2.c |  5 
  src/egl/main/eglapi.c   |  2 ++
  src/egl/main/eglcontext.c   | 58 +
  src/egl/main/eglcontext.h   |  1 +
  src/egl/main/egldisplay.h   |  5 
  6 files changed, 79 insertions(+)

diff --git a/include/GL/internal/dri_interface.h 
b/include/GL/internal/dri_interface.h
index 783ff1c70d..bcc6a2e423 100644
--- a/include/GL/internal/dri_interface.h
+++ b/include/GL/internal/dri_interface.h
@@ -1765,6 +1765,14 @@ typedef struct __DRIDriverVtableExtensionRec {
   */
  #define __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB  0x000c
  
+/* Bitmaks of supported/available context priorities - must match

+ * __EGL_CONTEXT_PRIORITY_LOW_BIT et al
+ */
+#define __DRI2_RENDERER_HAS_CONTEXT_PRIORITY  0x000d
+#define   __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_LOW(1 << 0)
+#define   __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_MEDIUM (1 << 1)
+#define   __DRI2_RENDERER_HAS_CONTEXT_PRIORITY_HIGH   (1 << 2)
+
  typedef struct __DRI2rendererQueryExtensionRec __DRI2rendererQueryExtension;
  struct __DRI2rendererQueryExtensionRec {
 __DRIextension base;
diff --git a/src/egl/drivers/dri2/egl_dri2.c b/src/egl/drivers/dri2/egl_dri2.c
index adcaae0bab..e87144892e 100644
--- a/src/egl/drivers/dri2/egl_dri2.c
+++ b/src/egl/drivers/dri2/egl_dri2.c
@@ -666,6 +666,11 @@ dri2_setup_screen(_EGLDisplay *disp)
 disp->Extensions.KHR_no_config_context = EGL_TRUE;
 disp->Extensions.KHR_surfaceless_context = EGL_TRUE;
  
+   /* Report back to EGL the bitmask of priorities supported */

+   disp->Extensions.IMG_context_priority =
+  dri2_renderer_query_integer(dri2_dpy,
+  __DRI2_RENDERER_HAS_CONTEXT_PRIORITY);
+
 if (dri2_renderer_query_integer(dri2_dpy,
 __DRI2_RENDERER_HAS_FRAMEBUFFER_SRGB))
disp->Extensions.KHR_gl_colorspace = EGL_TRUE;
diff --git a/src/egl/main/eglapi.c b/src/egl/main/eglapi.c
index 4a9b3fe392..6d35ba5d7a 100644
--- a/src/egl/main/eglapi.c
+++ b/src/egl/main/eglapi.c
@@ -490,6 +490,8 @@ _eglCreateExtensionsString(_EGLDisplay *dpy)
 _EGL_CHECK_EXTENSION(EXT_image_dma_buf_import_modifiers);
 _EGL_CHECK_EXTENSION(EXT_swap_buffers_with_damage);
  
+   _EGL_CHECK_EXTENSION(IMG_context_priority);

+
 _EGL_CHECK_EXTENSION(KHR_cl_event2);
 _EGL_CHECK_EXTENSION(KHR_config_attribs);
 _EGL_CHECK_EXTENSION(KHR_create_context);
diff --git a/src/egl/main/eglcontext.c b/src/egl/main/eglcontext.c
index 1b03160439..8c64f9ab82 100644
--- a/src/egl/main/eglcontext.c
+++ b/src/egl/main/eglcontext.c
@@ -332,6 +332,60 @@ _eglParseContextAttribList(_EGLContext *ctx, _EGLDisplay 
*dpy,
   ctx->NoError = !!val;
   break;
  
+  case EGL_CONTEXT_PRIORITY_LEVEL_IMG:

+ /* The  EGL_IMG_context_priority spec says:
+  

Re: [Mesa-dev] [PATCH] radv: emit fmuladd instead of fma to llvm.

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

On 4 Oct 2017 04:11, "Dave Airlie"  wrote:

From: Dave Airlie 

For Vulkan SPIR-V the spec states
fma() Inherited from OpFMul followed by OpFAdd.

Matt says the backend will do the right thing depending on the
hardware being compiled for, if you use the fmuladd intrinsic.

Using the Mad Max pts test, on high settings at 4K:
CHP: 55->60
HGDD: 46->50
LM: 55->60
No change on Stronghold.

Thanks to Feral for spending the time to track this down.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_
llvm.c
index d7b6259..11ba487 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1707,7 +1707,7 @@ static void visit_alu(struct ac_nir_context *ctx,
const nir_alu_instr *instr)
  result);
break;
case nir_op_ffma:
-   result = emit_intrin_3f_param(>ac, "llvm.fma",
+   result = emit_intrin_3f_param(>ac, "llvm.fmuladd",
  ac_to_float_type(>ac,
def_type), src[0], src[1], src[2]);
break;
case nir_op_ibitfield_extract:
--
2.9.4

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Re: [Mesa-dev] [PATCH] Replace byte-swapping code with builtins in pack.c

[Matt Turner]

On Tue, Oct 3, 2017 at 11:01 AM, Jochen Rollwagen  wrote:
> From 4cebe50a9bade6717923e104c954f3fad75f71bb Mon Sep 17 00:00:00 2001
> From: Jochen Rollwagen 
> Date: Tue, 3 Oct 2017 19:54:10 +0200
> Subject: [PATCH] Replace byte-swapping code with builtins in pack.c
>
> This patch replaces some code for byte-swapping in pack.c with the builtin
> functions allowing the compiler to do its optimization magic
> ---
>  src/mesa/main/pack.c |   22 ++
>  1 file changed, 2 insertions(+), 20 deletions(-)
>
> diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
> index 94a6d28..9bfde39 100644
> --- a/src/mesa/main/pack.c
> +++ b/src/mesa/main/pack.c
> @@ -230,26 +230,8 @@ _mesa_pack_bitmap( GLint width, GLint height, const
> GLubyte
>  *source,
> }
>  }
>
> -
> -#define SWAP2BYTE(VALUE)\
> -   {\
> -  GLubyte *bytes = (GLubyte *) &(VALUE);\
> -  GLubyte tmp = bytes[0];\
> -  bytes[0] = bytes[1];\
> -  bytes[1] = tmp;\
> -   }
> -
> -#define SWAP4BYTE(VALUE)\
> -   {\
> -  GLubyte *bytes = (GLubyte *) &(VALUE);\
> -  GLubyte tmp = bytes[0];\
> -  bytes[0] = bytes[3];\
> -  bytes[3] = tmp;\
> -  tmp = bytes[1];\
> -  bytes[1] = bytes[2];\
> -  bytes[2] = tmp;\
> -   }
> -
> +#define SWAP2BYTE(VALUE) __builtin_bswap16(VALUE)
> +#define SWAP4BYTE(VALUE) __builtin_bswap32(VALUE)

In my experience it's much simpler to just write these as

   return ((x & 0xff) << 8) | ((x >> 8) & 0xff);

and

   return  ((x & 0xff) << 24) |
   ((x & 0xff00) << 8) |
   ((x & 0xff) >> 8) |
   ((x >> 24) & 0xff);

and not have to deal with compiler intrinsics. Compilers will
recognize these patterns and use the appropriate instructions (rol for
2-bytes and bswap for 4-bytes).

You should be able to count the numbers of those instructions before
and after such a patch to confirm it's working as expected.
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Re: [Mesa-dev] [PATCH v2 10/11] anv: enable multiple planes per image/imageView

[Lionel Landwerlin]

On 04/10/17 02:16, Jason Ekstrand wrote:


Ok, maybe I'm being a bit dense, but doesn't the aspect imply the 
plane?  Why can't we just use anv_image_aspect_to_plane here?  That 
would reduce the churn by a good bit.


                              enum isl_aux_usage aux_usage,
                              struct blorp_surf *blorp_surf)
 {
+   /* For the stencil surface aux_usage is always NONE. */
    if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT ||
        aux_usage == ISL_AUX_USAGE_HIZ)
       aux_usage = ISL_AUX_USAGE_NONE;


It was for that bit right here.
I need to check again, maybe this can go. I remember this triggered some 
failures.
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[Mesa-dev] [PATCH] radv: enable tc compatible htile for d32s8 also.

[Dave Airlie]

From: Dave Airlie 

This enables tc compatible htile for stencil surfaces as well.

This gives a 3-5fps boost on Mad Max on high@4k.

It also depends on Bas's tc-compat htile patch.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_image.c | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index bf30281..c017bf8 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -114,7 +114,8 @@ radv_init_surface(struct radv_device *device,
pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
pCreateInfo->mipLevels <= 1 &&
device->physical_device->rad_info.chip_class >= VI &&
-   (pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
+   ((pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
+ pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT) ||
 (device->physical_device->rad_info.chip_class >= GFX9 &&
  pCreateInfo->format == VK_FORMAT_D16_UNORM)))
surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
-- 
2.9.4

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Re: [Mesa-dev] [PATCH] Replace byte-swapping code with builtins in pack.c

[Brian Paul]

On 10/03/2017 12:01 PM, Jochen Rollwagen wrote:

 From 4cebe50a9bade6717923e104c954f3fad75f71bb Mon Sep 17 00:00:00 2001
From: Jochen Rollwagen 
Date: Tue, 3 Oct 2017 19:54:10 +0200
Subject: [PATCH] Replace byte-swapping code with builtins in pack.c

This patch replaces some code for byte-swapping in pack.c with the
builtin functions allowing the compiler to do its optimization magic
---
  src/mesa/main/pack.c |   22 ++
  1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
index 94a6d28..9bfde39 100644
--- a/src/mesa/main/pack.c
+++ b/src/mesa/main/pack.c
@@ -230,26 +230,8 @@ _mesa_pack_bitmap( GLint width, GLint height, const
GLubyte
  *source,
 }
  }

-
-#define SWAP2BYTE(VALUE)\
-   {\
-  GLubyte *bytes = (GLubyte *) &(VALUE);\
-  GLubyte tmp = bytes[0];\
-  bytes[0] = bytes[1];\
-  bytes[1] = tmp;\
-   }
-
-#define SWAP4BYTE(VALUE)\
-   {\
-  GLubyte *bytes = (GLubyte *) &(VALUE);\
-  GLubyte tmp = bytes[0];\
-  bytes[0] = bytes[3];\
-  bytes[3] = tmp;\
-  tmp = bytes[1];\
-  bytes[1] = bytes[2];\
-  bytes[2] = tmp;\
-   }
-
+#define SWAP2BYTE(VALUE) __builtin_bswap16(VALUE)
+#define SWAP4BYTE(VALUE) __builtin_bswap32(VALUE)


Looks like a gcc feature.  We also need to build with other compilers 
like Microsoft's.


-Brian



  static void
  extract_uint_indexes(GLuint n, GLuint indexes[],


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[Mesa-dev] [PATCH] Replace byte-swapping code with builtins in pack.c

[Jochen Rollwagen]

From 4cebe50a9bade6717923e104c954f3fad75f71bb Mon Sep 17 00:00:00 2001
From: Jochen Rollwagen 
Date: Tue, 3 Oct 2017 19:54:10 +0200
Subject: [PATCH] Replace byte-swapping code with builtins in pack.c

This patch replaces some code for byte-swapping in pack.c with the 
builtin functions allowing the compiler to do its optimization magic

---
 src/mesa/main/pack.c |   22 ++
 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
index 94a6d28..9bfde39 100644
--- a/src/mesa/main/pack.c
+++ b/src/mesa/main/pack.c
@@ -230,26 +230,8 @@ _mesa_pack_bitmap( GLint width, GLint height, const 
GLubyte

 *source,
}
 }

-
-#define SWAP2BYTE(VALUE)\
-   {\
-  GLubyte *bytes = (GLubyte *) &(VALUE);\
-  GLubyte tmp = bytes[0];\
-  bytes[0] = bytes[1];\
-  bytes[1] = tmp;\
-   }
-
-#define SWAP4BYTE(VALUE)\
-   {\
-  GLubyte *bytes = (GLubyte *) &(VALUE);\
-  GLubyte tmp = bytes[0];\
-  bytes[0] = bytes[3];\
-  bytes[3] = tmp;\
-  tmp = bytes[1];\
-  bytes[1] = bytes[2];\
-  bytes[2] = tmp;\
-   }
-
+#define SWAP2BYTE(VALUE) __builtin_bswap16(VALUE)
+#define SWAP4BYTE(VALUE) __builtin_bswap32(VALUE)

 static void
 extract_uint_indexes(GLuint n, GLuint indexes[],
--
1.7.9.5

>From 4cebe50a9bade6717923e104c954f3fad75f71bb Mon Sep 17 00:00:00 2001
From: Jochen Rollwagen 
Date: Tue, 3 Oct 2017 19:54:10 +0200
Subject: [PATCH] Replace byte-swapping code with builtins in pack.c

This patch replaces some code for byte-swapping in pack.c with the builtin functions
allowing the compiler to do its optimization magic
---
 src/mesa/main/pack.c |   22 ++
 1 file changed, 2 insertions(+), 20 deletions(-)

diff --git a/src/mesa/main/pack.c b/src/mesa/main/pack.c
index 94a6d28..9bfde39 100644
--- a/src/mesa/main/pack.c
+++ b/src/mesa/main/pack.c
@@ -230,26 +230,8 @@ _mesa_pack_bitmap( GLint width, GLint height, const GLubyte *source,
}
 }
 
-
-#define SWAP2BYTE(VALUE)			\
-   {		\
-  GLubyte *bytes = (GLubyte *) &(VALUE);	\
-  GLubyte tmp = bytes[0];			\
-  bytes[0] = bytes[1];			\
-  bytes[1] = tmp;\
-   }
-
-#define SWAP4BYTE(VALUE)			\
-   {		\
-  GLubyte *bytes = (GLubyte *) &(VALUE);	\
-  GLubyte tmp = bytes[0];			\
-  bytes[0] = bytes[3];			\
-  bytes[3] = tmp;\
-  tmp = bytes[1];\
-  bytes[1] = bytes[2];			\
-  bytes[2] = tmp;\
-   }
-
+#define SWAP2BYTE(VALUE) __builtin_bswap16(VALUE)
+#define SWAP4BYTE(VALUE) __builtin_bswap32(VALUE)
 
 static void
 extract_uint_indexes(GLuint n, GLuint indexes[],
-- 
1.7.9.5

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[Mesa-dev] [PATCH] radv: emit fmuladd instead of fma to llvm.

[Dave Airlie]

From: Dave Airlie 

For Vulkan SPIR-V the spec states
fma() Inherited from OpFMul followed by OpFAdd.

Matt says the backend will do the right thing depending on the
hardware being compiled for, if you use the fmuladd intrinsic.

Using the Mad Max pts test, on high settings at 4K:
CHP: 55->60
HGDD: 46->50
LM: 55->60
No change on Stronghold.

Thanks to Feral for spending the time to track this down.

Signed-off-by: Dave Airlie 
---
 src/amd/common/ac_nir_to_llvm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/amd/common/ac_nir_to_llvm.c b/src/amd/common/ac_nir_to_llvm.c
index d7b6259..11ba487 100644
--- a/src/amd/common/ac_nir_to_llvm.c
+++ b/src/amd/common/ac_nir_to_llvm.c
@@ -1707,7 +1707,7 @@ static void visit_alu(struct ac_nir_context *ctx, const 
nir_alu_instr *instr)
  result);
break;
case nir_op_ffma:
-   result = emit_intrin_3f_param(>ac, "llvm.fma",
+   result = emit_intrin_3f_param(>ac, "llvm.fmuladd",
  ac_to_float_type(>ac, 
def_type), src[0], src[1], src[2]);
break;
case nir_op_ibitfield_extract:
-- 
2.9.4

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Re: [Mesa-dev] [PATCH] radv: Implement TC compatible HTILE.

[Dave Airlie]

On 4 October 2017 at 10:51, Bas Nieuwenhuizen  wrote:
> The situations where we enable it are quite limitied, but it works,
> even for madmax, so lets just enable it.

Let's land it, then we can work out where it needs tuning.

Reviewed-by: Dave Airlie 

Dave.

> ---
>  src/amd/vulkan/radv_device.c | 28 ++--
>  src/amd/vulkan/radv_image.c  | 21 +
>  src/amd/vulkan/radv_meta_clear.c | 18 ++
>  src/amd/vulkan/radv_private.h|  1 +
>  4 files changed, 62 insertions(+), 6 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 402c948e523..aa7fe35d87e 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -3249,6 +3249,18 @@ radv_initialise_ds_surface(struct radv_device *device,
> if (iview->image->surface.htile_size && !level) {
> ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
>
> +   if (iview->image->tc_compatible_htile) {
> +   unsigned max_zplanes = 4;
> +
> +   if (iview->vk_format == VK_FORMAT_D16_UNORM  
> &&
> +   iview->image->info.samples > 1)
> +   max_zplanes = 2;
> +
> +   ds->db_z_info |= 
> S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
> + S_028038_ITERATE_FLUSH(1);
> +   ds->db_stencil_info |= 
> S_02803C_ITERATE_FLUSH(1);
> +   }
> +
> if (!iview->image->surface.has_stencil)
> /* Use all of the htile_buffer for depth if 
> there's no stencil. */
> ds->db_stencil_info |= 
> S_02803C_TILE_STENCIL_DISABLE(1);
> @@ -3268,7 +3280,7 @@ radv_initialise_ds_surface(struct radv_device *device,
> z_offs += iview->image->surface.u.legacy.level[level].offset;
> s_offs += 
> iview->image->surface.u.legacy.stencil_level[level].offset;
>
> -   ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
> +   ds->db_depth_info = 
> S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
> ds->db_z_info = S_028040_FORMAT(format) | 
> S_028040_ZRANGE_PRECISION(1);
> ds->db_stencil_info = S_028044_FORMAT(stencil_format);
>
> @@ -3312,7 +3324,8 @@ radv_initialise_ds_surface(struct radv_device *device,
> if (iview->image->surface.htile_size && !level) {
> ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
>
> -   if (!iview->image->surface.has_stencil)
> +   if (!iview->image->surface.has_stencil &&
> +   !iview->image->tc_compatible_htile)
> /* Use all of the htile_buffer for depth if 
> there's no stencil. */
> ds->db_stencil_info |= 
> S_028044_TILE_STENCIL_DISABLE(1);
>
> @@ -3320,6 +,17 @@ radv_initialise_ds_surface(struct radv_device *device,
> iview->image->htile_offset;
> ds->db_htile_data_base = va >> 8;
> ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
> +
> +   if (iview->image->tc_compatible_htile) {
> +   ds->db_htile_surface |= 
> S_028ABC_TC_COMPATIBLE(1);
> +
> +   if (iview->image->info.samples <= 1)
> +   ds->db_z_info |= 
> S_028040_DECOMPRESS_ON_N_ZPLANES(5);
> +   else if (iview->image->info.samples <= 4)
> +   ds->db_z_info |= 
> S_028040_DECOMPRESS_ON_N_ZPLANES(3);
> +   else
> +   ds->db_z_info|= 
> S_028040_DECOMPRESS_ON_N_ZPLANES(2);
> +   }
> }
> }
>
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 35c58f45ab5..bf30281abaa 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -109,6 +109,15 @@ radv_init_surface(struct radv_device *device,
>
> if (is_depth) {
> surface->flags |= RADEON_SURF_ZBUFFER;
> +   if (!(pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
> +   !(pCreateInfo->flags & 
> VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) &&
> +   pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
> +   pCreateInfo->mipLevels <= 1 &&
> +   device->physical_device->rad_info.chip_class >= VI &&
> +   (pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
> +(device->physical_device->rad_info.chip_class >= GFX9 &&
> +

Re: [Mesa-dev] [PATCH 1/6] meson: Build i965 and dri stack

[Nicholas Miell]

On 10/03/2017 05:26 PM, Dylan Baker wrote:


diff --git a/meson_options.txt b/meson_options.txt
index eccd5c10d59..568903f1a0a 100644
--- a/meson_options.txt
+++ b/meson_options.txt



+option('valgrind',   type : 'boolean', vaule : true,


"vaule" typo.

"[PATCH 5/6] meson_options: Remove extra whitespace between parameters" 
also touches this line and does not fix the typo.


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Re: [Mesa-dev] [PATCH 2/6] meson: build glx

[Nicholas Miell]

On 10/03/2017 05:26 PM, Dylan Baker wrote:


diff --git a/meson_options.txt b/meson_options.txt
index 568903f1a0a..62d6b593f88 100644
--- a/meson_options.txt
+++ b/meson_options.txt



+option('glvnd',  type : 'boolean', vaule : false,


"vaule" again, although you fix this in "[PATCH 4/6] meson: build gbm" 
of this series.


I'm beginning to think that Meson should warn about unknown keys in 
dictionaries.

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[Mesa-dev] [PATCH] radv: Implement TC compatible HTILE.

[Bas Nieuwenhuizen]

The situations where we enable it are quite limitied, but it works,
even for madmax, so lets just enable it.
---
 src/amd/vulkan/radv_device.c | 28 ++--
 src/amd/vulkan/radv_image.c  | 21 +
 src/amd/vulkan/radv_meta_clear.c | 18 ++
 src/amd/vulkan/radv_private.h|  1 +
 4 files changed, 62 insertions(+), 6 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 402c948e523..aa7fe35d87e 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3249,6 +3249,18 @@ radv_initialise_ds_surface(struct radv_device *device,
if (iview->image->surface.htile_size && !level) {
ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
 
+   if (iview->image->tc_compatible_htile) {
+   unsigned max_zplanes = 4;
+
+   if (iview->vk_format == VK_FORMAT_D16_UNORM  &&
+   iview->image->info.samples > 1)
+   max_zplanes = 2;
+
+   ds->db_z_info |= 
S_028038_DECOMPRESS_ON_N_ZPLANES(max_zplanes + 1) |
+ S_028038_ITERATE_FLUSH(1);
+   ds->db_stencil_info |= 
S_02803C_ITERATE_FLUSH(1);
+   }
+
if (!iview->image->surface.has_stencil)
/* Use all of the htile_buffer for depth if 
there's no stencil. */
ds->db_stencil_info |= 
S_02803C_TILE_STENCIL_DISABLE(1);
@@ -3268,7 +3280,7 @@ radv_initialise_ds_surface(struct radv_device *device,
z_offs += iview->image->surface.u.legacy.level[level].offset;
s_offs += 
iview->image->surface.u.legacy.stencil_level[level].offset;
 
-   ds->db_depth_info = S_02803C_ADDR5_SWIZZLE_MASK(1);
+   ds->db_depth_info = 
S_02803C_ADDR5_SWIZZLE_MASK(!iview->image->tc_compatible_htile);
ds->db_z_info = S_028040_FORMAT(format) | 
S_028040_ZRANGE_PRECISION(1);
ds->db_stencil_info = S_028044_FORMAT(stencil_format);
 
@@ -3312,7 +3324,8 @@ radv_initialise_ds_surface(struct radv_device *device,
if (iview->image->surface.htile_size && !level) {
ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
 
-   if (!iview->image->surface.has_stencil)
+   if (!iview->image->surface.has_stencil &&
+   !iview->image->tc_compatible_htile)
/* Use all of the htile_buffer for depth if 
there's no stencil. */
ds->db_stencil_info |= 
S_028044_TILE_STENCIL_DISABLE(1);
 
@@ -3320,6 +,17 @@ radv_initialise_ds_surface(struct radv_device *device,
iview->image->htile_offset;
ds->db_htile_data_base = va >> 8;
ds->db_htile_surface = S_028ABC_FULL_CACHE(1);
+
+   if (iview->image->tc_compatible_htile) {
+   ds->db_htile_surface |= 
S_028ABC_TC_COMPATIBLE(1);
+
+   if (iview->image->info.samples <= 1)
+   ds->db_z_info |= 
S_028040_DECOMPRESS_ON_N_ZPLANES(5);
+   else if (iview->image->info.samples <= 4)
+   ds->db_z_info |= 
S_028040_DECOMPRESS_ON_N_ZPLANES(3);
+   else
+   ds->db_z_info|= 
S_028040_DECOMPRESS_ON_N_ZPLANES(2);
+   }
}
}
 
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 35c58f45ab5..bf30281abaa 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -109,6 +109,15 @@ radv_init_surface(struct radv_device *device,
 
if (is_depth) {
surface->flags |= RADEON_SURF_ZBUFFER;
+   if (!(pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) &&
+   !(pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) 
&&
+   pCreateInfo->tiling != VK_IMAGE_TILING_LINEAR &&
+   pCreateInfo->mipLevels <= 1 &&
+   device->physical_device->rad_info.chip_class >= VI &&
+   (pCreateInfo->format == VK_FORMAT_D32_SFLOAT ||
+(device->physical_device->rad_info.chip_class >= GFX9 &&
+ pCreateInfo->format == VK_FORMAT_D16_UNORM)))
+   surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
}
 
if (is_stencil)
@@ -255,6 +264,11 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va = gpu_address + image->dcc_offset;
if (chip_class <= VI)
  

[Mesa-dev] [PATCH 1/6] meson: Build i965 and dri stack

[Dylan Baker]

This gets pretty much the entire classic tree building, as well as
i965, including the various glapis. There are some workarounds for bugs
that are fixed in meson 0.43.0, which is due out on October 8th.

I have tested this with piglit using glx.

Signed-off-by: Dylan Baker 
---
 bin/install_megadrivers.py |  68 +++
 include/meson.build|  38 ++
 meson.build| 104 +++-
 meson_options.txt  |  14 +-
 src/compiler/{ => glsl/glcpp}/meson.build  |  57 +-
 src/compiler/glsl/meson.build  | 229 +++-
 src/compiler/glsl/tests/meson.build|  76 +++
 src/compiler/meson.build   |  12 +-
 src/git_sha1.h.in  |   1 +
 src/{compiler/glsl => mapi/es1api}/meson.build |  39 +-
 src/{compiler/glsl => mapi/es2api}/meson.build |  38 +-
 src/mapi/glapi/gen/meson.build | 270 ++
 src/mapi/glapi/meson.build |  81 +++
 {include => src/mapi}/meson.build  |  19 +-
 src/mapi/shared-glapi/meson.build  |  61 +++
 src/mapi/shared-glapi/tests/check_table.cpp|   6 +-
 .../glsl => mesa/drivers/dri/common}/meson.build   |  24 +-
 src/mesa/drivers/dri/i965/meson.build  | 177 +++
 src/{compiler => mesa/drivers/dri}/meson.build |  74 +--
 src/{compiler/glsl => mesa/main}/meson.build   |  29 +-
 src/mesa/meson.build   | 583 +
 src/{compiler/glsl => mesa/program}/meson.build|  18 +-
 src/meson.build|  26 +-
 src/util/meson.build   |   3 +-
 src/{compiler/glsl => util/xmlpool}/meson.build|  13 +-
 25 files changed, 1927 insertions(+), 133 deletions(-)
 create mode 100755 bin/install_megadrivers.py
 copy src/compiler/{ => glsl/glcpp}/meson.build (58%)
 create mode 100644 src/compiler/glsl/tests/meson.build
 create mode 100644 src/git_sha1.h.in
 copy src/{compiler/glsl => mapi/es1api}/meson.build (53%)
 copy src/{compiler/glsl => mapi/es2api}/meson.build (54%)
 create mode 100644 src/mapi/glapi/meson.build
 copy {include => src/mapi}/meson.build (81%)
 create mode 100644 src/mapi/shared-glapi/meson.build
 copy src/{compiler/glsl => mesa/drivers/dri/common}/meson.build (69%)
 create mode 100644 src/mesa/drivers/dri/i965/meson.build
 copy src/{compiler => mesa/drivers/dri}/meson.build (51%)
 copy src/{compiler/glsl => mesa/main}/meson.build (55%)
 create mode 100644 src/mesa/meson.build
 copy src/{compiler/glsl => mesa/program}/meson.build (74%)
 copy src/{compiler/glsl => util/xmlpool}/meson.build (80%)

diff --git a/bin/install_megadrivers.py b/bin/install_megadrivers.py
new file mode 100755
index 000..50a4323a6e8
--- /dev/null
+++ b/bin/install_megadrivers.py
@@ -0,0 +1,68 @@
+#!/usr/bin/env python
+# encoding=utf-8
+# Copyright ?? 2017 Intel Corporation
+
+# Permission is hereby granted, free of charge, to any person obtaining a copy
+# of this software and associated documentation files (the "Software"), to deal
+# in the Software without restriction, including without limitation the rights
+# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
+# copies of the Software, and to permit persons to whom the Software is
+# furnished to do so, subject to the following conditions:
+
+# The above copyright notice and this permission notice shall be included in
+# all copies or substantial portions of the Software.
+
+# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
+# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
+# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
+# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+# SOFTWARE.
+
+"""Script to install megadriver symlinks for meson."""
+
+import argparse
+import errno
+import os
+import shutil
+
+
+def main():
+parser = argparse.ArgumentParser()
+parser.add_argument('megadriver')
+parser.add_argument('libdir')
+parser.add_argument('drivers', nargs='+')
+args = parser.parse_args()
+
+to = os.path.join(os.environ.get('MESON_INSTALL_DESTDIR_PREFIX'), 
args.libdir)
+
+cross_found = False
+
+if not os.path.exists(to):
+os.makedirs(to)
+from_ = args.megadriver
+
+for each in args.drivers:
+final = os.path.join(to, each)
+if os.path.exists(final):
+os.unlink(final)
+print('installing {} to {}'.format(args.megadriver, to))
+try:
+os.link(from_, final)
+except OSError as e:
+if e.errno == errno.EXDEV:
+   

[Mesa-dev] [PATCH 2/6] meson: build glx

[Dylan Baker]

This gets GLX and the loader building. The resulting GLX and i965 have
been tested on piglit and seem to work fine. This patch leaves a lot of
todo's in it's wake, GLX is quite complicated, and the build options
involved are many, and the goal at the moment is to get dri and gallium
drivers building.

Signed-off-by: Dylan Baker 
---
 include/meson.build|   2 +-
 meson.build| 179 +--
 meson_options.txt  |   6 ++
 src/compiler/nir/meson.build   |   1 +
 src/glx/meson.build| 184 +
 src/{ => loader}/meson.build   |  56 +
 src/mapi/glapi/gen/meson.build |   5 +-
 src/mapi/glapi/meson.build |   2 +
 src/meson.build|   5 +-
 9 files changed, 353 insertions(+), 87 deletions(-)
 create mode 100644 src/glx/meson.build
 copy src/{ => loader}/meson.build (55%)

diff --git a/include/meson.build b/include/meson.build
index beb57e3e044..e33a8569d76 100644
--- a/include/meson.build
+++ b/include/meson.build
@@ -51,7 +51,7 @@ if with_opengl
   )
 endif
 
-if with_glx
+if with_glx != 'disabled'
   install_headers('GL/glx.h', 'GL/glext.h', 'GL/glx_mangle.h', subdir : 'GL')
 endif
 
diff --git a/meson.build b/meson.build
index 1824a7ea184..52ac24f59ca 100644
--- a/meson.build
+++ b/meson.build
@@ -21,7 +21,18 @@
 project('mesa', ['c', 'cpp'], version : '17.3.0-devel', license : 'MIT',
 default_options : ['c_std=c99', 'cpp_std=c++11'])
 
-with_dri3 = true  # XXX: need a switch for this
+# Arguments for the preprocessor, put these in a separate array from the C and
+# C++ (cpp in meson terminology) arguments since they need to be added to the
+# default arguments for both C and C++.
+pre_args = [
+  '-D__STDC_CONSTANT_MACROS',
+  '-D__STDC_FORMAT_MACROS',
+  '-D__STDC_LIMIT_MACROS',
+  '-DVERSION="@0@"'.format(meson.project_version()),
+  '-DPACKAGE_VERSION=VERSION',
+  
'-DPACKAGE_BUGREPORT="https://bugs.freedesktop.org/enter_bug.cgi?product=Mesa;',
+]
+
 with_vulkan_icd_dir = get_option('vulkan-icd-dir')
 with_tests = get_option('build-tests')
 with_valgrind = get_option('valgrind')
@@ -35,11 +46,24 @@ with_gles1 = get_option('gles1')
 with_gles2 = get_option('gles2')
 with_opengl = get_option('opengl')
 with_any_opengl = with_opengl or with_gles1 or with_gles2
-with_shared_glapi = get_option('shared-glapi')
+# Only build shared_glapi if at least one OpenGL API is enabled
+with_shared_glapi = get_option('shared-glapi') and with_any_opengl
+
+with_dri3 = get_option('dri3')
+if with_dri3 == 'auto'
+  if host_machine.system() == 'linux'
+with_dri3 = true
+  else
+with_dri3 = false
+ endif
+elif with_dri3 == 'yes'
+  with_dri3 = true
+else
+  with_dri3 = false
+endif
 
 # TODO: these will need options, but at the moment they just control header
 # installs
-with_glx = false
 with_osmesa = false
 
 # shared-glapi is required if at least two OpenGL APIs are being built
@@ -72,6 +96,12 @@ if not with_dri
   with_shared_glapi = false
 endif
 
+# TODO: other OSes
+with_dri_platform = 'drm'
+
+with_gallium = false
+# TODO: gallium drivers
+
 # TODO: there are more platforms required for non-vulkan drivers
 with_platform_wayland = false
 with_platform_x11 = false
@@ -82,20 +112,65 @@ if _platforms != ''
   with_platform_wayland = _split.contains('wayland')
 endif
 
+with_glx = get_option('glx')
+if with_glx != 'disabled'
+  pre_args += '-DGLX_USE_TLS'
+  if not (with_platform_x11 and with_any_opengl) and with_glx != 'auto'
+error('Cannot build GLX support without X11 platform support and at least 
one OpenGL API')
+  elif with_glx == 'gallium-xlib' 
+if not with_gallium
+  error('Gallium-xlib based GLX requires at least one gallium driver')
+elif with_dri
+  error('gallium-xlib conflicts with any dri driver')
+endif
+  elif with_glx == 'dri' and not with_dri
+error('dri based GLX requires at least one DRI driver')
+  elif with_glx == 'auto'
+if with_dri
+  with_glx = 'dri'
+elif with_gallium
+  with_glx = 'gallium-xlib'
+elif with_platform_x11 and with_any_opengl
+  with_glx = 'xlib'
+else
+  with_glx = 'disabled'
+endif
+  endif
+endif
+
+with_glvnd = get_option('glvnd')
+if with_glvnd and with_glx != 'dri'
+  message('glvnd requires dri based glx')
+endif
+
+# TODO: toggle for this
+with_glx_direct = true
+
 if with_vulkan_icd_dir == ''
   with_vulkan_icd_dir = join_paths(get_option('datadir'), 'vulkan/icd.d')
 endif
 
 with_intel_vk = false
 with_amd_vk = false
+with_any_vk = false
 _vulkan_drivers = get_option('vulkan-drivers')
 if _vulkan_drivers != ''
   _split = _vulkan_drivers.split(',')
   with_intel_vk = _split.contains('intel')
   with_amd_vk = _split.contains('amd')
+  with_any_vk = with_amd_vk or with_intel_vk
   if not (with_platform_x11 or with_platform_wayland)
 error('Vulkan requires at least one platform (x11, wayland)')
   endif
+  if not 

[Mesa-dev] [PATCH 6/6] meson: build classic swrast

[Dylan Baker]

This adds support for building the classic swrast implementation. This
driver has been tested with glxinfo and glxgears.

Signed-off-by: Dylan Baker 
---
 meson.build   |  2 ++
 meson_options.txt |  2 +-
 src/mesa/drivers/dri/meson.build  |  5 +++
 src/mesa/drivers/dri/{ => swrast}/meson.build | 45 +--
 4 files changed, 16 insertions(+), 38 deletions(-)
 copy src/mesa/drivers/dri/{ => swrast}/meson.build (52%)

diff --git a/meson.build b/meson.build
index 185d70509c5..603bdfbdb7f 100644
--- a/meson.build
+++ b/meson.build
@@ -73,10 +73,12 @@ endif
 
 with_dri = false
 with_dri_i965 = false
+with_dri_swrast = false
 _drivers = get_option('dri-drivers')
 if _drivers != ''
   _split = _drivers.split(',')
   with_dri_i965 = _split.contains('i965')
+  with_dri_swrast = _split.contains('swrast')
   with_dri = true
 endif
 
diff --git a/meson_options.txt b/meson_options.txt
index 2306be319cc..5fdb41e6071 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -21,7 +21,7 @@
 option('platforms',type : 'string', value : 'x11,wayland', description : 
'comma separated list of window systems to support. wayland, x11, surfaceless, 
drm, etc.')
 option('dri3', type : 'combo', value : 'auto', choices : ['auto', 'yes', 'no'],
description : 'enable support for dri3')
-option('dri-drivers', type : 'string', value : 'i965',
+option('dri-drivers', type : 'string', value : 'swrast,i965',
description : 'comma separated list of dri drivers to build.')
 option('dri-drivers-path', type : 'string', value : '',
description : 'Location of dri drivers. Default: $libdir/dri.')
diff --git a/src/mesa/drivers/dri/meson.build b/src/mesa/drivers/dri/meson.build
index f7403ec09fc..153aa15efb6 100644
--- a/src/mesa/drivers/dri/meson.build
+++ b/src/mesa/drivers/dri/meson.build
@@ -19,11 +19,16 @@
 # SOFTWARE.
 
 subdir('common')
+subdir('swrast')
 subdir('i965')
 
 if with_dri
   dri_drivers = []
   dri_link = []
+  if with_dri_swrast
+dri_drivers += libswrast_dri
+dri_link += 'swrast_dri.so'
+  endif
   if with_dri_i965
 dri_drivers += libi965
 dri_link += 'i965_dri.so'
diff --git a/src/mesa/drivers/dri/meson.build 
b/src/mesa/drivers/dri/swrast/meson.build
similarity index 52%
copy from src/mesa/drivers/dri/meson.build
copy to src/mesa/drivers/dri/swrast/meson.build
index f7403ec09fc..1235dedbe3c 100644
--- a/src/mesa/drivers/dri/meson.build
+++ b/src/mesa/drivers/dri/swrast/meson.build
@@ -18,40 +18,11 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-subdir('common')
-subdir('i965')
-
-if with_dri
-  dri_drivers = []
-  dri_link = []
-  if with_dri_i965
-dri_drivers += libi965
-dri_link += 'i965_dri.so'
-  endif
-
-  libmesa_dri_drivers = shared_library(
-'mesa_dri_drivers',
-dummy_cpp,  # see meson #2180
-link_whole : dri_drivers,
-link_with : [libmegadriver_stub, libdricommon, libxmlconfig, libglapi,
- libmesa_util, libnir, libmesa_classic],
-dependencies : [dep_selinux, dep_libdrm, dep_expat, dep_m, dep_thread,
-dep_dl],
-link_args : [ld_args_bsymbolic, ld_args_gc_sections],
-  )
-
-  pkg.generate(
-name : 'dri',
-filebase : 'dri',
-description : 'Direct Rendering Infrastructure',
-version : meson.project_version(),
-requires_private : ['libdrm >= 2.4.75'],  # FIXME: don't hardcode this
-  )
-
-  meson.add_install_script(
-join_paths(meson.source_root(), 'bin/install_megadrivers.py'),
-libmesa_dri_drivers.full_path(),
-with_dri_drivers_path,
-dri_link,
-  )
-endif
+libswrast_dri = static_library(
+  'swrast_dri',
+  files('swrast.c', 'swrast_priv.h'),
+  c_args : [c_vis_args],
+  include_directories : [inc_common, inc_dri_common],
+  dependencies : dep_libdrm,
+  build_by_default : false,
+)
-- 
2.14.1

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[Mesa-dev] [PATCH 0/6] Meson round 3, classic drivers

[Dylan Baker]

This series adds support for building the two classic drivers that I could
readily test, i965 and swrast. The main point is not to turn on drivers atm, but
to demonstrate that the underlying stack is being compiled correctly and that
the meson is correct and understandable; and to allow others wanting to work on
related code (like Eric on egl) to do so.

I have gallium patches that build radeonSi, but there's still some bugs there,
so I'm starting with this.

There are a number of TODO comments in this code for meson itself, several of
these bugs are addressed in meson 0.43.0 which is due out on the 8th.

Dylan Baker (6):
  meson: Build i965 and dri stack
  meson: build glx
  meson: Add support for configuring dri drivers directory.
  meson: build gbm
  meson_options: Remove extra whitespace between parameters
  meson: build classic swrast

 bin/install_megadrivers.py |  68 +++
 include/meson.build|  38 ++
 meson.build| 294 +--
 meson_options.txt  |  31 +-
 src/compiler/{ => glsl/glcpp}/meson.build  |  57 +-
 src/compiler/glsl/meson.build  | 229 +++-
 src/compiler/glsl/tests/meson.build|  76 +++
 src/compiler/meson.build   |  12 +-
 src/compiler/nir/meson.build   |   1 +
 src/{compiler => gbm}/meson.build  |  72 +--
 src/git_sha1.h.in  |   1 +
 src/glx/meson.build| 182 +++
 src/{compiler/glsl => loader}/meson.build  |  29 +-
 src/{compiler/glsl => mapi/es1api}/meson.build |  39 +-
 src/{compiler/glsl => mapi/es2api}/meson.build |  38 +-
 src/mapi/glapi/gen/meson.build | 271 ++
 src/mapi/glapi/meson.build |  83 +++
 {include => src/mapi}/meson.build  |  19 +-
 src/mapi/shared-glapi/meson.build  |  61 +++
 src/mapi/shared-glapi/tests/check_table.cpp|   6 +-
 .../glsl => mesa/drivers/dri/common}/meson.build   |  24 +-
 src/mesa/drivers/dri/i965/meson.build  | 177 +++
 src/mesa/drivers/dri/meson.build   |  62 +++
 .../mesa/drivers/dri/swrast}/meson.build   |  10 +-
 src/{compiler/glsl => mesa/main}/meson.build   |  29 +-
 src/mesa/meson.build   | 583 +
 src/{compiler/glsl => mesa/program}/meson.build|  18 +-
 src/meson.build|  35 +-
 src/util/meson.build   |   3 +-
 src/{compiler/glsl => util/xmlpool}/meson.build|  13 +-
 30 files changed, 2376 insertions(+), 185 deletions(-)
 create mode 100755 bin/install_megadrivers.py
 copy src/compiler/{ => glsl/glcpp}/meson.build (58%)
 create mode 100644 src/compiler/glsl/tests/meson.build
 copy src/{compiler => gbm}/meson.build (50%)
 create mode 100644 src/git_sha1.h.in
 create mode 100644 src/glx/meson.build
 copy src/{compiler/glsl => loader}/meson.build (61%)
 copy src/{compiler/glsl => mapi/es1api}/meson.build (53%)
 copy src/{compiler/glsl => mapi/es2api}/meson.build (54%)
 create mode 100644 src/mapi/glapi/meson.build
 copy {include => src/mapi}/meson.build (81%)
 create mode 100644 src/mapi/shared-glapi/meson.build
 copy src/{compiler/glsl => mesa/drivers/dri/common}/meson.build (69%)
 create mode 100644 src/mesa/drivers/dri/i965/meson.build
 create mode 100644 src/mesa/drivers/dri/meson.build
 copy {include => src/mesa/drivers/dri/swrast}/meson.build (82%)
 copy src/{compiler/glsl => mesa/main}/meson.build (55%)
 create mode 100644 src/mesa/meson.build
 copy src/{compiler/glsl => mesa/program}/meson.build (74%)
 copy src/{compiler/glsl => util/xmlpool}/meson.build (80%)

-- 
2.14.1

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[Mesa-dev] [PATCH 4/6] meson: build gbm

[Dylan Baker]

This doesn't include egl support, just dri support.

Signed-off-by: Dylan Baker 
---
 meson.build | 49 +---
 meson_options.txt   | 14 +
 src/{loader => gbm}/meson.build | 63 -
 src/glx/meson.build | 10 +++
 src/loader/meson.build  |  2 ++
 src/mesa/meson.build|  2 +-
 src/meson.build |  4 ++-
 7 files changed, 95 insertions(+), 49 deletions(-)
 copy src/{loader => gbm}/meson.build (50%)

diff --git a/meson.build b/meson.build
index ec50e10b38c..185d70509c5 100644
--- a/meson.build
+++ b/meson.build
@@ -54,19 +54,6 @@ with_any_opengl = with_opengl or with_gles1 or with_gles2
 # Only build shared_glapi if at least one OpenGL API is enabled
 with_shared_glapi = get_option('shared-glapi') and with_any_opengl
 
-with_dri3 = get_option('dri3')
-if with_dri3 == 'auto'
-  if host_machine.system() == 'linux'
-with_dri3 = true
-  else
-with_dri3 = false
- endif
-elif with_dri3 == 'yes'
-  with_dri3 = true
-else
-  with_dri3 = false
-endif
-
 # TODO: these will need options, but at the moment they just control header
 # installs
 with_osmesa = false
@@ -107,6 +94,27 @@ with_dri_platform = 'drm'
 with_gallium = false
 # TODO: gallium drivers
 
+# TODO: conditionalize libdrm requirement
+dep_libdrm = dependency('libdrm', version : '>= 2.4.75')
+pre_args += '-DHAVE_LIBDRM'
+
+with_dri2 = with_dri and with_dri_platform == 'drm' and dep_libdrm.found()
+with_dri3 = get_option('dri3')
+if with_dri3 == 'auto'
+  if host_machine.system() == 'linux' and with_dri2
+with_dri3 = true
+  else
+with_dri3 = false
+ endif
+elif with_dri3 == 'yes'
+  if not with_dri2
+error('dri3 support requires libdrm')
+  endif
+  with_dri3 = true
+else
+  with_dri3 = false
+endif
+
 # TODO: there are more platforms required for non-vulkan drivers
 with_platform_wayland = false
 with_platform_x11 = false
@@ -117,6 +125,18 @@ if _platforms != ''
   with_platform_wayland = _split.contains('wayland')
 endif
 
+with_gbm = get_option('gbm')
+if with_gbm == 'auto'
+  with_gbm = host_machine.system() == 'linux'
+elif with_gbm == 'yes'
+  if not ['linux', 'bsd'].contains(host_machine.system())
+error('GBM only supports unix-like platforms')
+  endif
+  with_gbm = true
+else
+  with_gbm = false
+endif
+
 with_glx = get_option('glx')
 if with_glx != 'disabled'
   pre_args += '-DGLX_USE_TLS'
@@ -446,9 +466,6 @@ dep_expat = dependency('expat')
 # its not linux and and wont
 dep_m = cc.find_library('m', required : false)
 
-# TODO: conditionalize libdrm requirement
-dep_libdrm = dependency('libdrm', version : '>= 2.4.75')
-pre_args += '-DHAVE_LIBDRM'
 dep_libdrm_amdgpu = []
 if with_amd_vk
   dep_libdrm_amdgpu = dependency('libdrm_amdgpu', version : '>= 2.4.82')
diff --git a/meson_options.txt b/meson_options.txt
index 130d3962db7..b6d44c44ba9 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -32,17 +32,19 @@ option('shader-cache',type : 'boolean', value : true,
description : 'Build with on-disk shader cache support')
 option('vulkan-icd-dir', type : 'string',  value : '',
description : 'Location relative to prefix to put vulkan icds on 
install. Default: $datadir/vulkan/icd.d')
-option('shared-glapi',   type : 'boolean', value : true,
+option('shared-glapi',type : 'boolean', value : true,
description : 'Whether to build a shared or static glapi')
-option('gles1',  type : 'boolean', value : true,
+option('gles1',   type : 'boolean', value : true,
description : 'Build support for OpenGL ES 1.x')
-option('gles2',  type : 'boolean', value : true,
+option('gles2',   type : 'boolean', value : true,
description : 'Build support for OpenGL ES 2.x and 3.x')
-option('opengl', type : 'boolean', value : true,
+option('opengl',  type : 'boolean', value : true,
description : 'Build support for OpenGL (all versions)')
-option('glx',type : 'combo',   value : 'auto', choices : ['auto', 
'disabled', 'dri', 'xlib', 'gallium-xlib'],
+option('gbm', type : 'combo',   value : 'auto', choices : ['auto', 
'yes', 'no'],
+   description : 'Build support for gbm platform')
+option('glx', type : 'combo',   value : 'auto', choices : ['auto', 
'disabled', 'dri', 'xlib', 'gallium-xlib'],
description : 'Build support for GLX platform')
-option('glvnd',  type : 'boolean', vaule : false,
+option('glvnd',   type : 'boolean', value : false,
description : 'Enable GLVND support.')
 option('asm',type : 'boolean', value : true,
description : 'Build assembly code if possible')
diff --git a/src/loader/meson.build b/src/gbm/meson.build
similarity index 50%
copy from src/loader/meson.build
copy to src/gbm/meson.build
index 2c2af7a3d59..45b71a5a6f6 100644
--- a/src/loader/meson.build
+++ 

[Mesa-dev] [PATCH 3/6] meson: Add support for configuring dri drivers directory.

[Dylan Baker]

Signed-off-by: Dylan Baker 
---
 meson.build  |  6 ++
 meson_options.txt| 14 --
 src/glx/meson.build  |  2 +-
 src/mesa/drivers/dri/meson.build |  2 +-
 4 files changed, 16 insertions(+), 8 deletions(-)

diff --git a/meson.build b/meson.build
index 52ac24f59ca..ec50e10b38c 100644
--- a/meson.build
+++ b/meson.build
@@ -42,6 +42,11 @@ with_asm = get_option('asm')
 with_appledri = false
 with_windowsdri = false
 
+with_dri_drivers_path = get_option('dri-drivers-path')
+if with_dri_drivers_path == ''
+  with_dri_drivers_path = join_paths(get_option('libdir'), 'dri')
+endif
+
 with_gles1 = get_option('gles1')
 with_gles2 = get_option('gles2')
 with_opengl = get_option('opengl')
@@ -573,6 +578,7 @@ if with_platform_x11
   dependency('xcb-dri2', version : '>= 1.8'),
   dependency('xcb-xfixes'),
 ]
+pre_args += '-DHAVE_X11_PLATFORM'
 if with_dri3
   pre_args += '-DHAVE_DRI3'
   dep_xcb_dri3 = [
diff --git a/meson_options.txt b/meson_options.txt
index 62d6b593f88..130d3962db7 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -18,13 +18,15 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-option('platforms',  type : 'string',  value : 'x11,wayland',
+option('platforms',   type : 'string',  value : 'x11,wayland',
description : 'comma separated list of window systems to support. 
wayland, x11, surfaceless, drm, etc.')
-option('dri3',   type : 'combo',   value : 'auto', choices : ['auto', 
'yes', 'no'],
-   description : 'comma separated list of window systems to support. 
wayland, x11, surfaceless, drm, etc.')
-option('dri-drivers',type : 'string',  value : 'i965',
+option('dri3',type : 'combo',   value : 'auto', choices : ['auto', 
'yes', 'no'],
+   description : 'enable support for dri3')
+option('dri-drivers', type : 'string',  value : 'i965',
description : 'comma separated list of dri drivers to build.')
-option('vulkan-drivers', type : 'string',  value : 'intel,amd',
+option('dri-drivers-path', type : 'string',  value : '',
+   description : 'Location of dri drivers. Default: $libdir/dri.')
+option('vulkan-drivers',  type : 'string',  value : 'intel,amd',
description : 'comma separated list of vulkan drivers to build.')
 option('shader-cache',type : 'boolean', value : true,
description : 'Build with on-disk shader cache support')
@@ -46,5 +48,5 @@ option('asm',type : 'boolean', value : true,
description : 'Build assembly code if possible')
 option('valgrind',   type : 'boolean', vaule : true,
description : 'Build with valgrind support if possible')
-option('build-tests',type : 'boolean', value : false,
+option('build-tests', type : 'boolean', value : false,
description : 'Build unit tests. Currently this will build *all* unit 
tests, which may build more than expected.')
diff --git a/src/glx/meson.build b/src/glx/meson.build
index 821623dc263..6b6e9095740 100644
--- a/src/glx/meson.build
+++ b/src/glx/meson.build
@@ -108,7 +108,7 @@ endif
 
 # TODO: libglvnd
 
-dri_driver_dir = join_paths(get_option('prefix'), get_option('libdir'), 'dri')
+dri_driver_dir = join_paths(get_option('prefix'), with_dri_drivers_path)
 if not with_glvnd
   gl_lib_name = 'GL'
   gl_lib_version = '1.2'
diff --git a/src/mesa/drivers/dri/meson.build b/src/mesa/drivers/dri/meson.build
index e9612ea7050..f7403ec09fc 100644
--- a/src/mesa/drivers/dri/meson.build
+++ b/src/mesa/drivers/dri/meson.build
@@ -51,7 +51,7 @@ if with_dri
   meson.add_install_script(
 join_paths(meson.source_root(), 'bin/install_megadrivers.py'),
 libmesa_dri_drivers.full_path(),
-join_paths(get_option('libdir'), 'dri'),
+with_dri_drivers_path,
 dri_link,
   )
 endif
-- 
2.14.1

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[Mesa-dev] [PATCH 5/6] meson_options: Remove extra whitespace between parameters

[Dylan Baker]

Originally I had these all colomized and pretty, then I wrote
descriptions for the options, and they ceased to be pretty.

Signed-off-by: Dylan Baker 
---
 meson_options.txt | 43 +--
 1 file changed, 17 insertions(+), 26 deletions(-)

diff --git a/meson_options.txt b/meson_options.txt
index b6d44c44ba9..2306be319cc 100644
--- a/meson_options.txt
+++ b/meson_options.txt
@@ -18,37 +18,28 @@
 # OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
 # SOFTWARE.
 
-option('platforms',   type : 'string',  value : 'x11,wayland',
-   description : 'comma separated list of window systems to support. 
wayland, x11, surfaceless, drm, etc.')
-option('dri3',type : 'combo',   value : 'auto', choices : ['auto', 
'yes', 'no'],
+option('platforms',type : 'string', value : 'x11,wayland', description : 
'comma separated list of window systems to support. wayland, x11, surfaceless, 
drm, etc.')
+option('dri3', type : 'combo', value : 'auto', choices : ['auto', 'yes', 'no'],
description : 'enable support for dri3')
-option('dri-drivers', type : 'string',  value : 'i965',
+option('dri-drivers', type : 'string', value : 'i965',
description : 'comma separated list of dri drivers to build.')
-option('dri-drivers-path', type : 'string',  value : '',
+option('dri-drivers-path', type : 'string', value : '',
description : 'Location of dri drivers. Default: $libdir/dri.')
-option('vulkan-drivers',  type : 'string',  value : 'intel,amd',
+option('vulkan-drivers', type : 'string', value : 'intel,amd',
description : 'comma separated list of vulkan drivers to build.')
-option('shader-cache',type : 'boolean', value : true,
-   description : 'Build with on-disk shader cache support')
-option('vulkan-icd-dir', type : 'string',  value : '',
+option('shader-cache', type : 'boolean', value : true, description : 'Build 
with on-disk shader cache support')
+option('vulkan-icd-dir', type : 'string', value : '',
description : 'Location relative to prefix to put vulkan icds on 
install. Default: $datadir/vulkan/icd.d')
-option('shared-glapi',type : 'boolean', value : true,
-   description : 'Whether to build a shared or static glapi')
-option('gles1',   type : 'boolean', value : true,
-   description : 'Build support for OpenGL ES 1.x')
-option('gles2',   type : 'boolean', value : true,
-   description : 'Build support for OpenGL ES 2.x and 3.x')
-option('opengl',  type : 'boolean', value : true,
-   description : 'Build support for OpenGL (all versions)')
-option('gbm', type : 'combo',   value : 'auto', choices : ['auto', 
'yes', 'no'],
+option('shared-glapi', type : 'boolean', value : true, description : 'Whether 
to build a shared or static glapi')
+option('gles1', type : 'boolean', value : true, description : 'Build support 
for OpenGL ES 1.x')
+option('gles2', type : 'boolean', value : true, description : 'Build support 
for OpenGL ES 2.x and 3.x')
+option('opengl', type : 'boolean', value : true, description : 'Build support 
for OpenGL (all versions)')
+option('gbm', type : 'combo', value : 'auto', choices : ['auto', 'yes', 'no'],
description : 'Build support for gbm platform')
-option('glx', type : 'combo',   value : 'auto', choices : ['auto', 
'disabled', 'dri', 'xlib', 'gallium-xlib'],
+option('glx', type : 'combo', value : 'auto', choices : ['auto', 'disabled', 
'dri', 'xlib', 'gallium-xlib'],
description : 'Build support for GLX platform')
-option('glvnd',   type : 'boolean', value : false,
-   description : 'Enable GLVND support.')
-option('asm',type : 'boolean', value : true,
-   description : 'Build assembly code if possible')
-option('valgrind',   type : 'boolean', vaule : true,
-   description : 'Build with valgrind support if possible')
-option('build-tests', type : 'boolean', value : false,
+option('glvnd', type : 'boolean', value : false, description : 'Enable GLVND 
support.')
+option('asm', type : 'boolean', value : true, description : 'Build assembly 
code if possible')
+option('valgrind', type : 'boolean', vaule : true, description : 'Build with 
valgrind support if possible')
+option('build-tests', type : 'boolean', value : false,
description : 'Build unit tests. Currently this will build *all* unit 
tests, which may build more than expected.')
-- 
2.14.1

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Re: [Mesa-dev] [PATCH v2 3/3] glsl: make loop unrolling more like the nir unrolling path

[Timothy Arceri]

Ping on patches 1 & 3

On 21/09/17 20:55, Timothy Arceri wrote:

The old code assumed that loop terminators will always be at
the start of the loop, resulting in otherwise unrollable
loops not being unrolled at all. For example the current
code would unroll:

   int j = 0;
   do {
  if (j > 5)
 break;

  ... do stuff ...

  j++;
   } while (j < 4);

But would fail to unroll the following as no iteration limit was
calculated because it failed to find the terminator:

   int j = 0;
   do {
  ... do stuff ...

  j++;
   } while (j < 4);

Also we would fail to unroll the following as we ended up
calculating the iteration limit as 6 rather than 4. The unroll
code then assumed we had 3 terminators rather the 2 as it
wasn't able to determine that "if (j > 5)" was redundant.

   int j = 0;
   do {
  if (j > 5)
 break;

  ... do stuff ...

  if (bool(i))
 break;

  j++;
   } while (j < 4);

This patch changes this pass to be more like the NIR unrolling pass.
With this change we handle loop terminators correctly and also
handle cases where the terminators have instructions in their
branches other than a break.

V2:
- fixed regression where loops with a break in else were never
   unrolled in v1.
- fixed confusing/wrong naming of bools in complex unrolling.
---
  src/compiler/glsl/loop_analysis.cpp |  50 +--
  src/compiler/glsl/loop_analysis.h   |   5 +-
  src/compiler/glsl/loop_unroll.cpp   | 172 
  3 files changed, 161 insertions(+), 66 deletions(-)

diff --git a/src/compiler/glsl/loop_analysis.cpp 
b/src/compiler/glsl/loop_analysis.cpp
index 78279844dc..5bf406e7ee 100644
--- a/src/compiler/glsl/loop_analysis.cpp
+++ b/src/compiler/glsl/loop_analysis.cpp
@@ -18,21 +18,21 @@
   * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
   * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
   * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
   * DEALINGS IN THE SOFTWARE.
   */
  
  #include "compiler/glsl_types.h"

  #include "loop_analysis.h"
  #include "ir_hierarchical_visitor.h"
  
-static bool is_loop_terminator(ir_if *ir);

+static void try_add_loop_terminator(loop_variable_state *ls, ir_if *ir);
  
  static bool all_expression_operands_are_loop_constant(ir_rvalue *,

  hash_table *);
  
  static ir_rvalue *get_basic_induction_increment(ir_assignment *, hash_table *);
  
  /**

   * Find an initializer of a variable outside a loop
   *
   * Works backwards from the loop to find the pre-loop value of the variable.
@@ -80,21 +80,21 @@ find_initial_value(ir_loop *loop, ir_variable *var)
   break;
}
 }
  
 return NULL;

  }
  
  
  static int

  calculate_iterations(ir_rvalue *from, ir_rvalue *to, ir_rvalue *increment,
- enum ir_expression_operation op)
+ enum ir_expression_operation op, bool continue_from_then)
  {
 if (from == NULL || to == NULL || increment == NULL)
return -1;
  
 void *mem_ctx = ralloc_context(NULL);
  
 ir_expression *const sub =

new(mem_ctx) ir_expression(ir_binop_sub, from->type, to, from);
  
 ir_expression *const div =

@@ -147,22 +147,24 @@ calculate_iterations(ir_rvalue *from, ir_rvalue *to, 
ir_rvalue *increment,
unreachable("Unsupported type for loop iterator.");
}
  
ir_expression *const mul =

   new(mem_ctx) ir_expression(ir_binop_mul, increment->type, iter,
  increment);
  
ir_expression *const add =

   new(mem_ctx) ir_expression(ir_binop_add, mul->type, mul, from);
  
-  ir_expression *const cmp =

+  ir_expression *cmp =
   new(mem_ctx) ir_expression(op, glsl_type::bool_type, add, to);
+  if (continue_from_then)
+ cmp = new(mem_ctx) ir_expression(ir_unop_logic_not, cmp);
  
ir_constant *const cmp_result = cmp->constant_expression_value(mem_ctx);
  
assert(cmp_result != NULL);

if (cmp_result->get_bool_component(0)) {
   iter_value += bias[i];
   valid_loop = true;
   break;
}
 }
@@ -299,26 +301,28 @@ loop_variable_state::insert(ir_variable *var)
 lv->var = var;
  
 _mesa_hash_table_insert(this->var_hash, lv->var, lv);

 this->variables.push_tail(lv);
  
 return lv;

  }
  
  
  loop_terminator *

-loop_variable_state::insert(ir_if *if_stmt)
+loop_variable_state::insert(ir_if *if_stmt, bool continue_from_then)
  {
 void *mem_ctx = ralloc_parent(this);
 loop_terminator *t = new(mem_ctx) loop_terminator();
  
 t->ir = if_stmt;

+   t->continue_from_then = continue_from_then;
+
 this->terminators.push_tail(t);
  
 return t;

  }
  
  
  /**

   * If the given variable already is recorded in the state for this loop,
   * return the corresponding loop_variable object 

Re: [Mesa-dev] [PATCH v2 09/11] anv: add nir lowering pass for ycrcb textures

[Jason Ekstrand]

On Tue, Oct 3, 2017 at 4:54 PM, Jason Ekstrand  wrote:

> On Tue, Oct 3, 2017 at 9:29 AM, Lionel Landwerlin <
> lionel.g.landwer...@intel.com> wrote:
>
>> This pass implements all the implicit conversions required by the
>> VK_KHR_sampler_ycbcr_conversion specification.
>>
>> It also inserts plane sources onto sampling instructions that we then
>> let the pipeline layout pass deal with, when mapping things correctly
>> to descriptors.
>>
>> Signed-off-by: Lionel Landwerlin 
>> ---
>>  src/intel/Makefile.sources   |   1 +
>>  src/intel/vulkan/anv_nir.h   |   3 +
>>  src/intel/vulkan/anv_nir_apply_pipeline_layout.c |  62 ++-
>>  src/intel/vulkan/anv_nir_lower_ycbcr_textures.c  | 468
>> +++
>>  src/intel/vulkan/anv_pipeline.c  |   2 +
>>  src/intel/vulkan/anv_private.h   |  16 +-
>>  6 files changed, 545 insertions(+), 7 deletions(-)
>>  create mode 100644 src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
>>
>> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
>> index bca7a132b26..9672dcc252d 100644
>> --- a/src/intel/Makefile.sources
>> +++ b/src/intel/Makefile.sources
>> @@ -219,6 +219,7 @@ VULKAN_FILES := \
>> vulkan/anv_nir_lower_input_attachments.c \
>> vulkan/anv_nir_lower_multiview.c \
>> vulkan/anv_nir_lower_push_constants.c \
>> +   vulkan/anv_nir_lower_ycbcr_textures.c \
>> vulkan/anv_pass.c \
>> vulkan/anv_pipeline.c \
>> vulkan/anv_pipeline_cache.c \
>> diff --git a/src/intel/vulkan/anv_nir.h b/src/intel/vulkan/anv_nir.h
>> index 5b450b45cdf..0a06e3a1cf0 100644
>> --- a/src/intel/vulkan/anv_nir.h
>> +++ b/src/intel/vulkan/anv_nir.h
>> @@ -37,6 +37,9 @@ void anv_nir_lower_push_constants(nir_shader *shader);
>>
>>  bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask);
>>
>> +void anv_nir_lower_ycbcr_textures(nir_shader *shader,
>> +  struct anv_pipeline *pipeline);
>> +
>>  void anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
>> nir_shader *shader,
>> struct brw_stage_prog_data *prog_data,
>> diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
>> b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
>> index 428cfdf42d1..7cd28debe09 100644
>> --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
>> +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
>> @@ -131,7 +131,7 @@ lower_res_index_intrinsic(nir_intrinsic_instr
>> *intrin,
>>  static void
>>  lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
>>  unsigned *const_index, unsigned hw_binding_size,
>> -nir_tex_src_type src_type,
>> +nir_tex_src_type src_type, bool allow_indirect,
>>  struct apply_pipeline_layout_state *state)
>>  {
>> nir_builder *b = >builder;
>> @@ -141,6 +141,15 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var
>> *deref,
>>nir_deref_array *deref_array = nir_deref_as_array(deref->dere
>> f.child);
>>
>>if (deref_array->deref_array_type ==
>> nir_deref_array_type_indirect) {
>> + /* From VK_KHR_sampler_ycbcr_conversion:
>> +  *
>> +  * If sampler Y’CBCR conversion is enabled, the combined image
>> +  * sampler must be indexed only by constant integral
>> expressions when
>> +  * aggregated into arrays in shader code, irrespective of the
>> +  * shaderSampledImageArrayDynamicIndexing feature.
>> +  */
>> + assert(allow_indirect);
>> +
>>   nir_ssa_def *index =
>>  nir_iadd(b, nir_imm_int(b, deref_array->base_offset),
>>  nir_ssa_for_src(b, deref_array->indirect, 1));
>> @@ -150,7 +159,6 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var
>> *deref,
>>
>>   nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
>> tex->num_srcs + 1);
>> -
>>
>
> Spurrious change?
>
>
>>   for (unsigned i = 0; i < tex->num_srcs; i++) {
>>  new_srcs[i].src_type = tex->src[i].src_type;
>>  nir_instr_move_src(>instr, _srcs[i].src,
>> >src[i].src);
>> @@ -186,6 +194,46 @@ cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var
>> *deref)
>> nir_instr_rewrite_src(>instr, _array->indirect,
>> NIR_SRC_INIT);
>>  }
>>
>> +static bool
>> +has_tex_src_plane(nir_tex_instr *tex)
>> +{
>> +   for (unsigned i = 0; i < tex->num_srcs; i++) {
>> +  if (tex->src[i].src_type == nir_tex_src_plane)
>> + return true;
>> +   }
>> +
>> +   return false;
>> +}
>> +
>> +static uint32_t
>> +extract_tex_src_plane(nir_tex_instr *tex)
>> +{
>> +   nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src, tex->num_srcs
>> - 1);
>> +   unsigned plane = 0;
>> +
>> +   for (unsigned i = 0, w = 0; i < tex->num_srcs; i++) {
>> +  

Re: [Mesa-dev] [PATCH v2 09/11] anv: add nir lowering pass for ycrcb textures

[Jason Ekstrand]

On Tue, Oct 3, 2017 at 9:29 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> This pass implements all the implicit conversions required by the
> VK_KHR_sampler_ycbcr_conversion specification.
>
> It also inserts plane sources onto sampling instructions that we then
> let the pipeline layout pass deal with, when mapping things correctly
> to descriptors.
>
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/Makefile.sources   |   1 +
>  src/intel/vulkan/anv_nir.h   |   3 +
>  src/intel/vulkan/anv_nir_apply_pipeline_layout.c |  62 ++-
>  src/intel/vulkan/anv_nir_lower_ycbcr_textures.c  | 468
> +++
>  src/intel/vulkan/anv_pipeline.c  |   2 +
>  src/intel/vulkan/anv_private.h   |  16 +-
>  6 files changed, 545 insertions(+), 7 deletions(-)
>  create mode 100644 src/intel/vulkan/anv_nir_lower_ycbcr_textures.c
>
> diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
> index bca7a132b26..9672dcc252d 100644
> --- a/src/intel/Makefile.sources
> +++ b/src/intel/Makefile.sources
> @@ -219,6 +219,7 @@ VULKAN_FILES := \
> vulkan/anv_nir_lower_input_attachments.c \
> vulkan/anv_nir_lower_multiview.c \
> vulkan/anv_nir_lower_push_constants.c \
> +   vulkan/anv_nir_lower_ycbcr_textures.c \
> vulkan/anv_pass.c \
> vulkan/anv_pipeline.c \
> vulkan/anv_pipeline_cache.c \
> diff --git a/src/intel/vulkan/anv_nir.h b/src/intel/vulkan/anv_nir.h
> index 5b450b45cdf..0a06e3a1cf0 100644
> --- a/src/intel/vulkan/anv_nir.h
> +++ b/src/intel/vulkan/anv_nir.h
> @@ -37,6 +37,9 @@ void anv_nir_lower_push_constants(nir_shader *shader);
>
>  bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask);
>
> +void anv_nir_lower_ycbcr_textures(nir_shader *shader,
> +  struct anv_pipeline *pipeline);
> +
>  void anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
> nir_shader *shader,
> struct brw_stage_prog_data *prog_data,
> diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> index 428cfdf42d1..7cd28debe09 100644
> --- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> +++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
> @@ -131,7 +131,7 @@ lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
>  static void
>  lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
>  unsigned *const_index, unsigned hw_binding_size,
> -nir_tex_src_type src_type,
> +nir_tex_src_type src_type, bool allow_indirect,
>  struct apply_pipeline_layout_state *state)
>  {
> nir_builder *b = >builder;
> @@ -141,6 +141,15 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var
> *deref,
>nir_deref_array *deref_array = nir_deref_as_array(deref->
> deref.child);
>
>if (deref_array->deref_array_type == nir_deref_array_type_indirect)
> {
> + /* From VK_KHR_sampler_ycbcr_conversion:
> +  *
> +  * If sampler Y’CBCR conversion is enabled, the combined image
> +  * sampler must be indexed only by constant integral expressions
> when
> +  * aggregated into arrays in shader code, irrespective of the
> +  * shaderSampledImageArrayDynamicIndexing feature.
> +  */
> + assert(allow_indirect);
> +
>   nir_ssa_def *index =
>  nir_iadd(b, nir_imm_int(b, deref_array->base_offset),
>  nir_ssa_for_src(b, deref_array->indirect, 1));
> @@ -150,7 +159,6 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var
> *deref,
>
>   nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
> tex->num_srcs + 1);
> -
>

Spurrious change?


>   for (unsigned i = 0; i < tex->num_srcs; i++) {
>  new_srcs[i].src_type = tex->src[i].src_type;
>  nir_instr_move_src(>instr, _srcs[i].src,
> >src[i].src);
> @@ -186,6 +194,46 @@ cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var
> *deref)
> nir_instr_rewrite_src(>instr, _array->indirect,
> NIR_SRC_INIT);
>  }
>
> +static bool
> +has_tex_src_plane(nir_tex_instr *tex)
> +{
> +   for (unsigned i = 0; i < tex->num_srcs; i++) {
> +  if (tex->src[i].src_type == nir_tex_src_plane)
> + return true;
> +   }
> +
> +   return false;
> +}
> +
> +static uint32_t
> +extract_tex_src_plane(nir_tex_instr *tex)
> +{
> +   nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src, tex->num_srcs
> - 1);
> +   unsigned plane = 0;
> +
> +   for (unsigned i = 0, w = 0; i < tex->num_srcs; i++) {
> +  if (tex->src[i].src_type == nir_tex_src_plane) {
> + nir_const_value *const_plane =
> +nir_src_as_const_value(tex->src[i].src);
> +
> + /* Our color conversion lowering pass 

Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Chad Versace]

On Tue 03 Oct 2017, Jason Ekstrand wrote:
> 
> On Tue, Oct 3, 2017 at 3:18 PM, Lionel Landwerlin <[1]
> lionel.g.landwer...@intel.com> wrote:
> 
> On 03/10/17 21:21, Chad Versace wrote:
> 
> On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> 
> On 03/10/17 19:13, Jason Ekstrand wrote:
> 
>      +1 to static inline
> 
> Done locally.
> 
> Cool. Waiting to see it appear in wip/djeath/ycbcr_conversion.
> 
> 
> Ah...
> I didn't actually test that (with all the other commits on top).
> 
> Unfortunately that's breaking a bit the way we index formats :
> 
> [4]https://github.com/djdeath/mesa/blob/wip/djdeath/ycbcr_conversion/src/
> intel/vulkan/anv_formats.c#L49
> 
> 
> Right... That's a bummer.  Macros it is, I guess.

Fair enough. But please make the macros uppercase, so no one is hurt by
the multiple evaluation.
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Re: [Mesa-dev] [PATCH v2 05/11] anv: modify the internal concept of format to express multiple planes

[Jason Ekstrand]

I made some comments on v1 of this patch which appear to have gone
unanswered.  The two I think are important are

 1) Naming.  Should it be plane_format or format_plane?  I think I mildly
prefer the later but coulbe be confinced.
 2) I don't think anv_get_isl_format needs to be renamed.  It already takes
an aspect and does planar-like things and you aren't adding any parameters
here.

On Tue, Oct 3, 2017 at 9:29 AM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> A given Vulkan format can now be decomposed into a set of planes. We
> now use 'struct anv_format_plane' to represent the format of those
> planes.
>
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/vulkan/anv_blorp.c |  31 +--
>  src/intel/vulkan/anv_formats.c   | 505 --
> -
>  src/intel/vulkan/anv_image.c |  27 ++-
>  src/intel/vulkan/anv_private.h   |  54 -
>  src/intel/vulkan/genX_pipeline.c |  14 +-
>  5 files changed, 351 insertions(+), 280 deletions(-)
>
> diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
> index 8dead1d87a8..72f482625aa 100644
> --- a/src/intel/vulkan/anv_blorp.c
> +++ b/src/intel/vulkan/anv_blorp.c
> @@ -323,8 +323,9 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
>}
>
>const enum isl_format buffer_format =
> - anv_get_isl_format(_buffer->device->info,
> anv_image->vk_format,
> -aspect, VK_IMAGE_TILING_LINEAR);
> + anv_get_isl_plane_format(_buffer->device->info,
> +  anv_image->vk_format,
> +  aspect, VK_IMAGE_TILING_LINEAR);
>
>const VkExtent3D bufferImageExtent = {
>   .width  = pRegions[r].bufferRowLength ?
> @@ -459,12 +460,12 @@ void anv_CmdBlitImage(
>get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
> dst_image->aux_usage, );
>
> -  struct anv_format src_format =
> - anv_get_format(_buffer->device->info, src_image->vk_format,
> -src_res->aspectMask, src_image->tiling);
> -  struct anv_format dst_format =
> - anv_get_format(_buffer->device->info, dst_image->vk_format,
> -dst_res->aspectMask, dst_image->tiling);
> +  struct anv_format_plane src_format =
> + anv_get_plane_format(_buffer->device->info,
> src_image->vk_format,
> +  src_res->aspectMask, src_image->tiling);
> +  struct anv_format_plane dst_format =
> + anv_get_plane_format(_buffer->device->info,
> dst_image->vk_format,
> +  dst_res->aspectMask, dst_image->tiling);
>
>unsigned dst_start, dst_end;
>if (dst_image->type == VK_IMAGE_TYPE_3D) {
> @@ -758,9 +759,9 @@ void anv_CmdClearColorImage(
>
>assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
>
> -  struct anv_format src_format =
> - anv_get_format(_buffer->device->info, image->vk_format,
> -VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
> +  struct anv_format_plane src_format =
> + anv_get_plane_format(_buffer->device->info,
> image->vk_format,
> +  VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
>
>unsigned base_layer = pRanges[r].baseArrayLayer;
>unsigned layer_count = anv_get_layerCount(image, [r]);
> @@ -974,10 +975,10 @@ clear_depth_stencil_attachment(struct
> anv_cmd_buffer *cmd_buffer,
>
> enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
> if (clear_depth) {
> -  depth_format = anv_get_isl_format(_buffer->device->info,
> -pass_att->format,
> -VK_IMAGE_ASPECT_DEPTH_BIT,
> -VK_IMAGE_TILING_OPTIMAL);
> +  depth_format = anv_get_isl_plane_format(_buffer->device->info,
> +  pass_att->format,
> +  VK_IMAGE_ASPECT_DEPTH_BIT,
> +  VK_IMAGE_TILING_OPTIMAL);
> }
>
> uint32_t binding_table;
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> formats.c
> index 71824256b25..8dd87133c0c 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -44,14 +44,33 @@
>  #define BGRA _ISL_SWIZZLE(BLUE, GREEN, RED, ALPHA)
>  #define RGB1 _ISL_SWIZZLE(RED, GREEN, BLUE, ONE)
>
> -#define swiz_fmt(__vk_fmt, __hw_fmt, __swizzle) \
> -   [__vk_fmt] = { \
> -  .isl_format = __hw_fmt, \
> -  .swizzle = __swizzle, \
> +#define _fmt(__hw_fmt, __swizzle) \
> +   { .isl_format = __hw_fmt, \
> + .swizzle = __swizzle }
> +
> +#define swiz_fmt1(__vk_fmt, __hw_fmt, __swizzle) \
> +   [vk_enum_offset(__vk_fmt)] = { \
> +  .planes = { \
> +  { .isl_format = __hw_fmt, .swizzle = __swizzle }, \

Re: [Mesa-dev] [PATCH 4/4] util: include string.h in u_string.h

[Charmaine Lee]

For the series, Reviewed-by: Charmaine Lee 

From: Brian Paul 
Sent: Tuesday, October 3, 2017 1:04:16 PM
To: mesa-dev@lists.freedesktop.org
Cc: Charmaine Lee; Neha Bhende
Subject: [PATCH 4/4] util: include string.h in u_string.h

To fix MinGW compiler warning about missing strlen() prototype.
Not sure how I missed this when fixing the malloc() / stdlib.h issue.
---
 src/util/u_string.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/util/u_string.h b/src/util/u_string.h
index 5a2a3e9..fa0241e 100644
--- a/src/util/u_string.h
+++ b/src/util/u_string.h
@@ -41,6 +41,7 @@
 #include 
 #include 
 #include 
+#include 

 #include "util/macros.h" // PRINTFLIKE

--
1.9.1

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[Mesa-dev] [PATCH] egl/wayland: restore WAYLAND_CLIENT_CFLAGS

[Marek Olšák]

From: Slava Grigorev 

that is required to include wayland-egl.h header file if it is not
in /usr/include

Signed-off-by: Slava Grigorev 
Signed-off-by: Marek Olšák 
---
 src/egl/wayland/wayland-egl/Makefile.am | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/src/egl/wayland/wayland-egl/Makefile.am 
b/src/egl/wayland/wayland-egl/Makefile.am
index 08a6768..7dde955 100644
--- a/src/egl/wayland/wayland-egl/Makefile.am
+++ b/src/egl/wayland/wayland-egl/Makefile.am
@@ -1,15 +1,16 @@
 pkgconfigdir = $(libdir)/pkgconfig
 pkgconfig_DATA = wayland-egl.pc
 
 AM_CFLAGS = $(DEFINES) \
-   $(VISIBILITY_CFLAGS)
+   $(VISIBILITY_CFLAGS) \
+   $(WAYLAND_CLIENT_CFLAGS)
 
 lib_LTLIBRARIES = libwayland-egl.la
 noinst_HEADERS = wayland-egl-backend.h
 libwayland_egl_la_SOURCES = wayland-egl.c
 libwayland_egl_la_LDFLAGS = \
-no-undefined \
-version-info 1 \
$(GC_SECTIONS) \
$(LD_NO_UNDEFINED)
 
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Jason Ekstrand]

On Tue, Oct 3, 2017 at 3:18 PM, Lionel Landwerlin <
lionel.g.landwer...@intel.com> wrote:

> On 03/10/17 21:21, Chad Versace wrote:
>
>> On Tue 03 Oct 2017, Lionel Landwerlin wrote:
>>
>>> On 03/10/17 19:13, Jason Ekstrand wrote:
>>>
>>>  On Tue, Oct 3, 2017 at 9:43 AM, Chad Versace <[1]
>>> chadvers...@chromium.org>
>>>  wrote:
>>>
>>>  On Tue 03 Oct 2017, Lionel Landwerlin wrote:
>>>  > v2: Simplify offset enum computation (Jason)
>>>  >
>>>  > Signed-off-by: Lionel Landwerlin <[2]
>>> lionel.g.landwer...@intel.com>
>>>  > ---
>>>  >  src/vulkan/util/vk_util.h | 6 ++
>>>  >  1 file changed, 6 insertions(+)
>>>  >
>>>  > diff --git a/src/vulkan/util/vk_util.h
>>> b/src/vulkan/util/vk_util.h
>>>  > index 2ed601f881e..8c8cb64d513 100644
>>>  > --- a/src/vulkan/util/vk_util.h
>>>  > +++ b/src/vulkan/util/vk_util.h
>>>  > @@ -199,4 +199,10 @@ __vk_find_struct(void *start,
>>> VkStructureType
>>>  sType)
>>>  >
>>>  >  uint32_t vk_get_driver_version(void);
>>>  >
>>>  > +#define VK_EXT_OFFSET (10UL)
>>>  > +#define vk_enum_extension(__enum) \
>>>  > +   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET)
>>> /
>>>  1000UL) + 1) : 0)
>>>  > +#define vk_enum_offset(__enum) \
>>>  > +   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))
>>>
>>>  The macro functions, when called, look like regular functions
>>> due to
>>>  being lowercase. But they don't behave like functions; their
>>> arguments
>>>  suffer from the multiple evaluation disease.
>>>
>>>  Please rename the macros to be all uppercase, so callers'
>>> expectations
>>>  will be set correctly. Or, even better, define them as inline
>>>  functions.
>>>
>>>
>>>  +1 to static inline
>>>
>>> Done locally.
>>>
>> Cool. Waiting to see it appear in wip/djeath/ycbcr_conversion.
>>
>
> Ah...
> I didn't actually test that (with all the other commits on top).
>
> Unfortunately that's breaking a bit the way we index formats :
>
> https://github.com/djdeath/mesa/blob/wip/djdeath/ycbcr_conve
> rsion/src/intel/vulkan/anv_formats.c#L49


Right... That's a bummer.  Macros it is, I guess.
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Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Lionel Landwerlin]

On 03/10/17 21:21, Chad Versace wrote:

On Tue 03 Oct 2017, Lionel Landwerlin wrote:

On 03/10/17 19:13, Jason Ekstrand wrote:

 On Tue, Oct 3, 2017 at 9:43 AM, Chad Versace <[1]chadvers...@chromium.org>
 wrote:

 On Tue 03 Oct 2017, Lionel Landwerlin wrote:
 > v2: Simplify offset enum computation (Jason)
 >
 > Signed-off-by: Lionel Landwerlin <[2]lionel.g.landwer...@intel.com>
 > ---
 >  src/vulkan/util/vk_util.h | 6 ++
 >  1 file changed, 6 insertions(+)
 >
 > diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
 > index 2ed601f881e..8c8cb64d513 100644
 > --- a/src/vulkan/util/vk_util.h
 > +++ b/src/vulkan/util/vk_util.h
 > @@ -199,4 +199,10 @@ __vk_find_struct(void *start, VkStructureType
 sType)
 >
 >  uint32_t vk_get_driver_version(void);
 >
 > +#define VK_EXT_OFFSET (10UL)
 > +#define vk_enum_extension(__enum) \
 > +   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET) /
 1000UL) + 1) : 0)
 > +#define vk_enum_offset(__enum) \
 > +   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))

 The macro functions, when called, look like regular functions due to
 being lowercase. But they don't behave like functions; their arguments
 suffer from the multiple evaluation disease.

 Please rename the macros to be all uppercase, so callers' expectations
 will be set correctly. Or, even better, define them as inline
 functions.


 +1 to static inline

Done locally.

Cool. Waiting to see it appear in wip/djeath/ycbcr_conversion.


Ah...
I didn't actually test that (with all the other commits on top).

Unfortunately that's breaking a bit the way we index formats :

https://github.com/djdeath/mesa/blob/wip/djdeath/ycbcr_conversion/src/intel/vulkan/anv_formats.c#L49



References:

[1] mailto:chadvers...@chromium.org
[2] mailto:lionel.g.landwer...@intel.com
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Re: [Mesa-dev] [PATCH] radv: lower ffma in nir.

[Roland Scheidegger]

Am 03.10.2017 um 22:58 schrieb Dave Airlie:
> From: Dave Airlie 
> 
> So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
> mad operation, and the fma hw opcode on AMD hw is issued like a double
> opcode so is slower. Also the radeonsi stack does this.
> 
> This appears to improve performance on a number of games from Feral,
> and thanks to Feral for noticing the problem.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_shader.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index ca0ad2d..a37345b 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -64,6 +64,7 @@ static const struct nir_shader_compiler_options nir_options 
> = {
>   .lower_unpack_unorm_4x8 = true,
>   .lower_extract_byte = true,
>   .lower_extract_word = true,
> + .lower_ffma = true,
>   .max_unroll_iterations = 32
>  };
>  
> 

Looks like quite a misnomer to me in spir-v then - if it is allowed to
be unfused that's more commonly called fmuladd. After all the "f" in fma
is there for "fused"...

But anyway, I don't have anything against the patch if spir-v allows it...

Roland
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Re: [Mesa-dev] [PATCH] radv: lower ffma in nir.

[Matt Arsenault]

> On Oct 3, 2017, at 13:58, Dave Airlie  wrote:
> 
> From: Dave Airlie 
> 
> So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
> mad operation, and the fma hw opcode on AMD hw is issued like a double
> opcode so is slower. Also the radeonsi stack does this.
> 
> This appears to improve performance on a number of games from Feral,
> and thanks to Feral for noticing the problem.
> 
> Signed-off-by: Dave Airlie 
> ---
> src/amd/vulkan/radv_shader.c | 1 +
> 1 file changed, 1 insertion(+)
> 
> diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
> index ca0ad2d..a37345b 100644
> --- a/src/amd/vulkan/radv_shader.c
> +++ b/src/amd/vulkan/radv_shader.c
> @@ -64,6 +64,7 @@ static const struct nir_shader_compiler_options nir_options 
> = {
>   .lower_unpack_unorm_4x8 = true,
>   .lower_extract_byte = true,
>   .lower_extract_word = true,
> + .lower_ffma = true,
>   .max_unroll_iterations = 32
> };
> 
> -- 
> 2.9.5
> 
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If it doesn’t matter this should emit llvm.fmuladd. The backend decides what’s 
best to do based on the specific target whether it’s an FMA or MAD.

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[Mesa-dev] [PATCH] radv: lower ffma in nir.

[Dave Airlie]

From: Dave Airlie 

So it appears the Vulkan SPIR-V fma opcode can be equivalent to a
mad operation, and the fma hw opcode on AMD hw is issued like a double
opcode so is slower. Also the radeonsi stack does this.

This appears to improve performance on a number of games from Feral,
and thanks to Feral for noticing the problem.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_shader.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/amd/vulkan/radv_shader.c b/src/amd/vulkan/radv_shader.c
index ca0ad2d..a37345b 100644
--- a/src/amd/vulkan/radv_shader.c
+++ b/src/amd/vulkan/radv_shader.c
@@ -64,6 +64,7 @@ static const struct nir_shader_compiler_options nir_options = 
{
.lower_unpack_unorm_4x8 = true,
.lower_extract_byte = true,
.lower_extract_word = true,
+   .lower_ffma = true,
.max_unroll_iterations = 32
 };
 
-- 
2.9.5

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[Mesa-dev] [PATCH 2/2] swr/rast: use proper alignment for debug transposedPrims

[Tim Rowley]

Causing a crash in ParaView waveletcontour.py test when
_DEBUG defined due to vector aligned copy with unaligned
address.
---
 src/gallium/drivers/swr/rasterizer/core/clip.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/drivers/swr/rasterizer/core/clip.h 
b/src/gallium/drivers/swr/rasterizer/core/clip.h
index cde5261521..e9a410daa3 100644
--- a/src/gallium/drivers/swr/rasterizer/core/clip.h
+++ b/src/gallium/drivers/swr/rasterizer/core/clip.h
@@ -561,7 +561,7 @@ public:
 
 #if defined(_DEBUG)
 // TODO: need to increase stack size, allocating SIMD16-widened 
transposedPrims causes stack overflow in debug builds
-SIMDVERTEX_T *transposedPrims = 
reinterpret_cast(malloc(sizeof(SIMDVERTEX_T) * 
2));
+SIMDVERTEX_T *transposedPrims = 
reinterpret_cast(AlignedMalloc(sizeof(SIMDVERTEX_T) * 2, 64));
 
 #else
 SIMDVERTEX_T transposedPrims[2];
@@ -667,7 +667,7 @@ public:
 }
 
 #if defined(_DEBUG)
-free(transposedPrims);
+AlignedFree(transposedPrims);
 
 #endif
 // update global pipeline stat
-- 
2.11.0

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[Mesa-dev] [PATCH 1/2] configure.ac: add _DEBUG to strip_unwanted_llvm_flags

[Tim Rowley]

Assert-enabled builds of llvm add _DEBUG to the LLVM_CFLAGS.

This was causing a crash with swr running the ParaView
waveletcontour.py test, due to a bug in our _DEBUG code.
---
 configure.ac | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configure.ac b/configure.ac
index 903a3979d4..b2768f46c0 100644
--- a/configure.ac
+++ b/configure.ac
@@ -987,6 +987,7 @@ strip_unwanted_llvm_flags() {
 echo " `$1` " | sed -E \
 -e 's/[[[:space:]]]+-m[[^[:space:]]]*//g' \
 -e 's/[[[:space:]]]+-DNDEBUG[[[:space:]]]/ /g' \
+-e 's/[[[:space:]]]+-D_DEBUG[[[:space:]]]/ /g' \
 -e 's/[[[:space:]]]+-D_GNU_SOURCE[[[:space:]]]/ /g' \
 -e 's/[[[:space:]]]+-pedantic[[[:space:]]]/ /g' \
 -e 's/[[[:space:]]]+-W[[^[:space:]]]*//g' \
-- 
2.11.0

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Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Chad Versace]

On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> On 03/10/17 19:13, Jason Ekstrand wrote:
> 
> On Tue, Oct 3, 2017 at 9:43 AM, Chad Versace <[1]chadvers...@chromium.org>
> wrote:
> 
> On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> > v2: Simplify offset enum computation (Jason)
> >
> > Signed-off-by: Lionel Landwerlin <[2]lionel.g.landwer...@intel.com>
> > ---
> >  src/vulkan/util/vk_util.h | 6 ++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
> > index 2ed601f881e..8c8cb64d513 100644
> > --- a/src/vulkan/util/vk_util.h
> > +++ b/src/vulkan/util/vk_util.h
> > @@ -199,4 +199,10 @@ __vk_find_struct(void *start, VkStructureType
> sType)
> >
> >  uint32_t vk_get_driver_version(void);
> >
> > +#define VK_EXT_OFFSET (10UL)
> > +#define vk_enum_extension(__enum) \
> > +   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET) /
> 1000UL) + 1) : 0)
> > +#define vk_enum_offset(__enum) \
> > +   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))
> 
> The macro functions, when called, look like regular functions due to
> being lowercase. But they don't behave like functions; their arguments
> suffer from the multiple evaluation disease.
> 
> Please rename the macros to be all uppercase, so callers' expectations
> will be set correctly. Or, even better, define them as inline
> functions.
> 
> 
> +1 to static inline
> 
> Done locally.

Cool. Waiting to see it appear in wip/djeath/ycbcr_conversion.
> 
> 
> References:
> 
> [1] mailto:chadvers...@chromium.org
> [2] mailto:lionel.g.landwer...@intel.com

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[Mesa-dev] [PATCH 4/4] util: include string.h in u_string.h

[Brian Paul]

To fix MinGW compiler warning about missing strlen() prototype.
Not sure how I missed this when fixing the malloc() / stdlib.h issue.
---
 src/util/u_string.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/util/u_string.h b/src/util/u_string.h
index 5a2a3e9..fa0241e 100644
--- a/src/util/u_string.h
+++ b/src/util/u_string.h
@@ -41,6 +41,7 @@
 #include 
 #include 
 #include 
+#include 
 
 #include "util/macros.h" // PRINTFLIKE
 
-- 
1.9.1

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[Mesa-dev] [PATCH 2/4] mesa: silence 'variable may be used uninitialized' warning in teximage.c

[Brian Paul]

Found with MinGW optimized build.
---
 src/mesa/main/teximage.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/mesa/main/teximage.c b/src/mesa/main/teximage.c
index 0a3025a..bb22b9a 100644
--- a/src/mesa/main/teximage.c
+++ b/src/mesa/main/teximage.c
@@ -4885,7 +4885,7 @@ compressed_tex_sub_image(unsigned dim, GLenum target, 
GLuint texture,
  const GLvoid *data, bool dsa, bool no_error,
  const char *caller)
 {
-   struct gl_texture_object *texObj;
+   struct gl_texture_object *texObj = NULL;
struct gl_texture_image *texImage;
 
GET_CURRENT_CONTEXT(ctx);
-- 
1.9.1

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[Mesa-dev] [PATCH 3/4] llvmpipe: silence 'variable may be used uninitialized' warnings

[Brian Paul]

---
 src/gallium/auxiliary/gallivm/lp_bld_format_aos.c | 2 +-
 src/gallium/drivers/llvmpipe/lp_state_fs.c| 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c 
b/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
index 2f72385..36dedba 100644
--- a/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
+++ b/src/gallium/auxiliary/gallivm/lp_bld_format_aos.c
@@ -532,7 +532,7 @@ lp_build_fetch_rgba_aos(struct gallivm_state *gallivm,
util_format_fits_8unorm(format_desc) &&
type.width == 8 && type.norm == 1 && type.sign == 0 &&
type.fixed == 0 && type.floating == 0) {
-  LLVMValueRef packed, res, chans[4], rgba[4];
+  LLVMValueRef packed, res = NULL, chans[4], rgba[4];
   LLVMTypeRef dst_vec_type, conv_vec_type;
   struct lp_type fetch_type, conv_type;
   struct lp_build_context bld_conv;
diff --git a/src/gallium/drivers/llvmpipe/lp_state_fs.c 
b/src/gallium/drivers/llvmpipe/lp_state_fs.c
index 9a43f01..05984b3 100644
--- a/src/gallium/drivers/llvmpipe/lp_state_fs.c
+++ b/src/gallium/drivers/llvmpipe/lp_state_fs.c
@@ -2777,7 +2777,7 @@ generate_variant(struct llvmpipe_context *lp,
  const struct lp_fragment_shader_variant_key *key)
 {
struct lp_fragment_shader_variant *variant;
-   const struct util_format_description *cbuf0_format_desc;
+   const struct util_format_description *cbuf0_format_desc = NULL;
boolean fullcolormask;
char module_name[64];
 
-- 
1.9.1

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[Mesa-dev] [PATCH 1/4] mesa: silence 'variable may be used uninitialized' warning in bufferobj.c

[Brian Paul]

Found with MinGW optimized build.
---
 src/mesa/main/bufferobj.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/mesa/main/bufferobj.c b/src/mesa/main/bufferobj.c
index 2da2128..0b98483 100644
--- a/src/mesa/main/bufferobj.c
+++ b/src/mesa/main/bufferobj.c
@@ -3287,6 +3287,7 @@ get_map_buffer_access_flags(struct gl_context *ctx, 
GLenum access,
   *flags = GL_MAP_READ_BIT | GL_MAP_WRITE_BIT;
   return _mesa_is_desktop_gl(ctx);
default:
+  *flags = 0;
   return false;
}
 }
-- 
1.9.1

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Re: [Mesa-dev] [PATCH 14/15] build: Remove HAVE_DLOPEN

[Rob Herring]

On Mon, Oct 2, 2017 at 1:59 AM, Matt Turner  wrote:
> ---
>  Android.common.mk   | 1 -

Reviewed-by: Rob Herring 

>  configure.ac| 4 ++--
>  meson.build | 1 -
>  src/mesa/SConscript | 4 
>  4 files changed, 2 insertions(+), 8 deletions(-)
>
> diff --git a/Android.common.mk b/Android.common.mk
> index 4d5daf8e9d..483f6c5be2 100644
> --- a/Android.common.mk
> +++ b/Android.common.mk
> @@ -64,7 +64,6 @@ LOCAL_CFLAGS += \
> -DHAVE___BUILTIN_UNREACHABLE \
> -DHAVE_PTHREAD=1 \
> -DHAVE_DLADDR \
> -   -DHAVE_DLOPEN \
> -DHAVE_DL_ITERATE_PHDR \
> -DMAJOR_IN_SYSMACROS \
> -fvisibility=hidden \
> diff --git a/configure.ac b/configure.ac
> index cfc97d9f06..903a3979d4 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -831,9 +831,9 @@ AC_LINK_IFELSE([AC_LANG_SOURCE([[
>
>  dnl Check to see if dlopen is in default libraries (like Solaris, which
>  dnl has it in libc), or if libdl is needed to get it.
> -AC_CHECK_FUNC([dlopen], [DEFINES="$DEFINES -DHAVE_DLOPEN"],
> +AC_CHECK_FUNC([dlopen], [],
>  [AC_CHECK_LIB([dl], [dlopen],
> -   [DEFINES="$DEFINES -DHAVE_DLOPEN"; DLOPEN_LIBS="-ldl"])])
> +   [DLOPEN_LIBS="-ldl"])])
>  AC_SUBST([DLOPEN_LIBS])
>
>  dnl Check if that library also has dladdr
> diff --git a/meson.build b/meson.build
> index 5353a41748..f1613ffcab 100644
> --- a/meson.build
> +++ b/meson.build
> @@ -260,7 +260,6 @@ if cc.has_function('dlopen')
>  else
>dep_dl = cc.find_library('dl')
>  endif
> -pre_args += '-DHAVE_DLOPEN'
>
>  if not cc.has_function('dladdr', dependencies : dep_dl)
>error('dl library doesn\'t have dladdr')
> diff --git a/src/mesa/SConscript b/src/mesa/SConscript
> index b63e15a3f0..ba98ad4323 100644
> --- a/src/mesa/SConscript
> +++ b/src/mesa/SConscript
> @@ -31,10 +31,6 @@ if env['platform'] == 'windows':
>  if not env['gles']:
>  # prevent _glapi_* from being declared __declspec(dllimport)
>  env.Append(CPPDEFINES = ['_GLAPI_NO_EXPORTS'])
> -else:
> -env.Append(CPPDEFINES = [
> -('HAVE_DLOPEN', '1'),
> -])
>
>  # parse Makefile.sources
>  source_lists = env.ParseSourceList('Makefile.sources')
> --
> 2.13.6
>
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Re: [Mesa-dev] [PATCH 04/10] radv: do not rebind the same pipeline when doing meta operations

[Samuel Pitoiset]

On 10/03/2017 08:55 PM, Bas Nieuwenhuizen wrote:

Doesn't it make more sense to do the check in radv_CmdBindPipeline?


It does.



On Tue, Oct 3, 2017 at 8:52 PM, Samuel Pitoiset
 wrote:

This might save some usless state changes, and it improves
consistency with the other meta operations.

Signed-off-by: Samuel Pitoiset 
---
  src/amd/vulkan/radv_meta_buffer.c | 18 --
  src/amd/vulkan/radv_meta_resolve_fs.c |  7 +--
  2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_buffer.c 
b/src/amd/vulkan/radv_meta_buffer.c
index ea11ed18c4..22be07a2ee 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -295,9 +295,12 @@ static void fill_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
 .size = size
 };

-   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
-VK_PIPELINE_BIND_POINT_COMPUTE,
-device->meta_state.buffer.fill_pipeline);
+   if (cmd_buffer->state.compute_pipeline !=
+   radv_pipeline_from_handle(device->meta_state.buffer.fill_pipeline)) 
{
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+VK_PIPELINE_BIND_POINT_COMPUTE,
+device->meta_state.buffer.fill_pipeline);
+   }

 radv_meta_push_descriptor_set(cmd_buffer, 
VK_PIPELINE_BIND_POINT_COMPUTE,
   device->meta_state.buffer.fill_p_layout,
@@ -352,9 +355,12 @@ static void copy_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
 .size = size
 };

-   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
-VK_PIPELINE_BIND_POINT_COMPUTE,
-device->meta_state.buffer.copy_pipeline);
+   if (cmd_buffer->state.compute_pipeline !=
+   radv_pipeline_from_handle(device->meta_state.buffer.copy_pipeline)) 
{
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+VK_PIPELINE_BIND_POINT_COMPUTE,
+device->meta_state.buffer.copy_pipeline);
+   }

 radv_meta_push_descriptor_set(cmd_buffer, 
VK_PIPELINE_BIND_POINT_COMPUTE,
   device->meta_state.buffer.copy_p_layout,
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c 
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 50d5ed7d5a..56b6e0c29a 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -418,8 +418,11 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
 unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
 VkPipeline pipeline_h = 
device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];

-   radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
-pipeline_h);
+   if (cmd_buffer->state.pipeline != 
radv_pipeline_from_handle(pipeline_h)) {
+   radv_CmdBindPipeline(cmd_buffer_h,
+VK_PIPELINE_BIND_POINT_GRAPHICS,
+pipeline_h);
+   }

 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, 
&(VkViewport) {
 .x = dest_offset->x,
--
2.14.2

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Re: [Mesa-dev] [PATCH 04/10] radv: do not rebind the same pipeline when doing meta operations

[Bas Nieuwenhuizen]

Doesn't it make more sense to do the check in radv_CmdBindPipeline?

On Tue, Oct 3, 2017 at 8:52 PM, Samuel Pitoiset
 wrote:
> This might save some usless state changes, and it improves
> consistency with the other meta operations.
>
> Signed-off-by: Samuel Pitoiset 
> ---
>  src/amd/vulkan/radv_meta_buffer.c | 18 --
>  src/amd/vulkan/radv_meta_resolve_fs.c |  7 +--
>  2 files changed, 17 insertions(+), 8 deletions(-)
>
> diff --git a/src/amd/vulkan/radv_meta_buffer.c 
> b/src/amd/vulkan/radv_meta_buffer.c
> index ea11ed18c4..22be07a2ee 100644
> --- a/src/amd/vulkan/radv_meta_buffer.c
> +++ b/src/amd/vulkan/radv_meta_buffer.c
> @@ -295,9 +295,12 @@ static void fill_buffer_shader(struct radv_cmd_buffer 
> *cmd_buffer,
> .size = size
> };
>
> -   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
> -VK_PIPELINE_BIND_POINT_COMPUTE,
> -device->meta_state.buffer.fill_pipeline);
> +   if (cmd_buffer->state.compute_pipeline !=
> +   
> radv_pipeline_from_handle(device->meta_state.buffer.fill_pipeline)) {
> +   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
> +VK_PIPELINE_BIND_POINT_COMPUTE,
> +device->meta_state.buffer.fill_pipeline);
> +   }
>
> radv_meta_push_descriptor_set(cmd_buffer, 
> VK_PIPELINE_BIND_POINT_COMPUTE,
>   device->meta_state.buffer.fill_p_layout,
> @@ -352,9 +355,12 @@ static void copy_buffer_shader(struct radv_cmd_buffer 
> *cmd_buffer,
> .size = size
> };
>
> -   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
> -VK_PIPELINE_BIND_POINT_COMPUTE,
> -device->meta_state.buffer.copy_pipeline);
> +   if (cmd_buffer->state.compute_pipeline !=
> +   
> radv_pipeline_from_handle(device->meta_state.buffer.copy_pipeline)) {
> +   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
> +VK_PIPELINE_BIND_POINT_COMPUTE,
> +device->meta_state.buffer.copy_pipeline);
> +   }
>
> radv_meta_push_descriptor_set(cmd_buffer, 
> VK_PIPELINE_BIND_POINT_COMPUTE,
>   device->meta_state.buffer.copy_p_layout,
> diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c 
> b/src/amd/vulkan/radv_meta_resolve_fs.c
> index 50d5ed7d5a..56b6e0c29a 100644
> --- a/src/amd/vulkan/radv_meta_resolve_fs.c
> +++ b/src/amd/vulkan/radv_meta_resolve_fs.c
> @@ -418,8 +418,11 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
> unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
> VkPipeline pipeline_h = 
> device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
>
> -   radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
> -pipeline_h);
> +   if (cmd_buffer->state.pipeline != 
> radv_pipeline_from_handle(pipeline_h)) {
> +   radv_CmdBindPipeline(cmd_buffer_h,
> +VK_PIPELINE_BIND_POINT_GRAPHICS,
> +pipeline_h);
> +   }
>
> radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, 
> &(VkViewport) {
> .x = dest_offset->x,
> --
> 2.14.2
>
> ___
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> mesa-dev@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/mesa-dev
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[Mesa-dev] [PATCH 03/10] radv: remove unused RADV_META_VERTEX_BINDING_COUNT

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.h | 2 --
 1 file changed, 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 20b4498ab3..252514540e 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -33,8 +33,6 @@
 extern "C" {
 #endif
 
-#define RADV_META_VERTEX_BINDING_COUNT 2
-
 struct radv_meta_saved_state {
struct radv_descriptor_set *old_descriptor_set0;
struct radv_pipeline *old_pipeline;
-- 
2.14.2

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[Mesa-dev] [PATCH 02/10] radv: select the pipeline outside of the loop when decompressing htile

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta_decompress.c | 24 
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_decompress.c 
b/src/amd/vulkan/radv_meta_decompress.c
index c68be27f1f..8abbcb6723 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -315,6 +315,7 @@ static void radv_process_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
uint32_t samples = image->info.samples;
uint32_t samples_log2 = ffs(samples) - 1;
struct radv_meta_state *meta_state = _buffer->device->meta_state;
+   VkPipeline pipeline_h;
 
if (!image->surface.htile_size)
return;
@@ -322,6 +323,17 @@ static void radv_process_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
 
radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer);
 
+   switch (op) {
+   case DEPTH_DECOMPRESS:
+   pipeline_h = 
meta_state->depth_decomp[samples_log2].decompress_pipeline;
+   break;
+   case DEPTH_RESUMMARIZE:
+   pipeline_h = 
meta_state->depth_decomp[samples_log2].resummarize_pipeline;
+   break;
+   default:
+   unreachable("unknown operation");
+   }
+
for (uint32_t layer = 0; layer < radv_get_layerCount(image, 
subresourceRange); layer++) {
struct radv_image_view iview;
 
@@ -376,18 +388,6 @@ static void radv_process_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
   },
   VK_SUBPASS_CONTENTS_INLINE);
 
-   VkPipeline pipeline_h;
-   switch (op) {
-   case DEPTH_DECOMPRESS:
-   pipeline_h = 
meta_state->depth_decomp[samples_log2].decompress_pipeline;
-   break;
-   case DEPTH_RESUMMARIZE:
-   pipeline_h = 
meta_state->depth_decomp[samples_log2].resummarize_pipeline;
-   break;
-   default:
-   unreachable("unknown operation");
-   }
-
emit_depth_decomp(cmd_buffer, &(VkExtent2D){width, height}, 
pipeline_h);
radv_CmdEndRenderPass(cmd_buffer_h);
 
-- 
2.14.2

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[Mesa-dev] [PATCH 07/10] radv: merge radv_meta_{save, restore}_pass() with RADV_META_SAVE_PASS

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.c| 40 +++
 src/amd/vulkan/radv_meta.h|  8 ---
 src/amd/vulkan/radv_meta_decompress.c |  6 ++
 src/amd/vulkan/radv_meta_fast_clear.c |  7 +++---
 4 files changed, 22 insertions(+), 39 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index d6966ed516..83932a84a3 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -61,6 +61,14 @@ radv_meta_save_novertex(struct radv_meta_saved_state *state,
memcpy(state->push_constants, cmd_buffer->push_constants,
   MAX_PUSH_CONSTANTS_SIZE);
}
+
+   if (state->flags & RADV_META_SAVE_PASS) {
+   state->pass = cmd_buffer->state.pass;
+   state->subpass = cmd_buffer->state.subpass;
+   state->framebuffer = cmd_buffer->state.framebuffer;
+   state->attachments = cmd_buffer->state.attachments;
+   state->render_area = cmd_buffer->state.render_area;
+   }
 }
 
 void
@@ -101,30 +109,16 @@ radv_meta_restore(const struct radv_meta_saved_state 
*state,
cmd_buffer->push_constant_stages |= 
VK_SHADER_STAGE_ALL_GRAPHICS |
VK_SHADER_STAGE_COMPUTE_BIT;
}
-}
-
-void
-radv_meta_save_pass(struct radv_meta_saved_pass_state *state,
-const struct radv_cmd_buffer *cmd_buffer)
-{
-   state->pass = cmd_buffer->state.pass;
-   state->subpass = cmd_buffer->state.subpass;
-   state->framebuffer = cmd_buffer->state.framebuffer;
-   state->attachments = cmd_buffer->state.attachments;
-   state->render_area = cmd_buffer->state.render_area;
-}
 
-void
-radv_meta_restore_pass(const struct radv_meta_saved_pass_state *state,
-   struct radv_cmd_buffer *cmd_buffer)
-{
-   cmd_buffer->state.pass = state->pass;
-   cmd_buffer->state.subpass = state->subpass;
-   cmd_buffer->state.framebuffer = state->framebuffer;
-   cmd_buffer->state.attachments = state->attachments;
-   cmd_buffer->state.render_area = state->render_area;
-   if (state->subpass)
-   radv_emit_framebuffer_state(cmd_buffer);
+   if (state->flags & RADV_META_SAVE_PASS) {
+   cmd_buffer->state.pass = state->pass;
+   cmd_buffer->state.subpass = state->subpass;
+   cmd_buffer->state.framebuffer = state->framebuffer;
+   cmd_buffer->state.attachments = state->attachments;
+   cmd_buffer->state.render_area = state->render_area;
+   if (state->subpass)
+   radv_emit_framebuffer_state(cmd_buffer);
+   }
 }
 
 void
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 0befecd043..6500c9118c 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -49,9 +49,7 @@ struct radv_meta_saved_state {
struct radv_scissor_state scissor;
 
char push_constants[128];
-};
 
-struct radv_meta_saved_pass_state {
struct radv_render_pass *pass;
const struct radv_subpass *subpass;
struct radv_attachment_state *attachments;
@@ -100,12 +98,6 @@ void radv_device_finish_meta_resolve_fragment_state(struct 
radv_device *device);
 void radv_meta_restore(const struct radv_meta_saved_state *state,
   struct radv_cmd_buffer *cmd_buffer);
 
-void radv_meta_save_pass(struct radv_meta_saved_pass_state *state,
-const struct radv_cmd_buffer *cmd_buffer);
-
-void radv_meta_restore_pass(const struct radv_meta_saved_pass_state *state,
-   struct radv_cmd_buffer *cmd_buffer);
-
 void radv_meta_save_compute(struct radv_meta_saved_compute_state *state,
const struct radv_cmd_buffer *cmd_buffer,
unsigned push_constant_size);
diff --git a/src/amd/vulkan/radv_meta_decompress.c 
b/src/amd/vulkan/radv_meta_decompress.c
index 3edc1be2f0..6aa833ea23 100644
--- a/src/amd/vulkan/radv_meta_decompress.c
+++ b/src/amd/vulkan/radv_meta_decompress.c
@@ -305,7 +305,6 @@ static void radv_process_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
 enum radv_depth_op op)
 {
struct radv_meta_saved_state saved_state;
-   struct radv_meta_saved_pass_state saved_pass_state;
VkDevice device_h = radv_device_to_handle(cmd_buffer->device);
VkCommandBuffer cmd_buffer_h = radv_cmd_buffer_to_handle(cmd_buffer);
uint32_t width = radv_minify(image->info.width,
@@ -319,10 +318,10 @@ static void radv_process_depth_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
 
if (!image->surface.htile_size)
return;
-   radv_meta_save_pass(_pass_state, cmd_buffer);
 
radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 

[Mesa-dev] [PATCH 10/10] radv: convert all COMPUTE operations to the RADV_META_SAVE_XXX flags

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.c| 31 
 src/amd/vulkan/radv_meta.h| 15 --
 src/amd/vulkan/radv_meta_buffer.c | 17 +++
 src/amd/vulkan/radv_meta_clear.c  | 24 +++-
 src/amd/vulkan/radv_meta_copy.c   | 53 ++-
 src/amd/vulkan/radv_meta_resolve_cs.c | 18 
 src/amd/vulkan/radv_query.c   |  9 --
 7 files changed, 60 insertions(+), 107 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 0b6dee25d9..c56ca78391 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -148,37 +148,6 @@ radv_meta_restore(const struct radv_meta_saved_state 
*state,
}
 }
 
-void
-radv_meta_save_compute(struct radv_meta_saved_compute_state *state,
-   const struct radv_cmd_buffer *cmd_buffer,
-   unsigned push_constant_size)
-{
-   state->old_pipeline = cmd_buffer->state.compute_pipeline;
-   state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
-   state->push_constant_size = push_constant_size;
-
-   if (state->push_constant_size) {
-   memcpy(state->push_constants, cmd_buffer->push_constants,
-  state->push_constant_size);
-   }
-}
-
-void
-radv_meta_restore_compute(const struct radv_meta_saved_compute_state *state,
-  struct radv_cmd_buffer *cmd_buffer)
-{
-   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), 
VK_PIPELINE_BIND_POINT_COMPUTE,
-radv_pipeline_to_handle(state->old_pipeline));
-
-   cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-
-   if (state->push_constant_size) {
-   memcpy(cmd_buffer->push_constants, state->push_constants,
-  state->push_constant_size);
-   cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
-   }
-}
-
 VkImageViewType
 radv_meta_get_view_type(const struct radv_image *image)
 {
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 87ff1babcb..a6dd092097 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -58,14 +58,6 @@ struct radv_meta_saved_state {
VkRect2D render_area;
 };
 
-struct radv_meta_saved_compute_state {
-   struct radv_descriptor_set *old_descriptor_set0;
-   struct radv_pipeline *old_pipeline;
-
-   unsigned push_constant_size;
-   char push_constants[128];
-};
-
 VkResult radv_device_init_meta_clear_state(struct radv_device *device);
 void radv_device_finish_meta_clear_state(struct radv_device *device);
 
@@ -102,13 +94,6 @@ void radv_meta_save(struct radv_meta_saved_state 
*saved_state,
 void radv_meta_restore(const struct radv_meta_saved_state *state,
   struct radv_cmd_buffer *cmd_buffer);
 
-void radv_meta_save_compute(struct radv_meta_saved_compute_state *state,
-   const struct radv_cmd_buffer *cmd_buffer,
-   unsigned push_constant_size);
-
-void radv_meta_restore_compute(const struct radv_meta_saved_compute_state 
*state,
-  struct radv_cmd_buffer *cmd_buffer);
-
 VkImageViewType radv_meta_get_view_type(const struct radv_image *image);
 
 uint32_t radv_meta_get_iview_layer(const struct radv_image *dest_image,
diff --git a/src/amd/vulkan/radv_meta_buffer.c 
b/src/amd/vulkan/radv_meta_buffer.c
index 22be07a2ee..ab9c39a3e6 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -285,9 +285,12 @@ static void fill_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
 {
struct radv_device *device = cmd_buffer->device;
uint64_t block_count = round_up_u64(size, 1024);
-   struct radv_meta_saved_compute_state saved_state;
+   struct radv_meta_saved_state saved_state;
 
-   radv_meta_save_compute(_state, cmd_buffer, 4);
+   radv_meta_save(_state, cmd_buffer,
+  RADV_META_SAVE_COMPUTE |
+  RADV_META_SAVE_CONSTANTS |
+  RADV_META_SAVE_DESCRIPTORS);
 
struct radv_buffer dst_buffer = {
.bo = bo,
@@ -328,7 +331,7 @@ static void fill_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
 
radv_CmdDispatch(radv_cmd_buffer_to_handle(cmd_buffer), block_count, 1, 
1);
 
-   radv_meta_restore_compute(_state, cmd_buffer);
+   radv_meta_restore(_state, cmd_buffer);
 }
 
 static void copy_buffer_shader(struct radv_cmd_buffer *cmd_buffer,
@@ -339,9 +342,11 @@ static void copy_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
 {
struct radv_device *device = cmd_buffer->device;
uint64_t block_count = round_up_u64(size, 1024);
-   struct radv_meta_saved_compute_state saved_state;
+   struct radv_meta_saved_state saved_state;
 
-   

[Mesa-dev] [PATCH 08/10] radv: add radv_meta_save() helper

[Samuel Pitoiset]

And merge radv_meta_save_novertex() with
radv_meta_save_graphics_reset_vport_scissor_novertex().

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.c| 33 -
 src/amd/vulkan/radv_meta.h|  7 +++
 src/amd/vulkan/radv_meta_blit.c   |  8 
 src/amd/vulkan/radv_meta_clear.c  | 27 ---
 src/amd/vulkan/radv_meta_copy.c   | 17 -
 src/amd/vulkan/radv_meta_decompress.c |  6 +++---
 src/amd/vulkan/radv_meta_fast_clear.c |  6 +++---
 src/amd/vulkan/radv_meta_resolve.c|  6 ++
 src/amd/vulkan/radv_meta_resolve_fs.c | 16 
 9 files changed, 55 insertions(+), 71 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 83932a84a3..6972a0b592 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -30,10 +30,9 @@
 #include 
 #include 
 
-static void
-radv_meta_save_novertex(struct radv_meta_saved_state *state,
-   const struct radv_cmd_buffer *cmd_buffer,
-   uint32_t flags)
+void
+radv_meta_save(struct radv_meta_saved_state *state,
+  struct radv_cmd_buffer *cmd_buffer, uint32_t flags)
 {
state->flags = flags;
 
@@ -51,6 +50,15 @@ radv_meta_save_novertex(struct radv_meta_saved_state *state,
typed_memcpy(state->scissor.scissors,
 cmd_buffer->state.dynamic.scissor.scissors,
 MAX_SCISSORS);
+
+   /* The most common meta operations all want to have the
+* viewport reset and any scissors disabled. The rest of the
+* dynamic state should have no effect.
+*/
+   cmd_buffer->state.dynamic.viewport.count = 0;
+   cmd_buffer->state.dynamic.scissor.count = 0;
+   cmd_buffer->state.dirty |= 1 << VK_DYNAMIC_STATE_VIEWPORT |
+  1 << VK_DYNAMIC_STATE_SCISSOR;
}
 
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
@@ -419,23 +427,6 @@ radv_device_finish_meta(struct radv_device *device)
radv_pipeline_cache_finish(>meta_state.cache);
 }
 
-/*
- * The most common meta operations all want to have the viewport
- * reset and any scissors disabled. The rest of the dynamic state
- * should have no effect.
- */
-void
-radv_meta_save_graphics_reset_vport_scissor_novertex(struct 
radv_meta_saved_state *saved_state,
-struct radv_cmd_buffer 
*cmd_buffer,
-uint32_t flags)
-{
-   radv_meta_save_novertex(saved_state, cmd_buffer, flags);
-   cmd_buffer->state.dynamic.viewport.count = 0;
-   cmd_buffer->state.dynamic.scissor.count = 0;
-   cmd_buffer->state.dirty |= 1 << VK_DYNAMIC_STATE_VIEWPORT |
-  1 << VK_DYNAMIC_STATE_SCISSOR;
-}
-
 nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def 
*comp2)
 {
 
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 6500c9118c..5c94ff5a84 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -95,6 +95,9 @@ void radv_device_finish_meta_resolve_compute_state(struct 
radv_device *device);
 VkResult radv_device_init_meta_resolve_fragment_state(struct radv_device 
*device);
 void radv_device_finish_meta_resolve_fragment_state(struct radv_device 
*device);
 
+void radv_meta_save(struct radv_meta_saved_state *saved_state,
+   struct radv_cmd_buffer *cmd_buffer, uint32_t flags);
+
 void radv_meta_restore(const struct radv_meta_saved_state *state,
   struct radv_cmd_buffer *cmd_buffer);
 
@@ -182,10 +185,6 @@ void radv_fast_clear_flush_image_inplace(struct 
radv_cmd_buffer *cmd_buffer,
 struct radv_image *image,
 const VkImageSubresourceRange 
*subresourceRange);
 
-void radv_meta_save_graphics_reset_vport_scissor_novertex(struct 
radv_meta_saved_state *saved_state,
- struct 
radv_cmd_buffer *cmd_buffer,
- uint32_t flags);
-
 void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
 struct radv_image *src_image,
 VkImageLayout src_image_layout,
diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index 55f9a8807b..6878d3b04e 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -512,10 +512,10 @@ void radv_CmdBlitImage(
assert(src_image->info.samples == 1);
assert(dest_image->info.samples == 1);
 
-   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer,
-  

[Mesa-dev] [PATCH 01/10] radv: add radv_htile_enabled() helper

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_device.c  | 5 ++---
 src/amd/vulkan/radv_private.h | 6 ++
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 402c948e52..0e4a83d612 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -3245,8 +3245,7 @@ radv_initialise_ds_surface(struct radv_device *device,
ds->db_depth_size = S_02801C_X_MAX(iview->image->info.width - 
1) |
S_02801C_Y_MAX(iview->image->info.height - 1);
 
-   /* Only use HTILE for the first level. */
-   if (iview->image->surface.htile_size && !level) {
+   if (radv_htile_enabled(iview->image, level)) {
ds->db_z_info |= S_028038_TILE_SURFACE_ENABLE(1);
 
if (!iview->image->surface.has_stencil)
@@ -3309,7 +3308,7 @@ radv_initialise_ds_surface(struct radv_device *device,
S_028058_HEIGHT_TILE_MAX((level_info->nblk_y / 8) - 1);
ds->db_depth_slice = 
S_02805C_SLICE_TILE_MAX((level_info->nblk_x * level_info->nblk_y) / 64 - 1);
 
-   if (iview->image->surface.htile_size && !level) {
+   if (radv_htile_enabled(iview->image, level)) {
ds->db_z_info |= S_028040_TILE_SURFACE_ENABLE(1);
 
if (!iview->image->surface.has_stencil)
diff --git a/src/amd/vulkan/radv_private.h b/src/amd/vulkan/radv_private.h
index 5cab407211..df3909fd15 100644
--- a/src/amd/vulkan/radv_private.h
+++ b/src/amd/vulkan/radv_private.h
@@ -1252,6 +1252,12 @@ radv_vi_dcc_enabled(const struct radv_image *image, 
unsigned level)
return image->surface.dcc_size && level < image->surface.num_dcc_levels;
 }
 
+static inline bool
+radv_htile_enabled(const struct radv_image *image, unsigned level)
+{
+   return image->surface.htile_size && level == 0;
+}
+
 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t 
family, uint32_t queue_family);
 
 static inline uint32_t
-- 
2.14.2

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[Mesa-dev] [PATCH 09/10] radv: add RADV_META_SAVE_COMPUTE flag

[Samuel Pitoiset]

This will allow use to merge the compute save/restore helpers.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.c | 23 +--
 src/amd/vulkan/radv_meta.h |  1 +
 2 files changed, 22 insertions(+), 2 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 6972a0b592..0b6dee25d9 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -34,9 +34,13 @@ void
 radv_meta_save(struct radv_meta_saved_state *state,
   struct radv_cmd_buffer *cmd_buffer, uint32_t flags)
 {
+   assert(flags & (RADV_META_SAVE_GRAPHICS | RADV_META_SAVE_COMPUTE));
+
state->flags = flags;
 
if (state->flags & RADV_META_SAVE_GRAPHICS) {
+   assert(!(state->flags & RADV_META_SAVE_COMPUTE));
+
state->old_pipeline = cmd_buffer->state.pipeline;
 
/* Save all viewports. */
@@ -61,6 +65,12 @@ radv_meta_save(struct radv_meta_saved_state *state,
   1 << VK_DYNAMIC_STATE_SCISSOR;
}
 
+   if (state->flags & RADV_META_SAVE_COMPUTE) {
+   assert(!(state->flags & RADV_META_SAVE_GRAPHICS));
+
+   state->old_pipeline = cmd_buffer->state.compute_pipeline;
+   }
+
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
}
@@ -106,6 +116,12 @@ radv_meta_restore(const struct radv_meta_saved_state 
*state,
   1 << VK_DYNAMIC_STATE_SCISSOR;
}
 
+   if (state->flags & RADV_META_SAVE_COMPUTE) {
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+VK_PIPELINE_BIND_POINT_COMPUTE,
+
radv_pipeline_to_handle(state->old_pipeline));
+   }
+
if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
cmd_buffer->state.descriptors_dirty |= (1 << 0);
@@ -114,8 +130,11 @@ radv_meta_restore(const struct radv_meta_saved_state 
*state,
if (state->flags & RADV_META_SAVE_CONSTANTS) {
memcpy(cmd_buffer->push_constants, state->push_constants,
   MAX_PUSH_CONSTANTS_SIZE);
-   cmd_buffer->push_constant_stages |= 
VK_SHADER_STAGE_ALL_GRAPHICS |
-   VK_SHADER_STAGE_COMPUTE_BIT;
+   cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
+
+   if (state->flags & RADV_META_SAVE_GRAPHICS) {
+   cmd_buffer->push_constant_stages |= 
VK_SHADER_STAGE_ALL_GRAPHICS;
+   }
}
 
if (state->flags & RADV_META_SAVE_PASS) {
diff --git a/src/amd/vulkan/radv_meta.h b/src/amd/vulkan/radv_meta.h
index 5c94ff5a84..87ff1babcb 100644
--- a/src/amd/vulkan/radv_meta.h
+++ b/src/amd/vulkan/radv_meta.h
@@ -38,6 +38,7 @@ enum radv_meta_save_flags {
RADV_META_SAVE_CONSTANTS   = (1 << 1),
RADV_META_SAVE_DESCRIPTORS = (1 << 2),
RADV_META_SAVE_GRAPHICS= (1 << 3),
+   RADV_META_SAVE_COMPUTE = (1 << 4),
 };
 
 struct radv_meta_saved_state {
-- 
2.14.2

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[Mesa-dev] [PATCH 05/10] radv: introduce the concept of meta save flags

[Samuel Pitoiset]

This will allow us to save/restore the different states on-demand
based on the meta operation. For now, this saves/restores all
states. Compute will follow once the graphics part is done.

The main idea is to merge all save/restore helpers.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta.c| 99 +--
 src/amd/vulkan/radv_meta.h| 12 -
 src/amd/vulkan/radv_meta_blit.c   |  2 +-
 src/amd/vulkan/radv_meta_clear.c  |  8 +--
 src/amd/vulkan/radv_meta_copy.c   |  4 +-
 src/amd/vulkan/radv_meta_decompress.c |  2 +-
 src/amd/vulkan/radv_meta_fast_clear.c |  2 +-
 src/amd/vulkan/radv_meta_resolve.c|  4 +-
 src/amd/vulkan/radv_meta_resolve_fs.c |  4 +-
 9 files changed, 85 insertions(+), 52 deletions(-)

diff --git a/src/amd/vulkan/radv_meta.c b/src/amd/vulkan/radv_meta.c
index 3ddbc2e9af..d6966ed516 100644
--- a/src/amd/vulkan/radv_meta.c
+++ b/src/amd/vulkan/radv_meta.c
@@ -32,53 +32,75 @@
 
 static void
 radv_meta_save_novertex(struct radv_meta_saved_state *state,
-   const struct radv_cmd_buffer *cmd_buffer)
+   const struct radv_cmd_buffer *cmd_buffer,
+   uint32_t flags)
 {
-   state->old_pipeline = cmd_buffer->state.pipeline;
-   state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
-
-   /* Save all viewports. */
-   state->viewport.count = cmd_buffer->state.dynamic.viewport.count;
-   typed_memcpy(state->viewport.viewports,
-cmd_buffer->state.dynamic.viewport.viewports,
-MAX_VIEWPORTS);
+   state->flags = flags;
+
+   if (state->flags & RADV_META_SAVE_GRAPHICS) {
+   state->old_pipeline = cmd_buffer->state.pipeline;
+
+   /* Save all viewports. */
+   state->viewport.count = 
cmd_buffer->state.dynamic.viewport.count;
+   typed_memcpy(state->viewport.viewports,
+cmd_buffer->state.dynamic.viewport.viewports,
+MAX_VIEWPORTS);
+
+   /* Save all scissors. */
+   state->scissor.count = cmd_buffer->state.dynamic.scissor.count;
+   typed_memcpy(state->scissor.scissors,
+cmd_buffer->state.dynamic.scissor.scissors,
+MAX_SCISSORS);
+   }
 
-   /* Save all scissors. */
-   state->scissor.count = cmd_buffer->state.dynamic.scissor.count;
-   typed_memcpy(state->scissor.scissors,
-cmd_buffer->state.dynamic.scissor.scissors,
-MAX_SCISSORS);
+   if (state->flags & RADV_META_SAVE_DESCRIPTORS) {
+   state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
+   }
 
-   memcpy(state->push_constants, cmd_buffer->push_constants, 
MAX_PUSH_CONSTANTS_SIZE);
+   if (state->flags & RADV_META_SAVE_CONSTANTS) {
+   memcpy(state->push_constants, cmd_buffer->push_constants,
+  MAX_PUSH_CONSTANTS_SIZE);
+   }
 }
 
 void
 radv_meta_restore(const struct radv_meta_saved_state *state,
  struct radv_cmd_buffer *cmd_buffer)
 {
-   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), 
VK_PIPELINE_BIND_POINT_GRAPHICS,
-radv_pipeline_to_handle(state->old_pipeline));
-   cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
-
-   cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
-
-   /* Restore all viewports. */
-   cmd_buffer->state.dynamic.viewport.count = state->viewport.count;
-   typed_memcpy(cmd_buffer->state.dynamic.viewport.viewports,
-state->viewport.viewports,
-MAX_VIEWPORTS);
-
-   /* Restore all scissors. */
-   cmd_buffer->state.dynamic.scissor.count = state->scissor.count;
-   typed_memcpy(cmd_buffer->state.dynamic.scissor.scissors,
-state->scissor.scissors,
-MAX_SCISSORS);
+   if (state->flags & RADV_META_SAVE_GRAPHICS) {
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+VK_PIPELINE_BIND_POINT_GRAPHICS,
+
radv_pipeline_to_handle(state->old_pipeline));
+
+   cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
+
+   /* Restore all viewports. */
+   cmd_buffer->state.dynamic.viewport.count = 
state->viewport.count;
+   typed_memcpy(cmd_buffer->state.dynamic.viewport.viewports,
+state->viewport.viewports,
+MAX_VIEWPORTS);
+
+   /* Restore all scissors. */
+   cmd_buffer->state.dynamic.scissor.count = state->scissor.count;
+   typed_memcpy(cmd_buffer->state.dynamic.scissor.scissors,
+state->scissor.scissors,
+   

[Mesa-dev] [PATCH 06/10] radv: convert all GFX operations to the RADV_META_SAVE_XXX flags

[Samuel Pitoiset]

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta_blit.c   |  5 -
 src/amd/vulkan/radv_meta_clear.c  | 20 
 src/amd/vulkan/radv_meta_copy.c   | 11 +--
 src/amd/vulkan/radv_meta_decompress.c |  3 ++-
 src/amd/vulkan/radv_meta_fast_clear.c |  3 ++-
 src/amd/vulkan/radv_meta_resolve.c|  6 --
 src/amd/vulkan/radv_meta_resolve_fs.c | 11 +--
 7 files changed, 46 insertions(+), 13 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_blit.c b/src/amd/vulkan/radv_meta_blit.c
index eb43b822e3..55f9a8807b 100644
--- a/src/amd/vulkan/radv_meta_blit.c
+++ b/src/amd/vulkan/radv_meta_blit.c
@@ -512,7 +512,10 @@ void radv_CmdBlitImage(
assert(src_image->info.samples == 1);
assert(dest_image->info.samples == 1);
 
-   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer, ~0);
+   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer,
+
RADV_META_SAVE_GRAPHICS |
+
RADV_META_SAVE_CONSTANTS |
+
RADV_META_SAVE_DESCRIPTORS);
 
for (unsigned r = 0; r < regionCount; r++) {
const VkImageSubresourceLayers *src_res = 
[r].srcSubresource;
diff --git a/src/amd/vulkan/radv_meta_clear.c b/src/amd/vulkan/radv_meta_clear.c
index 47aef2098a..1d137d3303 100644
--- a/src/amd/vulkan/radv_meta_clear.c
+++ b/src/amd/vulkan/radv_meta_clear.c
@@ -1139,7 +1139,10 @@ radv_cmd_buffer_clear_subpass(struct radv_cmd_buffer 
*cmd_buffer)
if (!radv_subpass_needs_clear(cmd_buffer))
return;
 
-   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer, ~0);
+   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer,
+
RADV_META_SAVE_GRAPHICS |
+
RADV_META_SAVE_CONSTANTS);
+
 
for (uint32_t i = 0; i < cmd_state->subpass->color_count; ++i) {
uint32_t a = 
cmd_state->subpass->color_attachments[i].attachment;
@@ -1381,7 +1384,10 @@ void radv_CmdClearColorImage(
if (cs)
radv_meta_save_compute(_state.compute, cmd_buffer, 16);
else
-   
radv_meta_save_graphics_reset_vport_scissor_novertex(_state.gfx, 
cmd_buffer, ~0);
+   
radv_meta_save_graphics_reset_vport_scissor_novertex(_state.gfx, 
cmd_buffer,
+
RADV_META_SAVE_GRAPHICS |
+
RADV_META_SAVE_CONSTANTS);
+
 
radv_cmd_clear_image(cmd_buffer, image, imageLayout,
 (const VkClearValue *) pColor,
@@ -1405,7 +1411,10 @@ void radv_CmdClearDepthStencilImage(
RADV_FROM_HANDLE(radv_image, image, image_h);
struct radv_meta_saved_state saved_state;
 
-   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer, ~0);
+   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer,
+
RADV_META_SAVE_GRAPHICS |
+
RADV_META_SAVE_CONSTANTS);
+
 
radv_cmd_clear_image(cmd_buffer, image, imageLayout,
 (const VkClearValue *) pDepthStencil,
@@ -1429,7 +1438,10 @@ void radv_CmdClearAttachments(
if (!cmd_buffer->state.subpass)
return;
 
-   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer, ~0);
+   radv_meta_save_graphics_reset_vport_scissor_novertex(_state, 
cmd_buffer,
+
RADV_META_SAVE_GRAPHICS |
+
RADV_META_SAVE_CONSTANTS);
+
 
/* FINISHME: We can do better than this dumb loop. It thrashes too much
 * state.
diff --git a/src/amd/vulkan/radv_meta_copy.c b/src/amd/vulkan/radv_meta_copy.c
index b5a14f6d9f..5272a3af4b 100644
--- a/src/amd/vulkan/radv_meta_copy.c
+++ b/src/amd/vulkan/radv_meta_copy.c
@@ -123,7 +123,10 @@ meta_copy_buffer_to_image(struct radv_cmd_buffer 
*cmd_buffer,
if (cs)
radv_meta_save_compute(_state.compute, cmd_buffer, 12);
else
-   
radv_meta_save_graphics_reset_vport_scissor_novertex(_state.gfx, 
cmd_buffer, ~0);
+   
radv_meta_save_graphics_reset_vport_scissor_novertex(_state.gfx, 
cmd_buffer,
+
RADV_META_SAVE_GRAPHICS |
+
RADV_META_SAVE_CONSTANTS |
+

[Mesa-dev] [PATCH 04/10] radv: do not rebind the same pipeline when doing meta operations

[Samuel Pitoiset]

This might save some usless state changes, and it improves
consistency with the other meta operations.

Signed-off-by: Samuel Pitoiset 
---
 src/amd/vulkan/radv_meta_buffer.c | 18 --
 src/amd/vulkan/radv_meta_resolve_fs.c |  7 +--
 2 files changed, 17 insertions(+), 8 deletions(-)

diff --git a/src/amd/vulkan/radv_meta_buffer.c 
b/src/amd/vulkan/radv_meta_buffer.c
index ea11ed18c4..22be07a2ee 100644
--- a/src/amd/vulkan/radv_meta_buffer.c
+++ b/src/amd/vulkan/radv_meta_buffer.c
@@ -295,9 +295,12 @@ static void fill_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
.size = size
};
 
-   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
-VK_PIPELINE_BIND_POINT_COMPUTE,
-device->meta_state.buffer.fill_pipeline);
+   if (cmd_buffer->state.compute_pipeline !=
+   radv_pipeline_from_handle(device->meta_state.buffer.fill_pipeline)) 
{
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+VK_PIPELINE_BIND_POINT_COMPUTE,
+device->meta_state.buffer.fill_pipeline);
+   }
 
radv_meta_push_descriptor_set(cmd_buffer, 
VK_PIPELINE_BIND_POINT_COMPUTE,
  device->meta_state.buffer.fill_p_layout,
@@ -352,9 +355,12 @@ static void copy_buffer_shader(struct radv_cmd_buffer 
*cmd_buffer,
.size = size
};
 
-   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
-VK_PIPELINE_BIND_POINT_COMPUTE,
-device->meta_state.buffer.copy_pipeline);
+   if (cmd_buffer->state.compute_pipeline !=
+   radv_pipeline_from_handle(device->meta_state.buffer.copy_pipeline)) 
{
+   radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
+VK_PIPELINE_BIND_POINT_COMPUTE,
+device->meta_state.buffer.copy_pipeline);
+   }
 
radv_meta_push_descriptor_set(cmd_buffer, 
VK_PIPELINE_BIND_POINT_COMPUTE,
  device->meta_state.buffer.copy_p_layout,
diff --git a/src/amd/vulkan/radv_meta_resolve_fs.c 
b/src/amd/vulkan/radv_meta_resolve_fs.c
index 50d5ed7d5a..56b6e0c29a 100644
--- a/src/amd/vulkan/radv_meta_resolve_fs.c
+++ b/src/amd/vulkan/radv_meta_resolve_fs.c
@@ -418,8 +418,11 @@ emit_resolve(struct radv_cmd_buffer *cmd_buffer,
unsigned fs_key = radv_format_meta_fs_key(dest_iview->vk_format);
VkPipeline pipeline_h = 
device->meta_state.resolve_fragment.rc[samples_log2].pipeline[fs_key];
 
-   radv_CmdBindPipeline(cmd_buffer_h, VK_PIPELINE_BIND_POINT_GRAPHICS,
-pipeline_h);
+   if (cmd_buffer->state.pipeline != 
radv_pipeline_from_handle(pipeline_h)) {
+   radv_CmdBindPipeline(cmd_buffer_h,
+VK_PIPELINE_BIND_POINT_GRAPHICS,
+pipeline_h);
+   }
 
radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, 
&(VkViewport) {
.x = dest_offset->x,
-- 
2.14.2

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Re: [Mesa-dev] [PATCH 1/5] ac: properly document a buffer.store LLVM workaround

[Samuel Pitoiset]

2-5 are:

Reviewed-by: Samuel Pitoiset 

On 10/03/2017 07:30 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/amd/common/ac_llvm_build.c | 13 -
  src/amd/common/ac_llvm_build.h |  2 +-
  2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 51fb009..0cebaa7 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -753,42 +753,45 @@ void
  ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
LLVMValueRef vdata,
unsigned num_channels,
LLVMValueRef voffset,
LLVMValueRef soffset,
unsigned inst_offset,
bool glc,
bool slc,
bool writeonly_memory,
-   bool has_add_tid)
+   bool swizzle_enable_hint)
  {
-   /* TODO: Fix stores with ADD_TID and remove the "has_add_tid" flag. */
-   if (!has_add_tid) {
+   /* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
+* (voffset is swizzled, but soffset isn't swizzled).
+* llvm.amdgcn.buffer.store doesn't have a separate soffset parameter.
+*/
+   if (!swizzle_enable_hint) {
/* Split 3 channel stores, becase LLVM doesn't support 3-channel
 * intrinsics. */
if (num_channels == 3) {
LLVMValueRef v[3], v01;
  
  			for (int i = 0; i < 3; i++) {

v[i] = LLVMBuildExtractElement(ctx->builder, 
vdata,
LLVMConstInt(ctx->i32, i, 0), 
"");
}
v01 = ac_build_gather_values(ctx, v, 2);
  
  			ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset,

soffset, inst_offset, glc, 
slc,
-   writeonly_memory, 
has_add_tid);
+   writeonly_memory, 
swizzle_enable_hint);
ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset,
soffset, inst_offset + 8,
glc, slc,
-   writeonly_memory, 
has_add_tid);
+   writeonly_memory, 
swizzle_enable_hint);
return;
}
  
  		unsigned func = CLAMP(num_channels, 1, 3) - 1;

static const char *types[] = {"f32", "v2f32", "v4f32"};
char name[256];
LLVMValueRef offset = soffset;
  
  		if (inst_offset)

offset = LLVMBuildAdd(ctx->builder, offset,
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 1d6dc0a..ac8ea9c 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -163,21 +163,21 @@ void
  ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
LLVMValueRef vdata,
unsigned num_channels,
LLVMValueRef voffset,
LLVMValueRef soffset,
unsigned inst_offset,
bool glc,
bool slc,
bool writeonly_memory,
-   bool has_add_tid);
+   bool swizzle_enable_hint);
  LLVMValueRef
  ac_build_buffer_load(struct ac_llvm_context *ctx,
 LLVMValueRef rsrc,
 int num_channels,
 LLVMValueRef vindex,
 LLVMValueRef voffset,
 LLVMValueRef soffset,
 unsigned inst_offset,
 unsigned glc,
 unsigned slc,


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Re: [Mesa-dev] [PATCH] radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival Evolved

[Samuel Pitoiset]

Figured the same fix locally yesterday, let's go this way for now.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=102955
Reviewed-by: Samuel Pitoiset 

On 10/03/2017 07:32 PM, Marek Olšák wrote:

From: Marek Olšák 

---
  src/gallium/drivers/radeonsi/driinfo_radeonsi.h |  4 
  src/gallium/drivers/radeonsi/si_blit.c  | 14 ++
  src/gallium/drivers/radeonsi/si_pipe.c  |  2 ++
  src/gallium/drivers/radeonsi/si_pipe.h  |  1 +
  src/util/drirc  |  5 +
  src/util/xmlpool/t_options.h|  5 +
  6 files changed, 31 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h 
b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index 989e517..7f57b4e 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,6 +1,10 @@
  // DriConf options specific to radeonsi
  DRI_CONF_SECTION_PERFORMANCE
  DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
  DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
  DRI_CONF_RADEONSI_COMMUTATIVE_BLEND_ADD("false")
  DRI_CONF_SECTION_END
+
+DRI_CONF_SECTION_DEBUG
+   DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR("false")
+DRI_CONF_SECTION_END
diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 67972a2..44e5251 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -896,20 +896,34 @@ static void si_clear(struct pipe_context *ctx, unsigned 
buffers,
if (!zstex->stencil_cleared || 
zstex->stencil_clear_value != stencil) {
sctx->db_stencil_disable_expclear = true;
}
  
  			zstex->stencil_clear_value = stencil;

sctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(sctx, >framebuffer.atom); /* 
updates DB_STENCIL_CLEAR */
sctx->db_stencil_clear = true;
si_mark_atom_dirty(sctx, >db_render_state);
}
+
+   /* TODO: Find out what's wrong here. Fast depth clear leads to
+* corruption in ARK: Survival Evolved, but that may just be
+* a coincidence and the root cause is elsewhere.
+*
+* The corruption can be fixed by putting the DB flush before
+* or after the depth clear. (suprisingly)
+*
+* https://bugs.freedesktop.org/show_bug.cgi?id=102955 
(apitrace)
+*
+* This hack massively decreases back-to-back ClearDepth 
performance.
+*/
+   if (sctx->screen->clear_db_cache_before_clear)
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
  
  	si_blitter_begin(ctx, SI_CLEAR);

util_blitter_clear(sctx->blitter, fb->width, fb->height,
   util_framebuffer_get_num_layers(fb),
   buffers, color, depth, stencil);
si_blitter_end(ctx);
  
  	if (sctx->db_depth_clear) {

sctx->db_depth_clear = false;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 79e4e1c..7039aab 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1050,20 +1050,22 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 sscreen->b.info.pfp_fw_version >= 79 &&
 sscreen->b.info.me_fw_version >= 142);
  
  	sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&

 sscreen->b.info.max_se >= 2 &&
 !(sscreen->b.debug_flags & 
DBG_NO_OUT_OF_ORDER);
sscreen->assume_no_z_fights =
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
sscreen->commutative_blend_add =
driQueryOptionb(config->options, 
"radeonsi_commutative_blend_add");
+   sscreen->clear_db_cache_before_clear =
+   driQueryOptionb(config->options, 
"radeonsi_clear_db_cache_before_clear");
sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 
&&
sscreen->b.family <= 
CHIP_POLARIS12) ||
   sscreen->b.family == CHIP_VEGA10 ||
   sscreen->b.family == CHIP_RAVEN;
sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
!(sscreen->b.debug_flags & DBG_NO_DPBB);
sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
!(sscreen->b.debug_flags & DBG_NO_DFSM);
  
  	/* While it would be nice not to have this flag, we are constrained

diff --git 

Re: [Mesa-dev] [PATCH v2 04/11] anv: prepare formats to handle disjoints sets

[Jason Ekstrand]

On Tue, Oct 3, 2017 at 10:16 AM, Chad Versace 
wrote:

> On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> > Newer format enums start at offset 10, making it impossible to
> > have them all in one table. This change splits the formats into sets
> > that we then access through indirection.
> >
> > Signed-off-by: Lionel Landwerlin 
> > ---
> >  src/intel/vulkan/anv_formats.c | 35 ++-
> >  1 file changed, 26 insertions(+), 9 deletions(-)
> >
> > diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_
> formats.c
> > index 049ffe17ac0..71824256b25 100644
> > --- a/src/intel/vulkan/anv_formats.c
> > +++ b/src/intel/vulkan/anv_formats.c
> > @@ -58,7 +58,7 @@
> >   * other.  The reason for this is that, for packed formats, the ISL (and
> >   * bspec) names are in LSB -> MSB order while VK formats are MSB -> LSB.
> >   */
> > -static const struct anv_format anv_formats[] = {
> > +static const struct anv_format main_formats[] = {
> > fmt(VK_FORMAT_UNDEFINED,   ISL_FORMAT_UNSUPPORTED),
> > fmt(VK_FORMAT_R4G4_UNORM_PACK8,ISL_FORMAT_UNSUPPORTED),
> > fmt(VK_FORMAT_R4G4B4A4_UNORM_PACK16,   ISL_FORMAT_A4B4G4R4_UNORM),
> > @@ -251,13 +251,30 @@ static const struct anv_format anv_formats[] = {
> >
> >  #undef fmt
> >
> > +static const struct {
> > +   const struct anv_format *formats;
> > +   uint32_t n_formats;
> > +} anv_formats[] = {
> > +   [0] = { .formats = main_formats, .n_formats =
> ARRAY_SIZE(main_formats), },
> > +};
> > +
> > +static struct anv_format
> > +format_extract(VkFormat vk_format)
> > +{
> > +   uint32_t enum_offset = vk_enum_offset(vk_format);
> > +   uint32_t ext_number = vk_enum_extension(vk_format);
> > +
> > +   if (ext_number >= ARRAY_SIZE(anv_formats) ||
> > +   enum_offset >= anv_formats[ext_number].n_formats)
> > +  return (struct anv_format) { .isl_format = ISL_FORMAT_UNSUPPORTED
> };
> > +
> > +   return anv_formats[ext_number].formats[enum_offset];
> > +}
> > +
> >  static bool
> >  format_supported(VkFormat vk_format)
> >  {
> > -   if (vk_format >= ARRAY_SIZE(anv_formats))
> > -  return false;
> > -
> > -   return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
> > +   return format_extract(vk_format).isl_format !=
> ISL_FORMAT_UNSUPPORTED;
> >  }
> >
> >  /**
> > @@ -267,10 +284,10 @@ struct anv_format
> >  anv_get_format(const struct gen_device_info *devinfo, VkFormat
> vk_format,
> > VkImageAspectFlags aspect, VkImageTiling tiling)
> >  {
> > -   if (!format_supported(vk_format))
> > -  return anv_formats[VK_FORMAT_UNDEFINED];
> > +   struct anv_format format = format_extract(vk_format);
> >
> > -   struct anv_format format = anv_formats[vk_format];
> > +   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
> > +  return format;
> >
> > if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
> >assert(vk_format_aspects(vk_format) &
> VK_IMAGE_ASPECT_STENCIL_BIT);
> > @@ -553,7 +570,7 @@ anv_get_image_format_properties(
> >  ** This field cannot be ASTC format if the Surface Type is
> SURFTYPE_1D.
> >  */
> > if (info->type == VK_IMAGE_TYPE_1D &&
> > -   isl_format_is_compressed(anv_formats[info->format].isl_format))
> {
> > +   isl_format_is_compressed(format_extract(info->format).isl_format))
> {
>
> When I see format_extract(), I have no idea what it does. How about
> giving it a name like format_to_anv(), vk_format_to_anv(), or even
> something as simple as format_get()? Everyone has a general
> understanding of what foobar_get() and foobar_to_stuff() does, but
> I don't think foobar_extract() is as well understand.
>

+1.  I like vk_to_anv_format personally.
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Re: [Mesa-dev] [PATCH] configure.ac: bump Clover LLVM requirement to 3.9

[Jan Vesely]

On Tue, 2017-10-03 at 17:51 +0100, Emil Velikov wrote:
> From: Emil Velikov 
> 
> The only driver that utilises Clover already depends on LLVM 3.9.
> Additionally close to every supported distribution has said version.
> 
> Additionally libclc requires LLVM 4.0 these days.

support for llvm-3.9 has been restored to libclc since our discussion.
sorry, I should have mentioned that.

Jan

> 
> With this in mind, there a handful of dead code that we could remove.
> That will come with later commits.
> 
> Note: this drops the LLVM 3.6 build from the Travis build. LLVM 3.9 (and
> later) are already covered in there.
> 
> Cc: Vedran Miletić 
> Cc: Jan Vesely 
> Cc: Aaron Watry 
> Cc: Francisco Jerez 
> Signed-off-by: Emil Velikov 
> ---
> Vedran can we volunteer you for the cleanup ;-)
> ---
>  .travis.yml  | 38 --
>  configure.ac |  2 +-
>  2 files changed, 1 insertion(+), 39 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index d9a8bf5a9d4..1e5f6bcb702 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -113,44 +113,6 @@ matrix:
>  - libx11-xcb-dev
>  - libelf-dev
>  - libunwind8-dev
> -- env:
> -# NOTE: Analogous to SWR above, building Clover is quite slow.
> -- LABEL="make Gallium ST Clover"
> -- BUILD=make
> -- MAKEFLAGS="-j4"
> -- MAKE_CHECK_COMMAND="true"
> -- LLVM_VERSION=3.6
> -- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> -- OVERRIDE_CC=gcc-4.7
> -- OVERRIDE_CXX=g++-4.7
> -- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> -- DRI_DRIVERS=""
> -- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
> --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
> --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
> -# i915 most likely doesn't work with OpenCL.
> -# Regardless - we're doing a quick build test here.
> -- GALLIUM_DRIVERS="i915"
> -- VULKAN_DRIVERS=""
> -- LIBUNWIND_FLAGS="--enable-libunwind"
> -  addons:
> -apt:
> -  sources:
> -- llvm-toolchain-trusty-3.6
> -  packages:
> -- libclc-dev
> -# LLVM packaging is broken and misses these dependencies
> -- libedit-dev
> -- g++-4.7
> -# From sources above
> -- llvm-3.6-dev
> -- clang-3.6
> -- libclang-3.6-dev
> -# Common
> -- xz-utils
> -- x11proto-xf86vidmode-dev
> -- libexpat1-dev
> -- libx11-xcb-dev
> -- libelf-dev
> -- libunwind8-dev
>  - env:
>  # NOTE: Analogous to SWR above, building Clover is quite slow.
>  - LABEL="make Gallium ST Clover LLVM-3.9"
> diff --git a/configure.ac b/configure.ac
> index cfc97d9f061..d62570fb14d 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -101,7 +101,7 @@ ZLIB_REQUIRED=1.2.3
>  
>  dnl LLVM versions
>  LLVM_REQUIRED_GALLIUM=3.3.0
> -LLVM_REQUIRED_OPENCL=3.6.0
> +LLVM_REQUIRED_OPENCL=3.9.0
>  LLVM_REQUIRED_R600=3.9.0
>  LLVM_REQUIRED_RADEONSI=3.9.0
>  LLVM_REQUIRED_RADV=3.9.0

-- 
Jan Vesely 

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Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Lionel Landwerlin]

On 03/10/17 19:13, Jason Ekstrand wrote:
On Tue, Oct 3, 2017 at 9:43 AM, Chad Versace > wrote:


On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> v2: Simplify offset enum computation (Jason)
>
> Signed-off-by: Lionel Landwerlin >
> ---
>  src/vulkan/util/vk_util.h | 6 ++
>  1 file changed, 6 insertions(+)
>
> diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
> index 2ed601f881e..8c8cb64d513 100644
> --- a/src/vulkan/util/vk_util.h
> +++ b/src/vulkan/util/vk_util.h
> @@ -199,4 +199,10 @@ __vk_find_struct(void *start,
VkStructureType sType)
>
>  uint32_t vk_get_driver_version(void);
>
> +#define VK_EXT_OFFSET (10UL)
> +#define vk_enum_extension(__enum) \
> +   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET) /
1000UL) + 1) : 0)
> +#define vk_enum_offset(__enum) \
> +   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))

The macro functions, when called, look like regular functions due to
being lowercase. But they don't behave like functions; their arguments
suffer from the multiple evaluation disease.

Please rename the macros to be all uppercase, so callers' expectations
will be set correctly. Or, even better, define them as inline
functions.


+1 to static inline


Done locally.

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Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Jason Ekstrand]

On Tue, Oct 3, 2017 at 9:43 AM, Chad Versace 
wrote:

> On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> > v2: Simplify offset enum computation (Jason)
> >
> > Signed-off-by: Lionel Landwerlin 
> > ---
> >  src/vulkan/util/vk_util.h | 6 ++
> >  1 file changed, 6 insertions(+)
> >
> > diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
> > index 2ed601f881e..8c8cb64d513 100644
> > --- a/src/vulkan/util/vk_util.h
> > +++ b/src/vulkan/util/vk_util.h
> > @@ -199,4 +199,10 @@ __vk_find_struct(void *start, VkStructureType sType)
> >
> >  uint32_t vk_get_driver_version(void);
> >
> > +#define VK_EXT_OFFSET (10UL)
> > +#define vk_enum_extension(__enum) \
> > +   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET) / 1000UL)
> + 1) : 0)
> > +#define vk_enum_offset(__enum) \
> > +   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))
>
> The macro functions, when called, look like regular functions due to
> being lowercase. But they don't behave like functions; their arguments
> suffer from the multiple evaluation disease.
>
> Please rename the macros to be all uppercase, so callers' expectations
> will be set correctly. Or, even better, define them as inline
> functions.


+1 to static inline
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Re: [Mesa-dev] [PATCH 2/2] egl/surfaceless: Use KMS swrast fallback

[Gurchetan Singh]

I mostly ran other tests suites. We actually don't run dEQP on VMs since
our current swrast-based implementation would segfault. We would need a
patch like:

https://lists.freedesktop.org/archives/mesa-dev/2017-August/164922.html

for it to work. However, I was able to verify dEQP successfully runs with
this patchset, though I just ran a few tests. I expect the full suite to be
up and running soon ...

On Tue, Oct 3, 2017 at 10:04 AM, Eric Engestrom 
wrote:

> On Tuesday, 2017-10-03 16:30:18 +, Gurchetan Singh wrote:
> > Hi Eric,
> >
> > Yes, you pushing this series would be great.
>
> Done; since I was editing it anyway, I also moved the _eglLog() string
> to avoid breaking it (makes grepping easier).
>
> > I did run our test suite on this patchset as well.
>
> You mean deqp, or another one?
> I assume the results were "100% success"?
>
> >
> > Best wishes,
> > Gurchetan
> >
> > On Tue, Oct 3, 2017 at 7:02 AM, Eric Engestrom <
> eric.engest...@imgtec.com>
> > wrote:
> >
> > > On Monday, 2017-10-02 20:48:24 +, gurchetansi...@chromium.org
> wrote:
> > > > From: Gurchetan Singh 
> > > >
> > > > The kms_swrast extension is an actively developed software fallback,
> > > > and platform_surfaceless can use it if there are no available
> > > > hardware drivers.
> > > >
> > > > v2: Split into 2 patches, use booleans, check LIBGL_ALWAYS_SOFTWARE,
> > > > and modify the eglLog level (Emil, Eric, Tomasz).
> > >
> > > Thanks, this is perfect :)
> > >
> > > Reviewed-by: Eric Engestrom 
> > >
> > > Do you want me to push this for you?
> > >
> > > It might be worth running deqp and other test suites to make sure
> > > everything is wired up correctly.
> > > (Given your chromium affiliation, I'm assuming you already know how to
> > > use the surfaceless patches for deqp [1])
> > >
> > > [1] https://chromium.googlesource.com/chromiumos/overlays/
> > > chromiumos-overlay/+/master/media-gfx/deqp
> > >
> > > > ---
> > > >  src/egl/drivers/dri2/platform_surfaceless.c | 19
> +++
> > > >  1 file changed, 15 insertions(+), 4 deletions(-)
> > > >
> > > > diff --git a/src/egl/drivers/dri2/platform_surfaceless.c
> > > b/src/egl/drivers/dri2/platform_surfaceless.c
> > > > index f6aa217d39..b0a43ac9de 100644
> > > > --- a/src/egl/drivers/dri2/platform_surfaceless.c
> > > > +++ b/src/egl/drivers/dri2/platform_surfaceless.c
> > > [snip]
> > > > @@ -320,7 +324,14 @@ dri2_initialize_surfaceless(_EGLDriver *drv,
> > > _EGLDisplay *disp)
> > > >
> > > > dri2_dpy->fd = -1;
> > > > disp->DriverData = (void *) dri2_dpy;
> > >
> > > Nit: newline here
> > > (I'll add it if/when I commit it, don't send a v3 for that)
> > >
> > > > -   if (!surfaceless_probe_device(disp)) {
> > > > +   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false)) {
> > > > +  driver_loaded = surfaceless_probe_device(disp, false);
> > > > +  if (!driver_loaded)
> > > > + _eglLog(_EGL_WARNING, "No hardware driver found, falling
> back
> > > to "
> > > > +  "software rendering");
> > > > +   }
> > > > +
> > > > +   if (!driver_loaded && !surfaceless_probe_device(disp, true)) {
> > > >err = "DRI2: failed to load driver";
> > > >goto cleanup;
> > > > }
> > > > --
> > > > 2.13.5
> > > >
> > >
>
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Re: [Mesa-dev] [PATCH v2 3/3] etnaviv: optimize RS transfers

[Christian Gmeiner]

2017-09-22 11:31 GMT+02:00 Lucas Stach :
> Currently we are blitting the whole resource when the RS is used to
> de-/tile a resource. This can be very inefficient for large resources
> where the transfer is only changing a small part of the resource
> (happens a lot with glTexSubImage2D).
>
> Optimize this by only blitting the tile aligned subregion of the
> resource, which the transfer is going to change.
>
> Signed-off-by: Lucas Stach 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_transfer.c | 29 
> ++
>  1 file changed, 25 insertions(+), 4 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_transfer.c 
> b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> index 6c1edd483541..ee5cda5e8ec2 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_transfer.c
> @@ -28,6 +28,7 @@
>  #include "etnaviv_clear_blit.h"
>  #include "etnaviv_context.h"
>  #include "etnaviv_debug.h"
> +#include "etnaviv_screen.h"
>
>  #include "pipe/p_defines.h"
>  #include "pipe/p_format.h"
> @@ -84,8 +85,7 @@ etna_transfer_unmap(struct pipe_context *pctx, struct 
> pipe_transfer *ptrans)
>   /* We have a temporary resource due to either tile status or
>* tiling format. Write back the updated buffer contents.
>* FIXME: we need to invalidate the tile status. */
> - etna_copy_resource(pctx, ptrans->resource, trans->rsc, 
> ptrans->level,
> -trans->rsc->last_level);
> + etna_copy_resource_box(pctx, ptrans->resource, trans->rsc, 
> ptrans->level, >box);
>} else if (trans->staging) {
>   /* map buffer object */
>   struct etna_resource_level *res_level = >levels[ptrans->level];
> @@ -212,9 +212,30 @@ etna_transfer_map(struct pipe_context *pctx, struct 
> pipe_resource *prsc,
>   return NULL;
>}
>
> +  /* Need to align the transfer region to satisfy RS restrictions, as we
> +   * really want to hit the RS blit path here.
> +   */
> +  unsigned w_align, h_align;
> +
> +  if (rsc->layout & ETNA_LAYOUT_BIT_SUPER) {
> + w_align = h_align = 64;
> +  } else {
> + w_align = ETNA_RS_WIDTH_MASK + 1;
> + h_align = ETNA_RS_HEIGHT_MASK + 1;
> +  }
> +  h_align *= ctx->screen->specs.pixel_pipes;
> +
> +  ptrans->box.width += ptrans->box.x & (w_align - 1);
> +  ptrans->box.x = ptrans->box.x & ~(w_align - 1);
> +  ptrans->box.width = align(ptrans->box.width, (ETNA_RS_WIDTH_MASK + 1));
> +  ptrans->box.height += ptrans->box.y & (h_align - 1);
> +  ptrans->box.y = ptrans->box.y & ~(h_align - 1);
> +  ptrans->box.height = align(ptrans->box.height,
> + (ETNA_RS_HEIGHT_MASK + 1) *
> +  ctx->screen->specs.pixel_pipes);
> +
>if (!(usage & PIPE_TRANSFER_DISCARD_WHOLE_RESOURCE))
> - etna_copy_resource(pctx, trans->rsc, prsc, level,
> -trans->rsc->last_level);
> + etna_copy_resource_box(pctx, trans->rsc, prsc, level, >box);
>
>/* Switch to using the temporary resource instead */
>rsc = etna_resource(trans->rsc);
> --
> 2.11.0
>
> ___
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greets
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Re: [Mesa-dev] [PATCH v2 2/3] etnaviv: add resource subregion copy

[Christian Gmeiner]

2017-09-22 11:31 GMT+02:00 Lucas Stach :
> This is useful if we only need to copy part of a larger resource, mostly
> when using the RS engine to de-/tile on pipe transfers.
>
> Signed-off-by: Lucas Stach 
> Reviewed-by: Wladimir J. van der Laan 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.c | 27 
> 
>  src/gallium/drivers/etnaviv/etnaviv_clear_blit.h |  5 +
>  2 files changed, 32 insertions(+)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> index 8030450dd1b0..971403c45476 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.c
> @@ -727,6 +727,33 @@ etna_copy_resource(struct pipe_context *pctx, struct 
> pipe_resource *dst,
>  }
>
>  void
> +etna_copy_resource_box(struct pipe_context *pctx, struct pipe_resource *dst,
> +   struct pipe_resource *src, int level,
> +   struct pipe_box *box)
> +{
> +   assert(src->format == dst->format);
> +   assert(src->array_size == dst->array_size);
> +
> +   struct pipe_blit_info blit = {};
> +   blit.mask = util_format_get_mask(dst->format);
> +   blit.filter = PIPE_TEX_FILTER_NEAREST;
> +   blit.src.resource = src;
> +   blit.src.format = src->format;
> +   blit.src.box = *box;
> +   blit.dst.resource = dst;
> +   blit.dst.format = dst->format;
> +   blit.dst.box = *box;
> +
> +   blit.dst.box.depth = blit.src.box.depth = 1;
> +   blit.src.level = blit.dst.level = level;
> +
> +   for (int layer = 0; layer < dst->array_size; layer++) {
> +  blit.src.box.z = blit.dst.box.z = layer;
> +  pctx->blit(pctx, );
> +   }
> +}
> +
> +void
>  etna_clear_blit_init(struct pipe_context *pctx)
>  {
> pctx->clear = etna_clear;
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h 
> b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h
> index 73d07044b2b3..9bba6236b4db 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h
> +++ b/src/gallium/drivers/etnaviv/etnaviv_clear_blit.h
> @@ -43,6 +43,11 @@ etna_copy_resource(struct pipe_context *pctx, struct 
> pipe_resource *dst,
> struct pipe_resource *src, int first_level, int 
> last_level);
>
>  void
> +etna_copy_resource_box(struct pipe_context *pctx, struct pipe_resource *dst,
> +   struct pipe_resource *src, int level,
> +   struct pipe_box *box);
> +
> +void
>  etna_clear_blit_init(struct pipe_context *pctx);
>
>  #endif
> --
> 2.11.0
>
> ___
> etnaviv mailing list
> etna...@lists.freedesktop.org
> https://lists.freedesktop.org/mailman/listinfo/etnaviv

greets
--
Christian Gmeiner, MSc

https://christian-gmeiner.info
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Re: [Mesa-dev] [PATCH] etnaviv: update HW headers and fix provoking vertex

[Christian Gmeiner]

Hi Lucas,

patch does not apply to master - could you rebase it?

Applying: etnaviv: update HW headers and fix provoking vertex
error: patch failed: src/gallium/drivers/etnaviv/hw/state_3d.xml.h:8
error: src/gallium/drivers/etnaviv/hw/state_3d.xml.h: patch does not apply
Patch failed at 0001 etnaviv: update HW headers and fix provoking vertex


2017-09-29 15:40 GMT+02:00 Lucas Stach :
> Now that the real meaning of the 2 bits in PA_SYSTEM_MODE is known,
> we can set them according to the rasterizer state, which fixes uses
> that are setting provoking vertex first.
>
> Signed-off-by: Lucas Stach 

Reviewed-by: Christian Gmeiner 

> ---
>  src/gallium/drivers/etnaviv/etnaviv_rasterizer.c |  3 +-
>  src/gallium/drivers/etnaviv/hw/cmdstream.xml.h   |  8 +--
>  src/gallium/drivers/etnaviv/hw/common.xml.h  | 18 +++---
>  src/gallium/drivers/etnaviv/hw/isa.xml.h |  4 +-
>  src/gallium/drivers/etnaviv/hw/state.xml.h   | 14 ++---
>  src/gallium/drivers/etnaviv/hw/state_3d.xml.h| 79 
> +++-
>  6 files changed, 75 insertions(+), 51 deletions(-)
>
> diff --git a/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c 
> b/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c
> index 56f2735e8a18..c8627b1a9ab4 100644
> --- a/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c
> +++ b/src/gallium/drivers/etnaviv/etnaviv_rasterizer.c
> @@ -61,7 +61,8 @@ etna_rasterizer_state_create(struct pipe_context *pctx,
> /* XXX anything else? */
> /* XXX bottom_edge_rule */
> cs->PA_SYSTEM_MODE =
> -  COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_UNK0 | 
> VIVS_PA_SYSTEM_MODE_UNK4);
> +  COND(!so->flatshade_first, VIVS_PA_SYSTEM_MODE_PROVOKING_VERTEX_LAST) |
> +  COND(so->half_pixel_center, VIVS_PA_SYSTEM_MODE_HALF_PIXEL_CENTER);
>
> /* so->scissor overrides the scissor, defaulting to the whole framebuffer,
>  * with the scissor state */
> diff --git a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h 
> b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
> index d4da03016ea5..f8d76b010582 100644
> --- a/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
> +++ b/src/gallium/drivers/etnaviv/hw/cmdstream.xml.h
> @@ -8,11 +8,11 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
>  git clone git://0x04.net/rules-ng-ng
>
>  The rules-ng-ng source files this header was generated from are:
> -- cmdstream.xml (  14313 bytes, from 2016-11-17 18:46:23)
> -- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
> -- common.xml(  23473 bytes, from 2017-01-07 14:27:54)
> +- cmdstream.xml (  15289 bytes, from 2017-09-29 11:52:39)
> +- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
> +- common.xml(  23529 bytes, from 2017-09-29 11:52:39)
>
> -Copyright (C) 2012-2016 by the following authors:
> +Copyright (C) 2012-2017 by the following authors:
>  - Wladimir J. van der Laan 
>  - Christian Gmeiner 
>  - Lucas Stach 
> diff --git a/src/gallium/drivers/etnaviv/hw/common.xml.h 
> b/src/gallium/drivers/etnaviv/hw/common.xml.h
> index 8b73fd812896..85c4990b61ae 100644
> --- a/src/gallium/drivers/etnaviv/hw/common.xml.h
> +++ b/src/gallium/drivers/etnaviv/hw/common.xml.h
> @@ -8,13 +8,13 @@ http://0x04.net/cgit/index.cgi/rules-ng-ng
>  git clone git://0x04.net/rules-ng-ng
>
>  The rules-ng-ng source files this header was generated from are:
> -- state.xml (  19930 bytes, from 2017-01-07 14:27:54)
> -- common.xml(  23473 bytes, from 2017-01-07 14:27:54)
> -- state_hi.xml  (  26403 bytes, from 2017-01-07 14:27:54)
> -- copyright.xml (   1597 bytes, from 2016-10-29 07:29:22)
> -- state_2d.xml  (  51552 bytes, from 2016-10-29 07:29:22)
> -- state_3d.xml  (  66964 bytes, from 2017-04-13 12:38:05)
> -- state_vg.xml  (   5975 bytes, from 2016-10-29 07:29:22)
> +- state.xml (  20229 bytes, from 2017-09-29 11:52:39)
> +- common.xml(  23529 bytes, from 2017-09-29 11:52:39)
> +- state_hi.xml  (  26403 bytes, from 2017-03-09 15:43:43)
> +- copyright.xml (   1597 bytes, from 2016-12-08 16:37:56)
> +- state_2d.xml  (  51552 bytes, from 2016-12-08 16:37:56)
> +- state_3d.xml  (  68429 bytes, from 2017-09-29 11:55:19)
> +- state_vg.xml  (   5975 bytes, from 2016-12-08 16:37:56)
>
>  Copyright (C) 2012-2017 by the following authors:
>  - Wladimir J. van der Laan 
> @@ -247,7 +247,7 @@ DEALINGS IN THE SOFTWARE.
>  #define chipMinorFeatures3_UNK24   0x0100
>  #define chipMinorFeatures3_UNK25   0x0200
>  #define chipMinorFeatures3_NEW_HZ  0x0400
> -#define chipMinorFeatures3_UNK27   0x0800
> +#define chipMinorFeatures3_PE_DITHER_FIX   0x0800
>  #define chipMinorFeatures3_UNK28   0x1000
>  #define chipMinorFeatures3_SH_ENHANCEMENTS3

Re: [Mesa-dev] [PATCH] intel: compiler: vec4: add missing default 0 lod

[Matt Turner]

On Tue, Oct 3, 2017 at 8:05 AM, Lionel Landwerlin
 wrote:
> We handle similar default valid for LOD in the fs backend for TXS/TXL.
> Without this we end up generating invalid MOV with a null src.
>
> Signed-off-by: Lionel Landwerlin 
> Cc: "17.2 17.1" 
> ---
>  src/intel/compiler/brw_vec4_nir.cpp | 9 +
>  1 file changed, 9 insertions(+)
>
> diff --git a/src/intel/compiler/brw_vec4_nir.cpp 
> b/src/intel/compiler/brw_vec4_nir.cpp
> index 0a1caa9fad8..9200ffa0ed7 100644
> --- a/src/intel/compiler/brw_vec4_nir.cpp
> +++ b/src/intel/compiler/brw_vec4_nir.cpp
> @@ -2228,6 +2228,15 @@ vec4_visitor::nir_emit_texture(nir_tex_instr *instr)
>}
> }
>
> +   /* TXS and TXL require a LOD but not everything we implement using those
> +* two opcodes provides one.  Provide a default LOD of 0.
> +*/
> +   if ((instr->op == nir_texop_txs ||
> +instr->op == nir_texop_txl) &&
> +   lod.file == BAD_FILE) {
> +  lod = brw_imm_ud(0u);
> +   }

Reviewed-by: Matt Turner 

Really glad to see the EU validator catching bugs.
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Re: [Mesa-dev] [PATCH 1/3] loader/dri3: Use local blits and local buffers when resizing

[Sinclair Yeh]

On Tue, Oct 03, 2017 at 02:16:42PM +0200, Thomas Hellstrom wrote:
> Hi!
> 
> Could anyone please review this series?
> 
> Thanks,
> Thomas

Minor typo in the commit message of 1/3:

[Mesa-dev] [PATCH 1/3] loader/dri3: Use local blits and local buffers when
resizing

When a drawable is resized, and we we fill the resized buffers, with data
 ^
typo


For 3/3, I don't know which buffer LOADER_DRI3_FRONT_ID represents, so I'm
assuming that line checks the correct condition.

Other than those the series:  Reviewed-by: Sinclair Yeh 

> 
> 
> On 09/15/2017 10:48 AM, Thomas Hellstrom wrote:
> > When a drawable is resized, and we we fill the resized buffers, with data
> > from the old buffers, use a local blit if there is a local buffer (back or
> > fake front), and we have local blitting capability.
> > 
> > Signed-off-by: Thomas Hellstrom 
> > ---
> >   src/loader/loader_dri3_helper.c | 50 
> > -
> >   1 file changed, 24 insertions(+), 26 deletions(-)
> > 
> > diff --git a/src/loader/loader_dri3_helper.c 
> > b/src/loader/loader_dri3_helper.c
> > index bcd5a66..aea0f68 100644
> > --- a/src/loader/loader_dri3_helper.c
> > +++ b/src/loader/loader_dri3_helper.c
> > @@ -1373,30 +1373,30 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
> > /* When resizing, copy the contents of the old buffer, waiting for 
> > that
> >  * copy to complete using our fences before proceeding
> >  */
> > -  switch (buffer_type) {
> > -  case loader_dri3_buffer_back:
> > - if (buffer) {
> > -if (!buffer->linear_buffer) {
> > -   dri3_fence_reset(draw->conn, new_buffer);
> > -   dri3_fence_await(draw->conn, draw, buffer);
> > -   dri3_copy_area(draw->conn,
> > -  buffer->pixmap,
> > -  new_buffer->pixmap,
> > -  dri3_drawable_gc(draw),
> > -  0, 0, 0, 0,
> > -  draw->width, draw->height);
> > -   dri3_fence_trigger(draw->conn, new_buffer);
> > -} else if (draw->vtable->in_current_context(draw)) {
> > -   (void) loader_dri3_blit_image(draw,
> > - new_buffer->image,
> > - buffer->image,
> > - 0, 0, draw->width, 
> > draw->height,
> > - 0, 0, 0);
> > -}
> > -dri3_free_render_buffer(draw, buffer);
> > +  if ((buffer_type == loader_dri3_buffer_back ||
> > +   (buffer_type == loader_dri3_buffer_front && 
> > draw->have_fake_front))
> > +  && buffer) {
> > +
> > + /* Fill the new buffer with data from an old buffer */
> > + dri3_fence_await(draw->conn, draw, buffer);
> > + if (!loader_dri3_blit_image(draw,
> > + new_buffer->image,
> > + buffer->image,
> > + 0, 0, draw->width, draw->height,
> > + 0, 0, 0) &&
> > + !buffer->linear_buffer) {
> > +dri3_fence_reset(draw->conn, new_buffer);
> > +dri3_copy_area(draw->conn,
> > +   buffer->pixmap,
> > +   new_buffer->pixmap,
> > +   dri3_drawable_gc(draw),
> > +   0, 0, 0, 0,
> > +   draw->width, draw->height);
> > +dri3_fence_trigger(draw->conn, new_buffer);
> >}
> > - break;
> > -  case loader_dri3_buffer_front:
> > + dri3_free_render_buffer(draw, buffer);
> > +  } else if (buffer_type == loader_dri3_buffer_front) {
> > + /* Fill the new fake front with data from a real front */
> >loader_dri3_swapbuffer_barrier(draw);
> >dri3_fence_reset(draw->conn, new_buffer);
> >dri3_copy_area(draw->conn,
> > @@ -1407,8 +1407,7 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
> >   draw->width, draw->height);
> >dri3_fence_trigger(draw->conn, new_buffer);
> > - if (new_buffer->linear_buffer &&
> > - draw->vtable->in_current_context(draw)) {
> > + if (new_buffer->linear_buffer) {
> >   dri3_fence_await(draw->conn, draw, new_buffer);
> >   (void) loader_dri3_blit_image(draw,
> > new_buffer->image,
> > @@ -1416,7 +1415,6 @@ dri3_get_buffer(__DRIdrawable *driDrawable,
> > 0, 0, draw->width, draw->height,
> > 0, 0, 0);
> >}
> > - break;
> > }
> > 

Re: [Mesa-dev] [PATCH 0/4] i965: ARB_indirect_parameters

[Manolova, Plamena]

Thank you Ken!

On Tue, Oct 3, 2017 at 2:26 AM, Kenneth Graunke 
wrote:

> On Monday, October 2, 2017 1:58:23 PM PDT Plamena Manolova wrote:
> > A series of patches introducing ARB_indirect_parameters
> > for i965. We can implement ARB_indirect_parameters for i965
> > by taking advantage of the conditional rendering mechanism.
> > This works by issuing maxdrawcount draw calls and using
> > conditional rendering to predicate each of them with
> > "drawcount > gl_DrawID". The first three patches are part
> > of a necessary refactor of brw_try_draw_prims while the last
> > one actually introduces the functionality.
> >
> > Plamena Manolova (4):
> >   i965: Introduce brw_prepare_drawing.
> >   i965: Indroduce brw_finish_drawing.
> >   i965: Refactor brw_try_draw_prims.
> >   i965: Implement ARB_indirect_parameters.
> >
> >  src/mesa/drivers/dri/i965/brw_context.h  |   8 +
> >  src/mesa/drivers/dri/i965/brw_draw.c | 384
> ++-
> >  src/mesa/drivers/dri/i965/brw_draw.h |  10 +
> >  src/mesa/drivers/dri/i965/intel_extensions.c |   4 +-
> >  4 files changed, 273 insertions(+), 133 deletions(-)
>
> Looks great, Pam!  Thank you!
>
> Series is:
> Reviewed-by: Kenneth Graunke 
>
> and pushed:
>
> To ssh://git.freedesktop.org/git/mesa/mesa
>765e1fa3724..598d613dc31  master -> master
>
>
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[Mesa-dev] [PATCH] radeonsi: add a drirc workaround for HTILE corruption in ARK: Survival Evolved

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/driinfo_radeonsi.h |  4 
 src/gallium/drivers/radeonsi/si_blit.c  | 14 ++
 src/gallium/drivers/radeonsi/si_pipe.c  |  2 ++
 src/gallium/drivers/radeonsi/si_pipe.h  |  1 +
 src/util/drirc  |  5 +
 src/util/xmlpool/t_options.h|  5 +
 6 files changed, 31 insertions(+)

diff --git a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h 
b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
index 989e517..7f57b4e 100644
--- a/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
+++ b/src/gallium/drivers/radeonsi/driinfo_radeonsi.h
@@ -1,6 +1,10 @@
 // DriConf options specific to radeonsi
 DRI_CONF_SECTION_PERFORMANCE
 DRI_CONF_RADEONSI_ENABLE_SISCHED("false")
 DRI_CONF_RADEONSI_ASSUME_NO_Z_FIGHTS("false")
 DRI_CONF_RADEONSI_COMMUTATIVE_BLEND_ADD("false")
 DRI_CONF_SECTION_END
+
+DRI_CONF_SECTION_DEBUG
+   DRI_CONF_RADEONSI_CLEAR_DB_CACHE_BEFORE_CLEAR("false")
+DRI_CONF_SECTION_END
diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 67972a2..44e5251 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -896,20 +896,34 @@ static void si_clear(struct pipe_context *ctx, unsigned 
buffers,
if (!zstex->stencil_cleared || 
zstex->stencil_clear_value != stencil) {
sctx->db_stencil_disable_expclear = true;
}
 
zstex->stencil_clear_value = stencil;
sctx->framebuffer.dirty_zsbuf = true;
si_mark_atom_dirty(sctx, >framebuffer.atom); /* 
updates DB_STENCIL_CLEAR */
sctx->db_stencil_clear = true;
si_mark_atom_dirty(sctx, >db_render_state);
}
+
+   /* TODO: Find out what's wrong here. Fast depth clear leads to
+* corruption in ARK: Survival Evolved, but that may just be
+* a coincidence and the root cause is elsewhere.
+*
+* The corruption can be fixed by putting the DB flush before
+* or after the depth clear. (suprisingly)
+*
+* https://bugs.freedesktop.org/show_bug.cgi?id=102955 
(apitrace)
+*
+* This hack massively decreases back-to-back ClearDepth 
performance.
+*/
+   if (sctx->screen->clear_db_cache_before_clear)
+   sctx->b.flags |= SI_CONTEXT_FLUSH_AND_INV_DB;
}
 
si_blitter_begin(ctx, SI_CLEAR);
util_blitter_clear(sctx->blitter, fb->width, fb->height,
   util_framebuffer_get_num_layers(fb),
   buffers, color, depth, stencil);
si_blitter_end(ctx);
 
if (sctx->db_depth_clear) {
sctx->db_depth_clear = false;
diff --git a/src/gallium/drivers/radeonsi/si_pipe.c 
b/src/gallium/drivers/radeonsi/si_pipe.c
index 79e4e1c..7039aab 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.c
+++ b/src/gallium/drivers/radeonsi/si_pipe.c
@@ -1050,20 +1050,22 @@ struct pipe_screen *radeonsi_screen_create(struct 
radeon_winsys *ws,
 sscreen->b.info.pfp_fw_version >= 79 &&
 sscreen->b.info.me_fw_version >= 142);
 
sscreen->has_out_of_order_rast = sscreen->b.chip_class >= VI &&
 sscreen->b.info.max_se >= 2 &&
 !(sscreen->b.debug_flags & 
DBG_NO_OUT_OF_ORDER);
sscreen->assume_no_z_fights =
driQueryOptionb(config->options, "radeonsi_assume_no_z_fights");
sscreen->commutative_blend_add =
driQueryOptionb(config->options, 
"radeonsi_commutative_blend_add");
+   sscreen->clear_db_cache_before_clear =
+   driQueryOptionb(config->options, 
"radeonsi_clear_db_cache_before_clear");
sscreen->has_msaa_sample_loc_bug = (sscreen->b.family >= CHIP_POLARIS10 
&&
sscreen->b.family <= 
CHIP_POLARIS12) ||
   sscreen->b.family == CHIP_VEGA10 ||
   sscreen->b.family == CHIP_RAVEN;
sscreen->dpbb_allowed = sscreen->b.chip_class >= GFX9 &&
!(sscreen->b.debug_flags & DBG_NO_DPBB);
sscreen->dfsm_allowed = sscreen->dpbb_allowed &&
!(sscreen->b.debug_flags & DBG_NO_DFSM);
 
/* While it would be nice not to have this flag, we are constrained
diff --git a/src/gallium/drivers/radeonsi/si_pipe.h 
b/src/gallium/drivers/radeonsi/si_pipe.h
index b96bf9d..50f59b9 100644
--- a/src/gallium/drivers/radeonsi/si_pipe.h
+++ b/src/gallium/drivers/radeonsi/si_pipe.h
@@ -91,20 +91,21 @@ struct u_suballocator;
 

[Mesa-dev] [PATCH 5/5] radeonsi: inline struct si_sampler_views

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_blit.c| 12 +++
 src/gallium/drivers/radeonsi/si_debug.c   |  2 +-
 src/gallium/drivers/radeonsi/si_descriptors.c | 51 +--
 src/gallium/drivers/radeonsi/si_pipe.h|  6 +++-
 src/gallium/drivers/radeonsi/si_state.h   |  8 -
 5 files changed, 37 insertions(+), 42 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index 957254b..67972a2 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -73,24 +73,24 @@ static void si_blitter_begin(struct pipe_context *ctx, enum 
si_blitter_op op)
util_blitter_save_viewport(sctx->blitter, 
>viewports.states[0]);
util_blitter_save_scissor(sctx->blitter, 
>scissors.states[0]);
}
 
if (op & SI_SAVE_FRAMEBUFFER)
util_blitter_save_framebuffer(sctx->blitter, 
>framebuffer.state);
 
if (op & SI_SAVE_TEXTURES) {
util_blitter_save_fragment_sampler_states(
sctx->blitter, 2,
-   
(void**)sctx->samplers[PIPE_SHADER_FRAGMENT].views.sampler_states);
+   
(void**)sctx->samplers[PIPE_SHADER_FRAGMENT].sampler_states);
 
util_blitter_save_fragment_sampler_views(sctx->blitter, 2,
-   sctx->samplers[PIPE_SHADER_FRAGMENT].views.views);
+   sctx->samplers[PIPE_SHADER_FRAGMENT].views);
}
 
if (op & SI_DISABLE_RENDER_COND)
sctx->b.render_cond_force_off = true;
 }
 
 static void si_blitter_end(struct pipe_context *ctx)
 {
struct si_context *sctx = (struct si_context *)ctx;
 
@@ -426,21 +426,21 @@ si_decompress_sampler_depth_textures(struct si_context 
*sctx,
unsigned i;
unsigned mask = textures->needs_depth_decompress_mask;
 
while (mask) {
struct pipe_sampler_view *view;
struct si_sampler_view *sview;
struct r600_texture *tex;
 
i = u_bit_scan();
 
-   view = textures->views.views[i];
+   view = textures->views[i];
assert(view);
sview = (struct si_sampler_view*)view;
 
tex = (struct r600_texture *)view->texture;
assert(tex->db_compatible);
 
si_decompress_depth(sctx, tex,
sview->is_stencil_sampler ? PIPE_MASK_S : 
PIPE_MASK_Z,
view->u.tex.first_level, 
view->u.tex.last_level,
0, util_max_layer(>resource.b.b, 
view->u.tex.first_level));
@@ -552,21 +552,21 @@ si_decompress_sampler_color_textures(struct si_context 
*sctx,
 {
unsigned i;
unsigned mask = textures->needs_color_decompress_mask;
 
while (mask) {
struct pipe_sampler_view *view;
struct r600_texture *tex;
 
i = u_bit_scan();
 
-   view = textures->views.views[i];
+   view = textures->views[i];
assert(view);
 
tex = (struct r600_texture *)view->texture;
 
si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
view->u.tex.last_level);
}
 }
 
 static void
@@ -622,29 +622,29 @@ static void si_check_render_feedback_texture(struct 
si_context *sctx,
}
}
 
if (render_feedback)
si_texture_disable_dcc(>b, tex);
 }
 
 static void si_check_render_feedback_textures(struct si_context *sctx,
   struct si_samplers *textures)
 {
-   uint32_t mask = textures->views.enabled_mask;
+   uint32_t mask = textures->enabled_mask;
 
while (mask) {
const struct pipe_sampler_view *view;
struct r600_texture *tex;
 
unsigned i = u_bit_scan();
 
-   view = textures->views.views[i];
+   view = textures->views[i];
if(view->texture->target == PIPE_BUFFER)
continue;
 
tex = (struct r600_texture *)view->texture;
 
si_check_render_feedback_texture(sctx, tex,
 view->u.tex.first_level,
 view->u.tex.last_level,
 view->u.tex.first_layer,
 view->u.tex.last_layer);
diff --git a/src/gallium/drivers/radeonsi/si_debug.c 
b/src/gallium/drivers/radeonsi/si_debug.c
index 5075ccd..ddf65d6 100644
--- a/src/gallium/drivers/radeonsi/si_debug.c
+++ b/src/gallium/drivers/radeonsi/si_debug.c
@@ -729,21 +729,21 @@ static void si_dump_descriptors(struct si_context *sctx,

[Mesa-dev] [PATCH 3/5] radeonsi: fold needs_*_decompress_mask update into si_set_sampler_view

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_descriptors.c | 100 --
 1 file changed, 46 insertions(+), 54 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 1afdfbe..3835046 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -436,144 +436,136 @@ static void si_set_sampler_view_desc(struct si_context 
*sctx,
/* Disable FMASK and bind sampler state in [12:15]. */
memcpy(desc + 8, null_texture_descriptor, 4*4);
 
if (sstate)
si_set_sampler_state_desc(sstate, sview,
  is_buffer ? NULL : rtex,
  desc + 12);
}
 }
 
+static bool color_needs_decompression(struct r600_texture *rtex)
+{
+   return rtex->fmask.size ||
+  (rtex->dirty_level_mask &&
+   (rtex->cmask.size || rtex->dcc_offset));
+}
+
+static bool depth_needs_decompression(struct r600_texture *rtex)
+{
+   /* If the depth/stencil texture is TC-compatible, no decompression
+* will be done. The decompression function will only flush DB caches
+* to make it coherent with shaders. That's necessary because the driver
+* doesn't flush DB caches in any other case.
+*/
+   return rtex->db_compatible;
+}
+
 static void si_set_sampler_view(struct si_context *sctx,
unsigned shader,
unsigned slot, struct pipe_sampler_view *view,
bool disallow_early_out)
 {
-   struct si_sampler_views *views = >samplers[shader].views;
+   struct si_textures_info *samplers = >samplers[shader];
+   struct si_sampler_views *views = >views;
struct si_sampler_view *rview = (struct si_sampler_view*)view;
struct si_descriptors *descs = si_sampler_and_image_descriptors(sctx, 
shader);
unsigned desc_slot = si_get_sampler_slot(slot);
uint32_t *desc = descs->list + desc_slot * 16;
 
if (views->views[slot] == view && !disallow_early_out)
return;
 
if (view) {
struct r600_texture *rtex = (struct r600_texture 
*)view->texture;
 
si_set_sampler_view_desc(sctx, rview,
 views->sampler_states[slot], desc);
 
-   if (rtex->resource.b.b.target == PIPE_BUFFER)
+   if (rtex->resource.b.b.target == PIPE_BUFFER) {
rtex->resource.bind_history |= PIPE_BIND_SAMPLER_VIEW;
+   samplers->needs_depth_decompress_mask &= ~(1u << slot);
+   samplers->needs_color_decompress_mask &= ~(1u << slot);
+   } else {
+   if (depth_needs_decompression(rtex)) {
+   samplers->needs_depth_decompress_mask |= 1u << 
slot;
+   } else {
+   samplers->needs_depth_decompress_mask &= ~(1u 
<< slot);
+   }
+   if (color_needs_decompression(rtex)) {
+   samplers->needs_color_decompress_mask |= 1u << 
slot;
+   } else {
+   samplers->needs_color_decompress_mask &= ~(1u 
<< slot);
+   }
+
+   if (rtex->dcc_offset &&
+   p_atomic_read(>framebuffers_bound))
+   sctx->need_check_render_feedback = true;
+   }
 
pipe_sampler_view_reference(>views[slot], view);
views->enabled_mask |= 1u << slot;
 
/* Since this can flush, it must be done after enabled_mask is
 * updated. */
si_sampler_view_add_buffer(sctx, view->texture,
   RADEON_USAGE_READ,
   rview->is_stencil_sampler, true);
} else {
pipe_sampler_view_reference(>views[slot], NULL);
memcpy(desc, null_texture_descriptor, 8*4);
/* Only clear the lower dwords of FMASK. */
memcpy(desc + 8, null_texture_descriptor, 4*4);
/* Re-set the sampler state if we are transitioning from FMASK. 
*/
if (views->sampler_states[slot])
si_set_sampler_state_desc(views->sampler_states[slot], 
NULL, NULL,
  desc + 12);
 
views->enabled_mask &= ~(1u << slot);
+   samplers->needs_depth_decompress_mask &= ~(1u << slot);
+   samplers->needs_color_decompress_mask &= ~(1u << slot);
}
 
sctx->descriptors_dirty |= 1u << 

[Mesa-dev] [PATCH 2/5] radeonsi: simplify a loop in si_update_fb_dirtiness_after_rendering

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_state.c | 26 +++---
 1 file changed, 11 insertions(+), 15 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_state.c 
b/src/gallium/drivers/radeonsi/si_state.c
index 4965a83..f5abbf3 100644
--- a/src/gallium/drivers/radeonsi/si_state.c
+++ b/src/gallium/drivers/radeonsi/si_state.c
@@ -2644,35 +2644,31 @@ void si_update_fb_dirtiness_after_rendering(struct 
si_context *sctx)
 
if (sctx->framebuffer.state.zsbuf) {
struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
struct r600_texture *rtex = (struct r600_texture 
*)surf->texture;
 
rtex->dirty_level_mask |= 1 << surf->u.tex.level;
 
if (rtex->surface.has_stencil)
rtex->stencil_dirty_level_mask |= 1 << 
surf->u.tex.level;
}
-   if (sctx->framebuffer.compressed_cb_mask) {
-   struct pipe_surface *surf;
-   struct r600_texture *rtex;
-   unsigned mask = sctx->framebuffer.compressed_cb_mask;
-
-   do {
-   unsigned i = u_bit_scan();
-   surf = sctx->framebuffer.state.cbufs[i];
-   rtex = (struct r600_texture*)surf->texture;
-
-   if (rtex->fmask.size)
-   rtex->dirty_level_mask |= 1 << 
surf->u.tex.level;
-   if (rtex->dcc_gather_statistics)
-   rtex->separate_dcc_dirty = true;
-   } while (mask);
+
+   unsigned compressed_cb_mask = sctx->framebuffer.compressed_cb_mask;
+   while (compressed_cb_mask) {
+   unsigned i = u_bit_scan(_cb_mask);
+   struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
+   struct r600_texture *rtex = (struct r600_texture*)surf->texture;
+
+   if (rtex->fmask.size)
+   rtex->dirty_level_mask |= 1 << surf->u.tex.level;
+   if (rtex->dcc_gather_statistics)
+   rtex->separate_dcc_dirty = true;
}
 }
 
 static void si_dec_framebuffer_counters(const struct pipe_framebuffer_state 
*state)
 {
for (int i = 0; i < state->nr_cbufs; ++i) {
struct r600_surface *surf = NULL;
struct r600_texture *rtex;
 
if (!state->cbufs[i])
-- 
2.7.4

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[Mesa-dev] [PATCH 4/5] radeonsi: rename si_textures_info -> si_samplers, si_images_info -> si_images

[Marek Olšák]

From: Marek Olšák 

---
 src/gallium/drivers/radeonsi/si_blit.c| 10 +-
 src/gallium/drivers/radeonsi/si_descriptors.c | 22 +++---
 src/gallium/drivers/radeonsi/si_pipe.h|  8 
 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/src/gallium/drivers/radeonsi/si_blit.c 
b/src/gallium/drivers/radeonsi/si_blit.c
index b8ff67d..957254b 100644
--- a/src/gallium/drivers/radeonsi/si_blit.c
+++ b/src/gallium/drivers/radeonsi/si_blit.c
@@ -414,21 +414,21 @@ si_decompress_depth(struct si_context *sctx,
/* set_framebuffer_state takes care of coherency for single-sample.
 * The DB->CB copy uses CB for the final writes.
 */
if (copy_planes && tex->resource.b.b.nr_samples > 1)
si_make_CB_shader_coherent(sctx, tex->resource.b.b.nr_samples,
   false);
 }
 
 static void
 si_decompress_sampler_depth_textures(struct si_context *sctx,
-struct si_textures_info *textures)
+struct si_samplers *textures)
 {
unsigned i;
unsigned mask = textures->needs_depth_decompress_mask;
 
while (mask) {
struct pipe_sampler_view *view;
struct si_sampler_view *sview;
struct r600_texture *tex;
 
i = u_bit_scan();
@@ -541,21 +541,21 @@ si_decompress_color_texture(struct si_context *sctx, 
struct r600_texture *tex,
if (!tex->cmask.size && !tex->fmask.size && !tex->dcc_offset)
return;
 
si_blit_decompress_color(>b.b, tex, first_level, last_level, 0,
 util_max_layer(>resource.b.b, 
first_level),
 false);
 }
 
 static void
 si_decompress_sampler_color_textures(struct si_context *sctx,
-struct si_textures_info *textures)
+struct si_samplers *textures)
 {
unsigned i;
unsigned mask = textures->needs_color_decompress_mask;
 
while (mask) {
struct pipe_sampler_view *view;
struct r600_texture *tex;
 
i = u_bit_scan();
 
@@ -564,21 +564,21 @@ si_decompress_sampler_color_textures(struct si_context 
*sctx,
 
tex = (struct r600_texture *)view->texture;
 
si_decompress_color_texture(sctx, tex, view->u.tex.first_level,
view->u.tex.last_level);
}
 }
 
 static void
 si_decompress_image_color_textures(struct si_context *sctx,
-  struct si_images_info *images)
+  struct si_images *images)
 {
unsigned i;
unsigned mask = images->needs_color_decompress_mask;
 
while (mask) {
const struct pipe_image_view *view;
struct r600_texture *tex;
 
i = u_bit_scan();
 
@@ -620,21 +620,21 @@ static void si_check_render_feedback_texture(struct 
si_context *sctx,
render_feedback = true;
break;
}
}
 
if (render_feedback)
si_texture_disable_dcc(>b, tex);
 }
 
 static void si_check_render_feedback_textures(struct si_context *sctx,
-  struct si_textures_info 
*textures)
+  struct si_samplers *textures)
 {
uint32_t mask = textures->views.enabled_mask;
 
while (mask) {
const struct pipe_sampler_view *view;
struct r600_texture *tex;
 
unsigned i = u_bit_scan();
 
view = textures->views.views[i];
@@ -645,21 +645,21 @@ static void si_check_render_feedback_textures(struct 
si_context *sctx,
 
si_check_render_feedback_texture(sctx, tex,
 view->u.tex.first_level,
 view->u.tex.last_level,
 view->u.tex.first_layer,
 view->u.tex.last_layer);
}
 }
 
 static void si_check_render_feedback_images(struct si_context *sctx,
-struct si_images_info *images)
+struct si_images *images)
 {
uint32_t mask = images->enabled_mask;
 
while (mask) {
const struct pipe_image_view *view;
struct r600_texture *tex;
 
unsigned i = u_bit_scan();
 
view = >views[i];
diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c 
b/src/gallium/drivers/radeonsi/si_descriptors.c
index 3835046..788e7c3 100644
--- a/src/gallium/drivers/radeonsi/si_descriptors.c
+++ b/src/gallium/drivers/radeonsi/si_descriptors.c
@@ -458,21 

[Mesa-dev] [PATCH 1/5] ac: properly document a buffer.store LLVM workaround

[Marek Olšák]

From: Marek Olšák 

---
 src/amd/common/ac_llvm_build.c | 13 -
 src/amd/common/ac_llvm_build.h |  2 +-
 2 files changed, 9 insertions(+), 6 deletions(-)

diff --git a/src/amd/common/ac_llvm_build.c b/src/amd/common/ac_llvm_build.c
index 51fb009..0cebaa7 100644
--- a/src/amd/common/ac_llvm_build.c
+++ b/src/amd/common/ac_llvm_build.c
@@ -753,42 +753,45 @@ void
 ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
LLVMValueRef vdata,
unsigned num_channels,
LLVMValueRef voffset,
LLVMValueRef soffset,
unsigned inst_offset,
bool glc,
bool slc,
bool writeonly_memory,
-   bool has_add_tid)
+   bool swizzle_enable_hint)
 {
-   /* TODO: Fix stores with ADD_TID and remove the "has_add_tid" flag. */
-   if (!has_add_tid) {
+   /* SWIZZLE_ENABLE requires that soffset isn't folded into voffset
+* (voffset is swizzled, but soffset isn't swizzled).
+* llvm.amdgcn.buffer.store doesn't have a separate soffset parameter.
+*/
+   if (!swizzle_enable_hint) {
/* Split 3 channel stores, becase LLVM doesn't support 3-channel
 * intrinsics. */
if (num_channels == 3) {
LLVMValueRef v[3], v01;
 
for (int i = 0; i < 3; i++) {
v[i] = LLVMBuildExtractElement(ctx->builder, 
vdata,
LLVMConstInt(ctx->i32, i, 0), 
"");
}
v01 = ac_build_gather_values(ctx, v, 2);
 
ac_build_buffer_store_dword(ctx, rsrc, v01, 2, voffset,
soffset, inst_offset, glc, 
slc,
-   writeonly_memory, 
has_add_tid);
+   writeonly_memory, 
swizzle_enable_hint);
ac_build_buffer_store_dword(ctx, rsrc, v[2], 1, voffset,
soffset, inst_offset + 8,
glc, slc,
-   writeonly_memory, 
has_add_tid);
+   writeonly_memory, 
swizzle_enable_hint);
return;
}
 
unsigned func = CLAMP(num_channels, 1, 3) - 1;
static const char *types[] = {"f32", "v2f32", "v4f32"};
char name[256];
LLVMValueRef offset = soffset;
 
if (inst_offset)
offset = LLVMBuildAdd(ctx->builder, offset,
diff --git a/src/amd/common/ac_llvm_build.h b/src/amd/common/ac_llvm_build.h
index 1d6dc0a..ac8ea9c 100644
--- a/src/amd/common/ac_llvm_build.h
+++ b/src/amd/common/ac_llvm_build.h
@@ -163,21 +163,21 @@ void
 ac_build_buffer_store_dword(struct ac_llvm_context *ctx,
LLVMValueRef rsrc,
LLVMValueRef vdata,
unsigned num_channels,
LLVMValueRef voffset,
LLVMValueRef soffset,
unsigned inst_offset,
bool glc,
bool slc,
bool writeonly_memory,
-   bool has_add_tid);
+   bool swizzle_enable_hint);
 LLVMValueRef
 ac_build_buffer_load(struct ac_llvm_context *ctx,
 LLVMValueRef rsrc,
 int num_channels,
 LLVMValueRef vindex,
 LLVMValueRef voffset,
 LLVMValueRef soffset,
 unsigned inst_offset,
 unsigned glc,
 unsigned slc,
-- 
2.7.4

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Re: [Mesa-dev] [PATCH v2 03/11] isl: fill out layout descriptions for yuv formats

[Lionel Landwerlin]

On 03/10/17 18:09, Chad Versace wrote:

On Tue 03 Oct 2017, Lionel Landwerlin wrote:

Some description was missing.

Signed-off-by: Lionel Landwerlin 
---
  src/intel/isl/isl_format_layout.csv | 8 
  1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl_format_layout.csv 
b/src/intel/isl/isl_format_layout.csv
index f340e30a1bf..ebb3d22bc18 100644
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src/intel/isl/isl_format_layout.csv
@@ -222,8 +222,8 @@ I8_UINT ,   8,  1,  1,  1, , ,  
   , , ,  ui
  I8_SINT ,   8,  1,  1,  1, , , , , ,  
si8,, linear,
  DXT1_RGB_SRGB   ,  64,  4,  4,  1,  un4,  un4,  un4, , ,  
   ,,   srgb,  dxt1
  R1_UNORM,   1,  1,  1,  1,  un1, , , , ,  
   ,, linear,
-YCRCB_NORMAL,   0,  0,  0,  0, , , , , ,   
  ,,yuv,
-YCRCB_SWAPUVY   ,   0,  0,  0,  0, , , , , ,   
  ,,yuv,
+YCRCB_NORMAL,  16,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,,yuv,
+YCRCB_SWAPUVY   ,  16,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,,yuv,

If you override the meaning of the rgb channels when colorspace == yuv,
then you must also update any code that makes decisions by inspecting
the rgb channels but neglects to inspect the colorspace. As far as I can
tell, the only code that needs updating is the body of
isl_format_is_rgb().

Other than that, overrideing the channels here looks good to me.


Thanks,

Feels like it should almost have its own patch.
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Re: [Mesa-dev] [PATCH v2 04/11] anv: prepare formats to handle disjoints sets

[Chad Versace]

On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> Newer format enums start at offset 10, making it impossible to
> have them all in one table. This change splits the formats into sets
> that we then access through indirection.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/vulkan/anv_formats.c | 35 ++-
>  1 file changed, 26 insertions(+), 9 deletions(-)
> 
> diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
> index 049ffe17ac0..71824256b25 100644
> --- a/src/intel/vulkan/anv_formats.c
> +++ b/src/intel/vulkan/anv_formats.c
> @@ -58,7 +58,7 @@
>   * other.  The reason for this is that, for packed formats, the ISL (and
>   * bspec) names are in LSB -> MSB order while VK formats are MSB -> LSB.
>   */
> -static const struct anv_format anv_formats[] = {
> +static const struct anv_format main_formats[] = {
> fmt(VK_FORMAT_UNDEFINED,   ISL_FORMAT_UNSUPPORTED),
> fmt(VK_FORMAT_R4G4_UNORM_PACK8,ISL_FORMAT_UNSUPPORTED),
> fmt(VK_FORMAT_R4G4B4A4_UNORM_PACK16,   ISL_FORMAT_A4B4G4R4_UNORM),
> @@ -251,13 +251,30 @@ static const struct anv_format anv_formats[] = {
>  
>  #undef fmt
>  
> +static const struct {
> +   const struct anv_format *formats;
> +   uint32_t n_formats;
> +} anv_formats[] = {
> +   [0] = { .formats = main_formats, .n_formats = ARRAY_SIZE(main_formats), },
> +};
> +
> +static struct anv_format
> +format_extract(VkFormat vk_format)
> +{
> +   uint32_t enum_offset = vk_enum_offset(vk_format);
> +   uint32_t ext_number = vk_enum_extension(vk_format);
> +
> +   if (ext_number >= ARRAY_SIZE(anv_formats) ||
> +   enum_offset >= anv_formats[ext_number].n_formats)
> +  return (struct anv_format) { .isl_format = ISL_FORMAT_UNSUPPORTED };
> +
> +   return anv_formats[ext_number].formats[enum_offset];
> +}
> +
>  static bool
>  format_supported(VkFormat vk_format)
>  {
> -   if (vk_format >= ARRAY_SIZE(anv_formats))
> -  return false;
> -
> -   return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
> +   return format_extract(vk_format).isl_format != ISL_FORMAT_UNSUPPORTED;
>  }
>  
>  /**
> @@ -267,10 +284,10 @@ struct anv_format
>  anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
> VkImageAspectFlags aspect, VkImageTiling tiling)
>  {
> -   if (!format_supported(vk_format))
> -  return anv_formats[VK_FORMAT_UNDEFINED];
> +   struct anv_format format = format_extract(vk_format);
>  
> -   struct anv_format format = anv_formats[vk_format];
> +   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
> +  return format;
>  
> if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
>assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
> @@ -553,7 +570,7 @@ anv_get_image_format_properties(
>  ** This field cannot be ASTC format if the Surface Type is 
> SURFTYPE_1D.
>  */
> if (info->type == VK_IMAGE_TYPE_1D &&
> -   isl_format_is_compressed(anv_formats[info->format].isl_format)) {
> +   isl_format_is_compressed(format_extract(info->format).isl_format)) {

When I see format_extract(), I have no idea what it does. How about
giving it a name like format_to_anv(), vk_format_to_anv(), or even
something as simple as format_get()? Everyone has a general
understanding of what foobar_get() and foobar_to_stuff() does, but
I don't think foobar_extract() is as well understand.

As precedent, there is only one other function with 'extract' in its
name under src/intel, brw_vec4_surface_builder.cpp:emit_extract(). And,
as expected, emit_extract() is not a getter.
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Re: [Mesa-dev] [PATCH 03/44] i965/fs/nir: Use the nir_src_bit_size helper

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 05/09/17 16:12, Jason Ekstrand wrote:

---
  src/intel/compiler/brw_fs_nir.cpp | 12 +++-
  1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/src/intel/compiler/brw_fs_nir.cpp 
b/src/intel/compiler/brw_fs_nir.cpp
index d760946..18c5fc6 100644
--- a/src/intel/compiler/brw_fs_nir.cpp
+++ b/src/intel/compiler/brw_fs_nir.cpp
@@ -3448,9 +3448,7 @@ fs_visitor::nir_emit_cs_intrinsic(const fs_builder ,
 * expected by our 32-bit write messages.
 */
unsigned type_size = 4;
-  unsigned bit_size = instr->src[0].is_ssa ?
- instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size;
-  if (bit_size == 64) {
+  if (nir_src_bit_size(instr->src[0]) == 64) {
   type_size = 8;
   fs_reg tmp =
 fs_reg(VGRF, alloc.allocate(alloc.sizes[val_reg.nr]), 
val_reg.type);
@@ -3955,9 +3953,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
 * expected by our 32-bit write messages.
 */
unsigned type_size = 4;
-  unsigned bit_size = instr->src[0].is_ssa ?
- instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size;
-  if (bit_size == 64) {
+  if (nir_src_bit_size(instr->src[0]) == 64) {
   type_size = 8;
   fs_reg tmp =
 fs_reg(VGRF, alloc.allocate(alloc.sizes[val_reg.nr]), 
val_reg.type);
@@ -4022,9 +4018,7 @@ fs_visitor::nir_emit_intrinsic(const fs_builder , 
nir_intrinsic_instr *instr
  
unsigned num_components = instr->num_components;

unsigned first_component = nir_intrinsic_component(instr);
-  unsigned bit_size = instr->src[0].is_ssa ?
- instr->src[0].ssa->bit_size : instr->src[0].reg.reg->bit_size;
-  if (bit_size == 64) {
+  if (nir_src_bit_size(instr->src[0]) == 64) {
   fs_reg tmp =
  fs_reg(VGRF, alloc.allocate(2 * num_components),
 BRW_REGISTER_TYPE_F);



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Re: [Mesa-dev] [PATCH 02/44] nir: Get rid of the variable on vote intrinsics

[Lionel Landwerlin]

Reviewed-by: Lionel Landwerlin 

On 05/09/17 16:12, Jason Ekstrand wrote:

This looks like a copy+paste error.  They don't actually write into that
variable as would be implied by putting the return there.
---
  src/compiler/glsl/glsl_to_nir.cpp | 2 --
  src/compiler/nir/nir_intrinsics.h | 6 +++---
  2 files changed, 3 insertions(+), 5 deletions(-)

diff --git a/src/compiler/glsl/glsl_to_nir.cpp 
b/src/compiler/glsl/glsl_to_nir.cpp
index bb2ba17..c984c16 100644
--- a/src/compiler/glsl/glsl_to_nir.cpp
+++ b/src/compiler/glsl/glsl_to_nir.cpp
@@ -1165,8 +1165,6 @@ nir_visitor::visit(ir_call *ir)
case nir_intrinsic_vote_eq: {
   nir_ssa_dest_init(>instr, >dest, 1, 32, NULL);
  
- instr->variables[0] = evaluate_deref(>instr, ir->return_deref);

-
   ir_rvalue *value = (ir_rvalue *) ir->actual_parameters.get_head();
   instr->src[0] = nir_src_for_ssa(evaluate_rvalue(value));
  
diff --git a/src/compiler/nir/nir_intrinsics.h b/src/compiler/nir/nir_intrinsics.h

index ea51525..0de7080 100644
--- a/src/compiler/nir/nir_intrinsics.h
+++ b/src/compiler/nir/nir_intrinsics.h
@@ -121,9 +121,9 @@ BARRIER(memory_barrier_shared)
  INTRINSIC(discard_if, 1, ARR(1), false, 0, 0, 0, xx, xx, xx, 0)
  
  /** ARB_shader_group_vote intrinsics */

-INTRINSIC(vote_any, 1, ARR(1), true, 1, 1, 0, xx, xx, xx, 
NIR_INTRINSIC_CAN_ELIMINATE)
-INTRINSIC(vote_all, 1, ARR(1), true, 1, 1, 0, xx, xx, xx, 
NIR_INTRINSIC_CAN_ELIMINATE)
-INTRINSIC(vote_eq,  1, ARR(1), true, 1, 1, 0, xx, xx, xx, 
NIR_INTRINSIC_CAN_ELIMINATE)
+INTRINSIC(vote_any, 1, ARR(1), true, 1, 0, 0, xx, xx, xx, 
NIR_INTRINSIC_CAN_ELIMINATE)
+INTRINSIC(vote_all, 1, ARR(1), true, 1, 0, 0, xx, xx, xx, 
NIR_INTRINSIC_CAN_ELIMINATE)
+INTRINSIC(vote_eq,  1, ARR(1), true, 1, 0, 0, xx, xx, xx, 
NIR_INTRINSIC_CAN_ELIMINATE)
  
  /**

   * Basic Geometry Shader intrinsics.



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Re: [Mesa-dev] [PATCH] configure.ac: bump Clover LLVM requirement to 3.9

[Emil Velikov]

On 3 October 2017 at 18:05, Eric Engestrom  wrote:
> On Tuesday, 2017-10-03 16:51:16 +, Emil Velikov wrote:
>> From: Emil Velikov 
>>
>> The only driver that utilises Clover already depends on LLVM 3.9.
>> Additionally close to every supported distribution has said version.
>>
>> Additionally libclc requires LLVM 4.0 these days.
>>
>> With this in mind, there a handful of dead code that we could remove.
>> That will come with later commits.
>>
>> Note: this drops the LLVM 3.6 build from the Travis build. LLVM 3.9 (and
>> later) are already covered in there.
>>
>> Cc: Vedran Miletić 
>> Cc: Jan Vesely 
>> Cc: Aaron Watry 
>> Cc: Francisco Jerez 
>> Signed-off-by: Emil Velikov 
>
> Reviewed-by: Eric Engestrom 
>
> Can you add a link to the ML discussion?
>
Definitely, not sure why I did not think about that.

https://lists.freedesktop.org/archives/mesa-dev/2017-September/170028.html

-Emil
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Re: [Mesa-dev] [PATCH v2 03/11] isl: fill out layout descriptions for yuv formats

[Chad Versace]

On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> Some description was missing.
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/isl/isl_format_layout.csv | 8 
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/src/intel/isl/isl_format_layout.csv 
> b/src/intel/isl/isl_format_layout.csv
> index f340e30a1bf..ebb3d22bc18 100644
> --- a/src/intel/isl/isl_format_layout.csv
> +++ b/src/intel/isl/isl_format_layout.csv
> @@ -222,8 +222,8 @@ I8_UINT ,   8,  1,  1,  1, , 
> , , , ,  ui
>  I8_SINT ,   8,  1,  1,  1, , , , , , 
>  si8,, linear,
>  DXT1_RGB_SRGB   ,  64,  4,  4,  1,  un4,  un4,  un4, , , 
> ,,   srgb,  dxt1
>  R1_UNORM,   1,  1,  1,  1,  un1, , , , , 
> ,, linear,
> -YCRCB_NORMAL,   0,  0,  0,  0, , , , , , 
> ,,yuv,
> -YCRCB_SWAPUVY   ,   0,  0,  0,  0, , , , , , 
> ,,yuv,
> +YCRCB_NORMAL,  16,  1,  1,  1,  un8,  un8,  un8, , , 
> ,,yuv,
> +YCRCB_SWAPUVY   ,  16,  1,  1,  1,  un8,  un8,  un8, , , 
> ,,yuv,

If you override the meaning of the rgb channels when colorspace == yuv,
then you must also update any code that makes decisions by inspecting
the rgb channels but neglects to inspect the colorspace. As far as I can
tell, the only code that needs updating is the body of
isl_format_is_rgb().

Other than that, overrideing the channels here looks good to me.
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[Mesa-dev] [Bug 103078] MATLAB broken with mesa software rendering

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103078

--- Comment #1 from Emil Velikov  ---
Hi Sergio,

I won't be looking at the issue, I'm afraid yet here's a couple of
ideas/suggestions that should help:

- try to track down the first Mesa version (ideally a commit) that breaks
things
- isolate that the issue is not LLVM related by rebuilding mesa without it
- check that the correct libraries are picked (using strace or LD_DEBUG=libs) 
Matlab might be shipping libraries (say libc/libstdc++) that are older than the
ones Mesa is build against.
- try to get more verbose information of the issue - not sure if the dev. will
have a matlab license to debug themselves

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Re: [Mesa-dev] [PATCH] configure.ac: bump Clover LLVM requirement to 3.9

[Eric Engestrom]

On Tuesday, 2017-10-03 16:51:16 +, Emil Velikov wrote:
> From: Emil Velikov 
> 
> The only driver that utilises Clover already depends on LLVM 3.9.
> Additionally close to every supported distribution has said version.
> 
> Additionally libclc requires LLVM 4.0 these days.
> 
> With this in mind, there a handful of dead code that we could remove.
> That will come with later commits.
> 
> Note: this drops the LLVM 3.6 build from the Travis build. LLVM 3.9 (and
> later) are already covered in there.
> 
> Cc: Vedran Miletić 
> Cc: Jan Vesely 
> Cc: Aaron Watry 
> Cc: Francisco Jerez 
> Signed-off-by: Emil Velikov 

Reviewed-by: Eric Engestrom 

Can you add a link to the ML discussion?

> ---
> Vedran can we volunteer you for the cleanup ;-)
> ---
>  .travis.yml  | 38 --
>  configure.ac |  2 +-
>  2 files changed, 1 insertion(+), 39 deletions(-)
> 
> diff --git a/.travis.yml b/.travis.yml
> index d9a8bf5a9d4..1e5f6bcb702 100644
> --- a/.travis.yml
> +++ b/.travis.yml
> @@ -113,44 +113,6 @@ matrix:
>  - libx11-xcb-dev
>  - libelf-dev
>  - libunwind8-dev
> -- env:
> -# NOTE: Analogous to SWR above, building Clover is quite slow.
> -- LABEL="make Gallium ST Clover"
> -- BUILD=make
> -- MAKEFLAGS="-j4"
> -- MAKE_CHECK_COMMAND="true"
> -- LLVM_VERSION=3.6
> -- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
> -- OVERRIDE_CC=gcc-4.7
> -- OVERRIDE_CXX=g++-4.7
> -- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
> -- DRI_DRIVERS=""
> -- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
> --enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
> --disable-va --disable-omx-bellagio --disable-gallium-osmesa"
> -# i915 most likely doesn't work with OpenCL.
> -# Regardless - we're doing a quick build test here.
> -- GALLIUM_DRIVERS="i915"
> -- VULKAN_DRIVERS=""
> -- LIBUNWIND_FLAGS="--enable-libunwind"
> -  addons:
> -apt:
> -  sources:
> -- llvm-toolchain-trusty-3.6
> -  packages:
> -- libclc-dev
> -# LLVM packaging is broken and misses these dependencies
> -- libedit-dev
> -- g++-4.7
> -# From sources above
> -- llvm-3.6-dev
> -- clang-3.6
> -- libclang-3.6-dev
> -# Common
> -- xz-utils
> -- x11proto-xf86vidmode-dev
> -- libexpat1-dev
> -- libx11-xcb-dev
> -- libelf-dev
> -- libunwind8-dev
>  - env:
>  # NOTE: Analogous to SWR above, building Clover is quite slow.
>  - LABEL="make Gallium ST Clover LLVM-3.9"
> diff --git a/configure.ac b/configure.ac
> index cfc97d9f061..d62570fb14d 100644
> --- a/configure.ac
> +++ b/configure.ac
> @@ -101,7 +101,7 @@ ZLIB_REQUIRED=1.2.3
>  
>  dnl LLVM versions
>  LLVM_REQUIRED_GALLIUM=3.3.0
> -LLVM_REQUIRED_OPENCL=3.6.0
> +LLVM_REQUIRED_OPENCL=3.9.0
>  LLVM_REQUIRED_R600=3.9.0
>  LLVM_REQUIRED_RADEONSI=3.9.0
>  LLVM_REQUIRED_RADV=3.9.0
> -- 
> 2.14.1
> 
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Re: [Mesa-dev] [PATCH 2/2] egl/surfaceless: Use KMS swrast fallback

[Eric Engestrom]

On Tuesday, 2017-10-03 16:30:18 +, Gurchetan Singh wrote:
> Hi Eric,
> 
> Yes, you pushing this series would be great.

Done; since I was editing it anyway, I also moved the _eglLog() string
to avoid breaking it (makes grepping easier).

> I did run our test suite on this patchset as well.

You mean deqp, or another one?
I assume the results were "100% success"?

> 
> Best wishes,
> Gurchetan
> 
> On Tue, Oct 3, 2017 at 7:02 AM, Eric Engestrom 
> wrote:
> 
> > On Monday, 2017-10-02 20:48:24 +, gurchetansi...@chromium.org wrote:
> > > From: Gurchetan Singh 
> > >
> > > The kms_swrast extension is an actively developed software fallback,
> > > and platform_surfaceless can use it if there are no available
> > > hardware drivers.
> > >
> > > v2: Split into 2 patches, use booleans, check LIBGL_ALWAYS_SOFTWARE,
> > > and modify the eglLog level (Emil, Eric, Tomasz).
> >
> > Thanks, this is perfect :)
> >
> > Reviewed-by: Eric Engestrom 
> >
> > Do you want me to push this for you?
> >
> > It might be worth running deqp and other test suites to make sure
> > everything is wired up correctly.
> > (Given your chromium affiliation, I'm assuming you already know how to
> > use the surfaceless patches for deqp [1])
> >
> > [1] https://chromium.googlesource.com/chromiumos/overlays/
> > chromiumos-overlay/+/master/media-gfx/deqp
> >
> > > ---
> > >  src/egl/drivers/dri2/platform_surfaceless.c | 19 +++
> > >  1 file changed, 15 insertions(+), 4 deletions(-)
> > >
> > > diff --git a/src/egl/drivers/dri2/platform_surfaceless.c
> > b/src/egl/drivers/dri2/platform_surfaceless.c
> > > index f6aa217d39..b0a43ac9de 100644
> > > --- a/src/egl/drivers/dri2/platform_surfaceless.c
> > > +++ b/src/egl/drivers/dri2/platform_surfaceless.c
> > [snip]
> > > @@ -320,7 +324,14 @@ dri2_initialize_surfaceless(_EGLDriver *drv,
> > _EGLDisplay *disp)
> > >
> > > dri2_dpy->fd = -1;
> > > disp->DriverData = (void *) dri2_dpy;
> >
> > Nit: newline here
> > (I'll add it if/when I commit it, don't send a v3 for that)
> >
> > > -   if (!surfaceless_probe_device(disp)) {
> > > +   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false)) {
> > > +  driver_loaded = surfaceless_probe_device(disp, false);
> > > +  if (!driver_loaded)
> > > + _eglLog(_EGL_WARNING, "No hardware driver found, falling back
> > to "
> > > +  "software rendering");
> > > +   }
> > > +
> > > +   if (!driver_loaded && !surfaceless_probe_device(disp, true)) {
> > >err = "DRI2: failed to load driver";
> > >goto cleanup;
> > > }
> > > --
> > > 2.13.5
> > >
> >
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Re: [Mesa-dev] [PATCH] travis: add meson build for vulkan drivers.

[Dylan Baker]

Quoting Eric Engestrom (2017-10-03 08:29:12)
> On Monday, 2017-10-02 17:12:54 +, Dylan Baker wrote:
> > v2: - use -isystem`pwd` instead of cp to include fake linux header (Eric, 
> > Emil)
> > 
> > Signed-off-by: Dylan Baker 
> > ---
> >  .travis.yml | 36 
> >  1 file changed, 36 insertions(+)
> > 
> > diff --git a/.travis.yml b/.travis.yml
> > index d9a8bf5a9d4..ca766917f25 100644
> > --- a/.travis.yml
> > +++ b/.travis.yml
> > @@ -27,6 +27,7 @@ env:
> >  - WAYLAND_PROTOCOLS_VERSION=wayland-protocols-1.8
> >  - 
> > PKG_CONFIG_PATH=$HOME/prefix/lib/pkgconfig:$HOME/prefix/share/pkgconfig
> >  - LD_LIBRARY_PATH="$HOME/prefix/lib:$LD_LIBRARY_PATH"
> > +- PATH="$HOME/prefix/bin:$PATH"
> >  
> >  matrix:
> >include:
> > @@ -393,10 +394,34 @@ matrix:
> >  - libexpat1-dev
> >  - libx11-xcb-dev
> >  - libelf-dev
> > +- env:
> > +- LABEL="meson Vulkan"
> > +- BUILD=meson
> > +- MESON_OPTIONS="-Dbuild-tests=true"
> > +  addons:
> > +apt:
> > +  sources:
> > +- llvm-toolchain-trusty-3.9
> > +  packages:
> > +# LLVM packaging is broken and misses these dependencies
> > +- libedit-dev
> > +# From sources above
> > +- llvm-3.9-dev
> > +# Common
> > +- xz-utils
> > +- libexpat1-dev
> > +- libelf-dev
> > +- python3-pip
> >  
> >  install:
> >- pip install --user mako
> >  
> > +  # Install the latest meson from pip, since the version in the ubuntu 
> > repos is
> > +  # often quite old.
> > +  - if test "x$BUILD" = xmeson; then
> > +  pip3 install --user meson;
> > +fi
> > +
> ># Since libdrm gets updated in configure.ac regularly, try to pick up the
> ># latest version from there.
> >- for line in `grep "^LIBDRM.*_REQUIRED=" configure.ac`; do
> > @@ -471,6 +496,11 @@ install:
> >- tar -axvf $WAYLAND_PROTOCOLS_VERSION.tar.xz
> >- (cd $WAYLAND_PROTOCOLS_VERSION && ./configure --prefix=$HOME/prefix && 
> > make install)
> >  
> > +  # Meson requires ninja >= 1.6, but trusty has 1.3.x
> > +  - wget 
> > https://github.com/ninja-build/ninja/releases/download/v1.6.0/ninja-linux.zip;
> > +  - unzip ninja-linux.zip
> > +  - mv ninja $HOME/prefix/bin/
> > +
> ># Generate the header since one is missing on the Travis instance
> >- mkdir -p linux
> >- printf "%s\n" \
> > @@ -510,3 +540,9 @@ script:
> >test -n "$OVERRIDE_CXX" && export CXX="$OVERRIDE_CXX";
> >scons $SCONS_TARGET && eval $SCONS_CHECK_COMMAND;
> >  fi
> > +
> > +  - if test "x$BUILD" = xmeson; then
> > +  export CC="$CC -isystem`pwd`";
> 
> I also missed that in the make script :]
> I'd feel more comfortable having flags like this in the CFLAGS though,
> but I guess for now it's better to have consistency.
> 
> Just to confirm, the series is
> Reviewed-by: Eric Engestrom 
> 
> You have commit rights, right?

I do :)

Dylan

> 
> > +  meson _build $MESON_OPTIONS;
> > +  ninja -C _build test;
> > +fi
> > -- 
> > 2.14.1
> > 


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[Mesa-dev] [PATCH] configure.ac: bump Clover LLVM requirement to 3.9

[Emil Velikov]

From: Emil Velikov 

The only driver that utilises Clover already depends on LLVM 3.9.
Additionally close to every supported distribution has said version.

Additionally libclc requires LLVM 4.0 these days.

With this in mind, there a handful of dead code that we could remove.
That will come with later commits.

Note: this drops the LLVM 3.6 build from the Travis build. LLVM 3.9 (and
later) are already covered in there.

Cc: Vedran Miletić 
Cc: Jan Vesely 
Cc: Aaron Watry 
Cc: Francisco Jerez 
Signed-off-by: Emil Velikov 
---
Vedran can we volunteer you for the cleanup ;-)
---
 .travis.yml  | 38 --
 configure.ac |  2 +-
 2 files changed, 1 insertion(+), 39 deletions(-)

diff --git a/.travis.yml b/.travis.yml
index d9a8bf5a9d4..1e5f6bcb702 100644
--- a/.travis.yml
+++ b/.travis.yml
@@ -113,44 +113,6 @@ matrix:
 - libx11-xcb-dev
 - libelf-dev
 - libunwind8-dev
-- env:
-# NOTE: Analogous to SWR above, building Clover is quite slow.
-- LABEL="make Gallium ST Clover"
-- BUILD=make
-- MAKEFLAGS="-j4"
-- MAKE_CHECK_COMMAND="true"
-- LLVM_VERSION=3.6
-- LLVM_CONFIG="llvm-config-${LLVM_VERSION}"
-- OVERRIDE_CC=gcc-4.7
-- OVERRIDE_CXX=g++-4.7
-- DRI_LOADERS="--disable-glx --disable-gbm --disable-egl"
-- DRI_DRIVERS=""
-- GALLIUM_ST="--disable-dri --enable-opencl --enable-opencl-icd 
--enable-llvm --disable-xa --disable-nine --disable-xvmc --disable-vdpau 
--disable-va --disable-omx-bellagio --disable-gallium-osmesa"
-# i915 most likely doesn't work with OpenCL.
-# Regardless - we're doing a quick build test here.
-- GALLIUM_DRIVERS="i915"
-- VULKAN_DRIVERS=""
-- LIBUNWIND_FLAGS="--enable-libunwind"
-  addons:
-apt:
-  sources:
-- llvm-toolchain-trusty-3.6
-  packages:
-- libclc-dev
-# LLVM packaging is broken and misses these dependencies
-- libedit-dev
-- g++-4.7
-# From sources above
-- llvm-3.6-dev
-- clang-3.6
-- libclang-3.6-dev
-# Common
-- xz-utils
-- x11proto-xf86vidmode-dev
-- libexpat1-dev
-- libx11-xcb-dev
-- libelf-dev
-- libunwind8-dev
 - env:
 # NOTE: Analogous to SWR above, building Clover is quite slow.
 - LABEL="make Gallium ST Clover LLVM-3.9"
diff --git a/configure.ac b/configure.ac
index cfc97d9f061..d62570fb14d 100644
--- a/configure.ac
+++ b/configure.ac
@@ -101,7 +101,7 @@ ZLIB_REQUIRED=1.2.3
 
 dnl LLVM versions
 LLVM_REQUIRED_GALLIUM=3.3.0
-LLVM_REQUIRED_OPENCL=3.6.0
+LLVM_REQUIRED_OPENCL=3.9.0
 LLVM_REQUIRED_R600=3.9.0
 LLVM_REQUIRED_RADEONSI=3.9.0
 LLVM_REQUIRED_RADV=3.9.0
-- 
2.14.1

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Re: [Mesa-dev] [PATCH v2 02/11] isl: make format layout channels accessible by index

[Chad Versace]

On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/intel/isl/isl.h | 21 -
>  1 file changed, 12 insertions(+), 9 deletions(-)

Patch 2 is
Reviewed-by: Chad Versace 
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[Mesa-dev] [Bug 103078] MATLAB broken with mesa software rendering

[bugzilla-daemon]

https://bugs.freedesktop.org/show_bug.cgi?id=103078

Bug ID: 103078
   Summary: MATLAB broken with mesa software rendering
   Product: Mesa
   Version: git
  Hardware: x86-64 (AMD64)
OS: Linux (All)
Status: NEW
  Severity: major
  Priority: medium
 Component: Drivers/X11
  Assignee: mesa-dev@lists.freedesktop.org
  Reporter: sergio.calleg...@gmail.com
QA Contact: mesa-dev@lists.freedesktop.org

Software rendering with recent mesa (either LLVMPipe, softpipe or swr) breaks
matlab.

Seen with MATLAB 2016a on Kubuntu 17.04 with the latest (git) mesa as of today.

Graphic commands (e.g. plot) hang and make it impossible to close Matlab
cleanly.

On llvmpipe the 'opengl info' matlab command crashes with

Error using hgopengl
Java exception occurred:
java.lang.RuntimeException: Waited 5000ms for: <38d5ebf2, 64757a04>[count 2 [
add. 0, orig 2], qsz 0, owner
, add.owner Startup Class Loader-SharedResourceRunner] -

at
jogamp.common.util.locks.RecursiveLockImpl01Unfairish.lock(RecursiveLockImpl01Unfairish.java:198)
at com.jogamp.opengl.GLProfile.initSingleton(GLProfile.java:199)
at com.jogamp.opengl.GLProfile.getDefaultDevice(GLProfile.java:2003)
at com.jogamp.opengl.GLCapabilities.(GLCapabilities.java:84)
at
com.mathworks.hg.uij.OpenGLUtils$MyGLListener.getGLInformation(OpenGLUtils.java:320)
at
com.mathworks.hg.uij.OpenGLUtils$MyGLListener.getGLData(OpenGLUtils.java:498)
at com.mathworks.hg.uij.OpenGLUtils.getGLData(OpenGLUtils.java:78)

Error in hgopengl

On softpipe, the same command hangs.

This is curious because matlab has itself a software rendering mode, that seems
to rely on mesa X11. The opengl info for it returns

  Version: '2.1 Mesa 10.5.2'
   Vendor: 'Brian Paul'
 Renderer: 'Mesa X11'
   MaxTextureSize: 16384
   Visual: 'Visual 0x72, (RGBA 32 bits (8 8 8 8), Z
depth 16 bits, Hardware acceleratio…'
 Software: 'true'
 HardwareSupportLevel: 'none (known graphics driver issues)'
SupportsGraphicsSmoothing: 0
SupportsDepthPeelTransparency: 1
   SupportsAlignVertexCenters: 0
   Extensions: {151x1 cell}
   MaxFrameBufferSize: 16384

So, it looks like mesa was supporting matlab 2016a just fine at the time of
10.5.2 and that we are now facing a regression.

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Re: [Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Chad Versace]

On Tue 03 Oct 2017, Lionel Landwerlin wrote:
> v2: Simplify offset enum computation (Jason)
> 
> Signed-off-by: Lionel Landwerlin 
> ---
>  src/vulkan/util/vk_util.h | 6 ++
>  1 file changed, 6 insertions(+)
> 
> diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
> index 2ed601f881e..8c8cb64d513 100644
> --- a/src/vulkan/util/vk_util.h
> +++ b/src/vulkan/util/vk_util.h
> @@ -199,4 +199,10 @@ __vk_find_struct(void *start, VkStructureType sType)
>  
>  uint32_t vk_get_driver_version(void);
>  
> +#define VK_EXT_OFFSET (10UL)
> +#define vk_enum_extension(__enum) \
> +   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET) / 1000UL) + 1) 
> : 0)
> +#define vk_enum_offset(__enum) \
> +   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))

The macro functions, when called, look like regular functions due to
being lowercase. But they don't behave like functions; their arguments
suffer from the multiple evaluation disease.

Please rename the macros to be all uppercase, so callers' expectations
will be set correctly. Or, even better, define them as inline
functions.
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Re: [Mesa-dev] [PATCH v2 3/7] travis: Add clover build using llvm-3.7

[Eric Engestrom]

On Tuesday, 2017-10-03 12:28:54 -0400, Jan Vesely wrote:
> On Tue, 2017-10-03 at 17:26 +0100, Eric Engestrom wrote:
> > On Friday, 2017-09-29 16:32:36 +, Jan Vesely wrote:
> > > On Mon, 2017-09-18 at 16:46 +0100, Eric Engestrom wrote:
> > > > On Monday, 2017-09-18 11:10:37 -0400, Jan Vesely wrote:
> > > > > On Mon, 2017-09-18 at 11:13 +0100, Eric Engestrom wrote:
> > > > > > On Sunday, 2017-09-17 02:02:33 -0400, Jan Vesely wrote:
> > > > > > > v2: Use direct llvm repo link instead of alias
> > > > > > > Enable
> > > > > > > 
> > > > > > > Signed-off-by: Jan Vesely 
> > > > > > > ---
> > > > > > >  .travis.yml | 40 
> > > > > > >  1 file changed, 40 insertions(+)
> > > > > > > 
> > > > > > > diff --git a/.travis.yml b/.travis.yml
> > > > > > > index 0012d27dc7..638ec2a78a 100644
> > > > > > > --- a/.travis.yml
> > > > > > > +++ b/.travis.yml
> > > > > > > @@ -152,6 +152,46 @@ matrix:
> > > > > > >  - libelf-dev
> > > > > > >  - libunwind8-dev
> > > > > > >  - env:
> > > > > > > +# Disable for now since travis does not allow 
> > > > > > > llvm-toolchain-trusty-3.7
> > > > > > 
> > > > > > You can drop this line now :)
> > > > > 
> > > > > Fixed locally.
> > > > > 
> > > > > > 
> > > > > > Don't 4.0 and 5.0 need the same binutils-2.26 as 3.9?
> > > > 
> > > > You didn't answer this; isn't it needed?
> > > > 
> > > > > > Speaking of, I think the OVERRIDE_PATH you added is the only way to 
> > > > > > do this.
> > > > > > 
> > > > > > With the above fixed or justified, the series is:
> > > > > > Reviewed-by: Eric Engestrom 
> > > > > 
> > > > > thanks.
> > > > > 
> > > > > > 
> > > > > > One thing before anyone pushes this however: this will make the 
> > > > > > builds
> > > > > > much longer; is the gain of testing every supported llvm version 
> > > > > > worth it?
> > > > > 
> > > > > It does not really make builds that much worse after the ccache has
> > > > > warmed up:
> > > > > https://travis-ci.org/jvesely/mesa/builds/276686220
> > > > > building SWR is the elephant and it leaves time to build these in
> > > > > parallel.
> > > > 
> > > > Looking at the numbers, I'm convinced :)
> > > > Do you have push access, or do you want me to push the series for you?
> > > > 
> > > > (Note: typo in the subject of patch 6/7)
> > > 
> > > sorry, I missed this part the first time.
> > > I've fixed the typo in patch 6 and pushed patches 5/6/7 per discussion
> > > with Emil.
> > 
> > Don't we want to drop the 3.6 build then?
> 
> I've left it for Emil to remove in the same patch(or series) that drops
> clover llvm<3.9 support. seemed like a good idea to keep around until
> then.

Very good point :)
I'll leave it alone.

> 
> Jan
> 
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[Mesa-dev] [PATCH v2 11/11] anv: enable VK_KHR_sampler_ycbcr_conversion

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_device.c  | 69 +-
 src/intel/vulkan/anv_extensions.py |  1 +
 src/intel/vulkan/anv_formats.c | 59 
 src/intel/vulkan/anv_image.c   | 42 ---
 src/intel/vulkan/anv_private.h |  4 +++
 src/intel/vulkan/genX_state.c  | 50 ++-
 6 files changed, 194 insertions(+), 31 deletions(-)

diff --git a/src/intel/vulkan/anv_device.c b/src/intel/vulkan/anv_device.c
index d576bb55315..1a5eee8a0b7 100644
--- a/src/intel/vulkan/anv_device.c
+++ b/src/intel/vulkan/anv_device.c
@@ -703,6 +703,13 @@ void anv_GetPhysicalDeviceFeatures2KHR(
  break;
   }
 
+  case 
VK_STRUCTURE_TYPE_PHYSICAL_DEVICE_SAMPLER_YCBCR_CONVERSION_FEATURES_KHR: {
+ VkPhysicalDeviceSamplerYcbcrConversionFeaturesKHR *features =
+(VkPhysicalDeviceSamplerYcbcrConversionFeaturesKHR *) ext;
+ features->samplerYcbcrConversion = true;
+ break;
+  }
+
   default:
  anv_debug_ignored_stype(ext->sType);
  break;
@@ -721,8 +728,12 @@ void anv_GetPhysicalDeviceProperties(
const uint32_t max_raw_buffer_sz = devinfo->gen >= 7 ?
   (1ul << 30) : (1ul << 27);
 
+   /* These numbers have to account for multiplanar images where we rebuild
+* things using shader snippets.
+*/
const uint32_t max_samplers = (devinfo->gen >= 8 || devinfo->is_haswell) ?
- 128 : 16;
+ (128 / 3) : (16 / 3);
+   const uint32_t max_descriptors = 256 / 3;
 
VkSampleCountFlags sample_counts =
   isl_device_get_sample_counts(>isl_dev);
@@ -749,14 +760,14 @@ void anv_GetPhysicalDeviceProperties(
   .maxPerStageDescriptorStorageImages   = 64,
   .maxPerStageDescriptorInputAttachments= 64,
   .maxPerStageResources = 250,
-  .maxDescriptorSetSamplers = 256,
-  .maxDescriptorSetUniformBuffers   = 256,
+  .maxDescriptorSetSamplers = max_descriptors,
+  .maxDescriptorSetUniformBuffers   = max_descriptors,
   .maxDescriptorSetUniformBuffersDynamic= MAX_DYNAMIC_BUFFERS / 2,
-  .maxDescriptorSetStorageBuffers   = 256,
+  .maxDescriptorSetStorageBuffers   = max_descriptors,
   .maxDescriptorSetStorageBuffersDynamic= MAX_DYNAMIC_BUFFERS / 2,
-  .maxDescriptorSetSampledImages= 256,
-  .maxDescriptorSetStorageImages= 256,
-  .maxDescriptorSetInputAttachments = 256,
+  .maxDescriptorSetSampledImages= max_descriptors,
+  .maxDescriptorSetStorageImages= max_descriptors,
+  .maxDescriptorSetInputAttachments = max_descriptors,
   .maxVertexInputAttributes = MAX_VBS,
   .maxVertexInputBindings   = MAX_VBS,
   .maxVertexInputAttributeOffset= 2047,
@@ -1826,8 +1837,48 @@ void anv_GetImageMemoryRequirements2KHR(
 const VkImageMemoryRequirementsInfo2KHR*pInfo,
 VkMemoryRequirements2KHR*   pMemoryRequirements)
 {
-   anv_GetImageMemoryRequirements(_device, pInfo->image,
-  >memoryRequirements);
+   if (pInfo->pNext == NULL) {
+  anv_GetImageMemoryRequirements(_device, pInfo->image,
+ >memoryRequirements);
+   } else {
+  vk_foreach_struct_const(ext, pInfo->pNext) {
+ switch (ext->sType) {
+ case VK_STRUCTURE_TYPE_IMAGE_PLANE_MEMORY_REQUIREMENTS_INFO_KHR: {
+ANV_FROM_HANDLE(anv_image, image, pInfo->image);
+ANV_FROM_HANDLE(anv_device, device, _device);
+struct anv_physical_device *pdevice = 
>instance->physicalDevice;
+const VkImagePlaneMemoryRequirementsInfoKHR *plane_reqs =
+   (const VkImagePlaneMemoryRequirementsInfoKHR *) ext;
+uint32_t plane = anv_image_aspect_to_plane(image->aspects,
+   
plane_reqs->planeAspect);
+
+assert(image->planes[plane].offset == 0);
+
+/* The Vulkan spec (git aaed022) says:
+ *
+ *memoryTypeBits is a bitfield and contains one bit set for
+ *every supported memory type for the resource. The bit `1<memoryRequirements.memoryTypeBits =
+   (1ull << pdevice->memory.type_count) - 1;
+
+pMemoryRequirements->memoryRequirements.size = 
image->planes[plane].size;

[Mesa-dev] [PATCH v2 05/11] anv: modify the internal concept of format to express multiple planes

[Lionel Landwerlin]

A given Vulkan format can now be decomposed into a set of planes. We
now use 'struct anv_format_plane' to represent the format of those
planes.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_blorp.c |  31 +--
 src/intel/vulkan/anv_formats.c   | 505 ---
 src/intel/vulkan/anv_image.c |  27 ++-
 src/intel/vulkan/anv_private.h   |  54 -
 src/intel/vulkan/genX_pipeline.c |  14 +-
 5 files changed, 351 insertions(+), 280 deletions(-)

diff --git a/src/intel/vulkan/anv_blorp.c b/src/intel/vulkan/anv_blorp.c
index 8dead1d87a8..72f482625aa 100644
--- a/src/intel/vulkan/anv_blorp.c
+++ b/src/intel/vulkan/anv_blorp.c
@@ -323,8 +323,9 @@ copy_buffer_to_image(struct anv_cmd_buffer *cmd_buffer,
   }
 
   const enum isl_format buffer_format =
- anv_get_isl_format(_buffer->device->info, anv_image->vk_format,
-aspect, VK_IMAGE_TILING_LINEAR);
+ anv_get_isl_plane_format(_buffer->device->info,
+  anv_image->vk_format,
+  aspect, VK_IMAGE_TILING_LINEAR);
 
   const VkExtent3D bufferImageExtent = {
  .width  = pRegions[r].bufferRowLength ?
@@ -459,12 +460,12 @@ void anv_CmdBlitImage(
   get_blorp_surf_for_anv_image(dst_image, dst_res->aspectMask,
dst_image->aux_usage, );
 
-  struct anv_format src_format =
- anv_get_format(_buffer->device->info, src_image->vk_format,
-src_res->aspectMask, src_image->tiling);
-  struct anv_format dst_format =
- anv_get_format(_buffer->device->info, dst_image->vk_format,
-dst_res->aspectMask, dst_image->tiling);
+  struct anv_format_plane src_format =
+ anv_get_plane_format(_buffer->device->info, src_image->vk_format,
+  src_res->aspectMask, src_image->tiling);
+  struct anv_format_plane dst_format =
+ anv_get_plane_format(_buffer->device->info, dst_image->vk_format,
+  dst_res->aspectMask, dst_image->tiling);
 
   unsigned dst_start, dst_end;
   if (dst_image->type == VK_IMAGE_TYPE_3D) {
@@ -758,9 +759,9 @@ void anv_CmdClearColorImage(
 
   assert(pRanges[r].aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 
-  struct anv_format src_format =
- anv_get_format(_buffer->device->info, image->vk_format,
-VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
+  struct anv_format_plane src_format =
+ anv_get_plane_format(_buffer->device->info, image->vk_format,
+  VK_IMAGE_ASPECT_COLOR_BIT, image->tiling);
 
   unsigned base_layer = pRanges[r].baseArrayLayer;
   unsigned layer_count = anv_get_layerCount(image, [r]);
@@ -974,10 +975,10 @@ clear_depth_stencil_attachment(struct anv_cmd_buffer 
*cmd_buffer,
 
enum isl_format depth_format = ISL_FORMAT_UNSUPPORTED;
if (clear_depth) {
-  depth_format = anv_get_isl_format(_buffer->device->info,
-pass_att->format,
-VK_IMAGE_ASPECT_DEPTH_BIT,
-VK_IMAGE_TILING_OPTIMAL);
+  depth_format = anv_get_isl_plane_format(_buffer->device->info,
+  pass_att->format,
+  VK_IMAGE_ASPECT_DEPTH_BIT,
+  VK_IMAGE_TILING_OPTIMAL);
}
 
uint32_t binding_table;
diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 71824256b25..8dd87133c0c 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -44,14 +44,33 @@
 #define BGRA _ISL_SWIZZLE(BLUE, GREEN, RED, ALPHA)
 #define RGB1 _ISL_SWIZZLE(RED, GREEN, BLUE, ONE)
 
-#define swiz_fmt(__vk_fmt, __hw_fmt, __swizzle) \
-   [__vk_fmt] = { \
-  .isl_format = __hw_fmt, \
-  .swizzle = __swizzle, \
+#define _fmt(__hw_fmt, __swizzle) \
+   { .isl_format = __hw_fmt, \
+ .swizzle = __swizzle }
+
+#define swiz_fmt1(__vk_fmt, __hw_fmt, __swizzle) \
+   [vk_enum_offset(__vk_fmt)] = { \
+  .planes = { \
+  { .isl_format = __hw_fmt, .swizzle = __swizzle }, \
+  }, \
+  .n_planes = 1, \
}
 
-#define fmt(__vk_fmt, __hw_fmt) \
-   swiz_fmt(__vk_fmt, __hw_fmt, RGBA)
+#define fmt1(__vk_fmt, __hw_fmt) \
+   swiz_fmt1(__vk_fmt, __hw_fmt, RGBA)
+
+#define ds_fmt(__vk_fmt, __depth_fmt, __stencil_fmt) \
+   [vk_enum_offset(__vk_fmt)] = { \
+  .planes = { \
+ { .isl_format = __depth_fmt, \
+   .swizzle = RGBA,   \
+ }, \
+ { .isl_format = __stencil_fmt, \
+   .swizzle = RGBA,   \
+ }, \
+  }, \
+  .n_planes = 2, \
+   }
 
 /* HINT: For array formats, the ISL name should match the VK name.  For
  * packed formats, they should have the channels 

[Mesa-dev] [PATCH v2 08/11] anv: prepare sampler emission code for multiplanar images

[Lionel Landwerlin]

New settings from the KHR_sampler_ycbcr_conversion specifications
might require different sampler settings for luma and chroma planes.
This change makes the sampler table emission ready to handle multiple
planes.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_private.h |  2 +-
 src/intel/vulkan/genX_cmd_buffer.c |  2 +-
 src/intel/vulkan/genX_state.c  | 80 +++---
 3 files changed, 43 insertions(+), 41 deletions(-)

diff --git a/src/intel/vulkan/anv_private.h b/src/intel/vulkan/anv_private.h
index 2b2598af4d1..63b803df6ea 100644
--- a/src/intel/vulkan/anv_private.h
+++ b/src/intel/vulkan/anv_private.h
@@ -2568,7 +2568,7 @@ void anv_fill_buffer_surface_state(struct anv_device 
*device,
uint32_t stride);
 
 struct anv_sampler {
-   uint32_t state[4];
+   uint32_t state[3][4];
uint32_t n_planes;
 };
 
diff --git a/src/intel/vulkan/genX_cmd_buffer.c 
b/src/intel/vulkan/genX_cmd_buffer.c
index 367fddcf02a..dc5cf687dc6 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -1745,7 +1745,7 @@ emit_samplers(struct anv_cmd_buffer *cmd_buffer,
   }
 
   memcpy(state->map + (s * 16),
- sampler->state, sizeof(sampler->state));
+ sampler->state, sampler->n_planes * sizeof(sampler->state[0]));
 
   s += sampler->n_planes;
}
diff --git a/src/intel/vulkan/genX_state.c b/src/intel/vulkan/genX_state.c
index 81570825a54..91da05cddbf 100644
--- a/src/intel/vulkan/genX_state.c
+++ b/src/intel/vulkan/genX_state.c
@@ -166,7 +166,7 @@ VkResult genX(CreateSampler)(
 
assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO);
 
-   sampler = vk_alloc2(>alloc, pAllocator, sizeof(*sampler), 8,
+   sampler = vk_zalloc2(>alloc, pAllocator, sizeof(*sampler), 8,
 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
if (!sampler)
   return vk_error(VK_ERROR_OUT_OF_HOST_MEMORY);
@@ -181,55 +181,57 @@ VkResult genX(CreateSampler)(
bool enable_mag_filter_addr_rounding =
   pCreateInfo->magFilter != VK_FILTER_NEAREST;
 
-   struct GENX(SAMPLER_STATE) sampler_state = {
-  .SamplerDisable = false,
-  .TextureBorderColorMode = DX10OGL,
+   for (unsigned p = 0; p < sampler->n_planes; p++) {
+  struct GENX(SAMPLER_STATE) sampler_state = {
+ .SamplerDisable = false,
+ .TextureBorderColorMode = DX10OGL,
 
 #if GEN_GEN >= 8
-  .LODPreClampMode = CLAMP_MODE_OGL,
+ .LODPreClampMode = CLAMP_MODE_OGL,
 #else
-  .LODPreClampEnable = CLAMP_ENABLE_OGL,
+ .LODPreClampEnable = CLAMP_ENABLE_OGL,
 #endif
 
 #if GEN_GEN == 8
-  .BaseMipLevel = 0.0,
+ .BaseMipLevel = 0.0,
 #endif
-  .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
-  .MagModeFilter = vk_to_gen_tex_filter(pCreateInfo->magFilter,
-pCreateInfo->anisotropyEnable),
-  .MinModeFilter = vk_to_gen_tex_filter(pCreateInfo->minFilter,
-pCreateInfo->anisotropyEnable),
-  .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
-  .AnisotropicAlgorithm = EWAApproximation,
-  .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
-  .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
-  .ChromaKeyEnable = 0,
-  .ChromaKeyIndex = 0,
-  .ChromaKeyMode = 0,
-  .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp],
-  .CubeSurfaceControlMode = OVERRIDE,
-
-  .BorderColorPointer = border_color_offset,
+ .MipModeFilter = vk_to_gen_mipmap_mode[pCreateInfo->mipmapMode],
+ .MagModeFilter = vk_to_gen_tex_filter(pCreateInfo->magFilter,
+   pCreateInfo->anisotropyEnable),
+ .MinModeFilter = vk_to_gen_tex_filter(pCreateInfo->minFilter,
+   pCreateInfo->anisotropyEnable),
+ .TextureLODBias = anv_clamp_f(pCreateInfo->mipLodBias, -16, 15.996),
+ .AnisotropicAlgorithm = EWAApproximation,
+ .MinLOD = anv_clamp_f(pCreateInfo->minLod, 0, 14),
+ .MaxLOD = anv_clamp_f(pCreateInfo->maxLod, 0, 14),
+ .ChromaKeyEnable = 0,
+ .ChromaKeyIndex = 0,
+ .ChromaKeyMode = 0,
+ .ShadowFunction = vk_to_gen_shadow_compare_op[pCreateInfo->compareOp],
+ .CubeSurfaceControlMode = OVERRIDE,
+
+ .BorderColorPointer = border_color_offset,
 
 #if GEN_GEN >= 8
-  .LODClampMagnificationMode = MIPNONE,
+ .LODClampMagnificationMode = MIPNONE,
 #endif
 
-  .MaximumAnisotropy = 
vk_to_gen_max_anisotropy(pCreateInfo->maxAnisotropy),
-  .RAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
-  .RAddressMagFilterRoundingEnable = enable_mag_filter_addr_rounding,
-  .VAddressMinFilterRoundingEnable = enable_min_filter_addr_rounding,
-  

[Mesa-dev] [PATCH v2 09/11] anv: add nir lowering pass for ycrcb textures

[Lionel Landwerlin]

This pass implements all the implicit conversions required by the
VK_KHR_sampler_ycbcr_conversion specification.

It also inserts plane sources onto sampling instructions that we then
let the pipeline layout pass deal with, when mapping things correctly
to descriptors.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/Makefile.sources   |   1 +
 src/intel/vulkan/anv_nir.h   |   3 +
 src/intel/vulkan/anv_nir_apply_pipeline_layout.c |  62 ++-
 src/intel/vulkan/anv_nir_lower_ycbcr_textures.c  | 468 +++
 src/intel/vulkan/anv_pipeline.c  |   2 +
 src/intel/vulkan/anv_private.h   |  16 +-
 6 files changed, 545 insertions(+), 7 deletions(-)
 create mode 100644 src/intel/vulkan/anv_nir_lower_ycbcr_textures.c

diff --git a/src/intel/Makefile.sources b/src/intel/Makefile.sources
index bca7a132b26..9672dcc252d 100644
--- a/src/intel/Makefile.sources
+++ b/src/intel/Makefile.sources
@@ -219,6 +219,7 @@ VULKAN_FILES := \
vulkan/anv_nir_lower_input_attachments.c \
vulkan/anv_nir_lower_multiview.c \
vulkan/anv_nir_lower_push_constants.c \
+   vulkan/anv_nir_lower_ycbcr_textures.c \
vulkan/anv_pass.c \
vulkan/anv_pipeline.c \
vulkan/anv_pipeline_cache.c \
diff --git a/src/intel/vulkan/anv_nir.h b/src/intel/vulkan/anv_nir.h
index 5b450b45cdf..0a06e3a1cf0 100644
--- a/src/intel/vulkan/anv_nir.h
+++ b/src/intel/vulkan/anv_nir.h
@@ -37,6 +37,9 @@ void anv_nir_lower_push_constants(nir_shader *shader);
 
 bool anv_nir_lower_multiview(nir_shader *shader, uint32_t view_mask);
 
+void anv_nir_lower_ycbcr_textures(nir_shader *shader,
+  struct anv_pipeline *pipeline);
+
 void anv_nir_apply_pipeline_layout(struct anv_pipeline *pipeline,
nir_shader *shader,
struct brw_stage_prog_data *prog_data,
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c 
b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 428cfdf42d1..7cd28debe09 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -131,7 +131,7 @@ lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
 static void
 lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
 unsigned *const_index, unsigned hw_binding_size,
-nir_tex_src_type src_type,
+nir_tex_src_type src_type, bool allow_indirect,
 struct apply_pipeline_layout_state *state)
 {
nir_builder *b = >builder;
@@ -141,6 +141,15 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
   nir_deref_array *deref_array = nir_deref_as_array(deref->deref.child);
 
   if (deref_array->deref_array_type == nir_deref_array_type_indirect) {
+ /* From VK_KHR_sampler_ycbcr_conversion:
+  *
+  * If sampler Y’CBCR conversion is enabled, the combined image
+  * sampler must be indexed only by constant integral expressions when
+  * aggregated into arrays in shader code, irrespective of the
+  * shaderSampledImageArrayDynamicIndexing feature.
+  */
+ assert(allow_indirect);
+
  nir_ssa_def *index =
 nir_iadd(b, nir_imm_int(b, deref_array->base_offset),
 nir_ssa_for_src(b, deref_array->indirect, 1));
@@ -150,7 +159,6 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
 
  nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
tex->num_srcs + 1);
-
  for (unsigned i = 0; i < tex->num_srcs; i++) {
 new_srcs[i].src_type = tex->src[i].src_type;
 nir_instr_move_src(>instr, _srcs[i].src, 
>src[i].src);
@@ -186,6 +194,46 @@ cleanup_tex_deref(nir_tex_instr *tex, nir_deref_var *deref)
nir_instr_rewrite_src(>instr, _array->indirect, NIR_SRC_INIT);
 }
 
+static bool
+has_tex_src_plane(nir_tex_instr *tex)
+{
+   for (unsigned i = 0; i < tex->num_srcs; i++) {
+  if (tex->src[i].src_type == nir_tex_src_plane)
+ return true;
+   }
+
+   return false;
+}
+
+static uint32_t
+extract_tex_src_plane(nir_tex_instr *tex)
+{
+   nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src, tex->num_srcs - 1);
+   unsigned plane = 0;
+
+   for (unsigned i = 0, w = 0; i < tex->num_srcs; i++) {
+  if (tex->src[i].src_type == nir_tex_src_plane) {
+ nir_const_value *const_plane =
+nir_src_as_const_value(tex->src[i].src);
+
+ /* Our color conversion lowering pass should only ever insert
+  * constants. */
+ assert(const_plane);
+ plane = const_plane->u32[0];
+  } else {
+ new_srcs[w].src_type = tex->src[i].src_type;
+ nir_instr_move_src(>instr, _srcs[w].src, >src[i].src);
+ w++;
+  }
+   }
+
+   ralloc_free(tex->src);
+   tex->src = new_srcs;
+  

Re: [Mesa-dev] [PATCH 2/2] egl/surfaceless: Use KMS swrast fallback

[Gurchetan Singh]

Hi Eric,

Yes, you pushing this series would be great. I did run our test suite on
this patchset as well.

Best wishes,
Gurchetan

On Tue, Oct 3, 2017 at 7:02 AM, Eric Engestrom 
wrote:

> On Monday, 2017-10-02 20:48:24 +, gurchetansi...@chromium.org wrote:
> > From: Gurchetan Singh 
> >
> > The kms_swrast extension is an actively developed software fallback,
> > and platform_surfaceless can use it if there are no available
> > hardware drivers.
> >
> > v2: Split into 2 patches, use booleans, check LIBGL_ALWAYS_SOFTWARE,
> > and modify the eglLog level (Emil, Eric, Tomasz).
>
> Thanks, this is perfect :)
>
> Reviewed-by: Eric Engestrom 
>
> Do you want me to push this for you?
>
> It might be worth running deqp and other test suites to make sure
> everything is wired up correctly.
> (Given your chromium affiliation, I'm assuming you already know how to
> use the surfaceless patches for deqp [1])
>
> [1] https://chromium.googlesource.com/chromiumos/overlays/
> chromiumos-overlay/+/master/media-gfx/deqp
>
> > ---
> >  src/egl/drivers/dri2/platform_surfaceless.c | 19 +++
> >  1 file changed, 15 insertions(+), 4 deletions(-)
> >
> > diff --git a/src/egl/drivers/dri2/platform_surfaceless.c
> b/src/egl/drivers/dri2/platform_surfaceless.c
> > index f6aa217d39..b0a43ac9de 100644
> > --- a/src/egl/drivers/dri2/platform_surfaceless.c
> > +++ b/src/egl/drivers/dri2/platform_surfaceless.c
> [snip]
> > @@ -320,7 +324,14 @@ dri2_initialize_surfaceless(_EGLDriver *drv,
> _EGLDisplay *disp)
> >
> > dri2_dpy->fd = -1;
> > disp->DriverData = (void *) dri2_dpy;
>
> Nit: newline here
> (I'll add it if/when I commit it, don't send a v3 for that)
>
> > -   if (!surfaceless_probe_device(disp)) {
> > +   if (!env_var_as_boolean("LIBGL_ALWAYS_SOFTWARE", false)) {
> > +  driver_loaded = surfaceless_probe_device(disp, false);
> > +  if (!driver_loaded)
> > + _eglLog(_EGL_WARNING, "No hardware driver found, falling back
> to "
> > +  "software rendering");
> > +   }
> > +
> > +   if (!driver_loaded && !surfaceless_probe_device(disp, true)) {
> >err = "DRI2: failed to load driver";
> >goto cleanup;
> > }
> > --
> > 2.13.5
> >
>
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[Mesa-dev] [PATCH v2 06/11] anv: add new formats KHR_sampler_ycbcr_conversion

[Lionel Landwerlin]

Adding new downsampling factors for each planes.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_formats.c| 158 --
 src/intel/vulkan/anv_private.h|  10 +++
 src/intel/vulkan/vk_format_info.h |  27 +++
 3 files changed, 189 insertions(+), 6 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 8dd87133c0c..303531a6ab9 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -22,6 +22,7 @@
  */
 
 #include "anv_private.h"
+#include "vk_enum_to_str.h"
 #include "vk_format_info.h"
 #include "vk_util.h"
 
@@ -44,14 +45,12 @@
 #define BGRA _ISL_SWIZZLE(BLUE, GREEN, RED, ALPHA)
 #define RGB1 _ISL_SWIZZLE(RED, GREEN, BLUE, ONE)
 
-#define _fmt(__hw_fmt, __swizzle) \
-   { .isl_format = __hw_fmt, \
- .swizzle = __swizzle }
-
 #define swiz_fmt1(__vk_fmt, __hw_fmt, __swizzle) \
[vk_enum_offset(__vk_fmt)] = { \
   .planes = { \
-  { .isl_format = __hw_fmt, .swizzle = __swizzle }, \
+ { .isl_format = __hw_fmt, .swizzle = __swizzle, \
+   .denominator_scales = { 1, 1, }, \
+ }, \
   }, \
   .n_planes = 1, \
}
@@ -64,14 +63,41 @@
   .planes = { \
  { .isl_format = __depth_fmt, \
.swizzle = RGBA,   \
+   .denominator_scales = { 1, 1, }, \
  }, \
  { .isl_format = __stencil_fmt, \
.swizzle = RGBA,   \
+   .denominator_scales = { 1, 1, }, \
  }, \
   }, \
   .n_planes = 2, \
}
 
+#define y_plane(__hw_fmt, __swizzle, __ycbcr_swizzle, dhs, dvs) \
+   { .isl_format = __hw_fmt, \
+ .swizzle = __swizzle, \
+ .ycbcr_swizzle = __ycbcr_swizzle, \
+ .denominator_scales = { dhs, dvs, }, \
+ .has_chroma = false, \
+   }
+
+#define chroma_plane(__hw_fmt, __swizzle, __ycbcr_swizzle, dhs, dvs) \
+   { .isl_format = __hw_fmt, \
+ .swizzle = __swizzle, \
+ .ycbcr_swizzle = __ycbcr_swizzle, \
+ .denominator_scales = { dhs, dvs, }, \
+ .has_chroma = true, \
+   }
+
+#define ycbcr_fmt(__vk_fmt, __n_planes, ...) \
+   [vk_enum_offset(__vk_fmt)] = { \
+  .planes = { \
+ __VA_ARGS__, \
+  }, \
+  .n_planes = __n_planes, \
+  .can_ycbcr = true, \
+   }
+
 /* HINT: For array formats, the ISL name should match the VK name.  For
  * packed formats, they should have the channels in reverse order from each
  * other.  The reason for this is that, for packed formats, the ISL (and
@@ -268,6 +294,76 @@ static const struct anv_format main_formats[] = {
fmt1(VK_FORMAT_B8G8R8A8_SRGB,   ISL_FORMAT_B8G8R8A8_UNORM_SRGB),
 };
 
+static const struct anv_format ycbcr_formats[] = {
+   ycbcr_fmt(VK_FORMAT_G8B8G8R8_422_UNORM_KHR, 1,
+ y_plane(ISL_FORMAT_YCRCB_SWAPUV, RGBA, _ISL_SWIZZLE(BLUE, GREEN, 
RED, ZERO), 1, 1)),
+   ycbcr_fmt(VK_FORMAT_B8G8R8G8_422_UNORM_KHR, 1,
+ y_plane(ISL_FORMAT_YCRCB_SWAPUVY, RGBA, _ISL_SWIZZLE(BLUE, GREEN, 
RED, ZERO), 1, 1)),
+   ycbcr_fmt(VK_FORMAT_G8_B8_R8_3PLANE_420_UNORM_KHR, 3,
+ y_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, 
ZERO, ZERO), 1, 1),
+ chroma_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, ZERO, 
ZERO, ZERO), 2, 2),
+ chroma_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(RED, ZERO, 
ZERO, ZERO), 2, 2)),
+   ycbcr_fmt(VK_FORMAT_G8_B8R8_2PLANE_420_UNORM_KHR, 2,
+ y_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, 
ZERO, ZERO), 1, 1),
+ chroma_plane(ISL_FORMAT_R8G8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, RED, 
ZERO, ZERO), 2, 2)),
+   ycbcr_fmt(VK_FORMAT_G8_B8_R8_3PLANE_422_UNORM_KHR, 3,
+ y_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, 
ZERO, ZERO), 1, 1),
+ chroma_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, ZERO, 
ZERO, ZERO), 2, 1),
+ chroma_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(RED, ZERO, 
ZERO, ZERO), 2, 1)),
+   ycbcr_fmt(VK_FORMAT_G8_B8R8_2PLANE_422_UNORM_KHR, 2,
+ y_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, 
ZERO, ZERO), 1, 1),
+ chroma_plane(ISL_FORMAT_R8G8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, RED, 
ZERO, ZERO), 2, 1)),
+   ycbcr_fmt(VK_FORMAT_G8_B8_R8_3PLANE_444_UNORM_KHR, 3,
+ y_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(GREEN, ZERO, 
ZERO, ZERO), 1, 1),
+ chroma_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(BLUE, ZERO, 
ZERO, ZERO), 1, 1),
+ chroma_plane(ISL_FORMAT_R8_UNORM, RGBA, _ISL_SWIZZLE(RED, ZERO, 
ZERO, ZERO), 1, 1)),
+
+   fmt1(VK_FORMAT_R10X6_UNORM_PACK16_KHR, ISL_FORMAT_UNSUPPORTED),
+   fmt1(VK_FORMAT_R10X6G10X6_UNORM_2PACK16_KHR, ISL_FORMAT_UNSUPPORTED),
+   fmt1(VK_FORMAT_R10X6G10X6B10X6A10X6_UNORM_4PACK16_KHR, 
ISL_FORMAT_UNSUPPORTED),
+   fmt1(VK_FORMAT_G10X6B10X6G10X6R10X6_422_UNORM_4PACK16_KHR, 
ISL_FORMAT_UNSUPPORTED),
+   

[Mesa-dev] [PATCH v2 07/11] anv: add descriptor support for multiplanar image/sampler

[Lionel Landwerlin]

v2: Drop a memset by using zalloc (Jason)
Decouple vulkan descriptors from the underlying binding table
(Jason)

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_descriptor_set.c| 24 -
 src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 66 ++--
 src/intel/vulkan/anv_private.h   | 22 
 src/intel/vulkan/genX_cmd_buffer.c   | 17 +++---
 src/intel/vulkan/genX_state.c|  2 +
 5 files changed, 97 insertions(+), 34 deletions(-)

diff --git a/src/intel/vulkan/anv_descriptor_set.c 
b/src/intel/vulkan/anv_descriptor_set.c
index 84077982307..704693e227f 100644
--- a/src/intel/vulkan/anv_descriptor_set.c
+++ b/src/intel/vulkan/anv_descriptor_set.c
@@ -35,6 +35,21 @@
  * Descriptor set layouts.
  */
 
+static uint32_t
+layout_binding_get_hw_binding_size(const VkDescriptorSetLayoutBinding *binding)
+{
+   if (binding->pImmutableSamplers == NULL)
+  return binding->descriptorCount;
+
+   uint32_t immutable_sampler_count = 0;
+   for (uint32_t i = 0; i < binding->descriptorCount; i++) {
+  ANV_FROM_HANDLE(anv_sampler, sampler, binding->pImmutableSamplers[i]);
+  immutable_sampler_count += sampler->n_planes;
+   }
+
+   return immutable_sampler_count;
+}
+
 VkResult anv_CreateDescriptorSetLayout(
 VkDevice_device,
 const VkDescriptorSetLayoutCreateInfo*  pCreateInfo,
@@ -75,6 +90,7 @@ VkResult anv_CreateDescriptorSetLayout(
 
   set_layout->binding[b].array_size = 0;
   set_layout->binding[b].immutable_samplers = NULL;
+  set_layout->binding[b].hw_binding_size = 0;
}
 
/* Initialize all samplers to 0 */
@@ -108,8 +124,13 @@ VkResult anv_CreateDescriptorSetLayout(
   set_layout->binding[b].type = binding->descriptorType;
 #endif
   set_layout->binding[b].array_size = binding->descriptorCount;
+  set_layout->binding[b].hw_binding_size =
+ layout_binding_get_hw_binding_size(binding);
   set_layout->binding[b].descriptor_index = set_layout->size;
+  set_layout->binding[b].hw_binding_index = set_layout->hw_size;
+
   set_layout->size += binding->descriptorCount;
+  set_layout->hw_size += set_layout->binding[b].hw_binding_size;
 
   switch (binding->descriptorType) {
   case VK_DESCRIPTOR_TYPE_SAMPLER:
@@ -323,6 +344,8 @@ VkResult anv_CreateDescriptorPool(
   case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC:
   case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC:
  buffer_count += pCreateInfo->pPoolSizes[i].descriptorCount;
+ /* Fallthrough */
+
   default:
  descriptor_count += pCreateInfo->pPoolSizes[i].descriptorCount;
  break;
@@ -612,7 +635,6 @@ anv_descriptor_set_write_image_view(struct 
anv_descriptor_set *set,
sampler = bind_layout->immutable_samplers ?
  bind_layout->immutable_samplers[element] :
  sampler;
-
*desc = (struct anv_descriptor) {
   .type = type,
   .layout = info->imageLayout,
diff --git a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c 
b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
index 67bcf5e29ef..428cfdf42d1 100644
--- a/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
+++ b/src/intel/vulkan/anv_nir_apply_pipeline_layout.c
@@ -130,7 +130,7 @@ lower_res_index_intrinsic(nir_intrinsic_instr *intrin,
 
 static void
 lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
-unsigned *const_index, unsigned array_size,
+unsigned *const_index, unsigned hw_binding_size,
 nir_tex_src_type src_type,
 struct apply_pipeline_layout_state *state)
 {
@@ -146,7 +146,7 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
 nir_ssa_for_src(b, deref_array->indirect, 1));
 
  if (state->add_bounds_checks)
-index = nir_umin(b, index, nir_imm_int(b, array_size - 1));
+index = nir_umin(b, index, nir_imm_int(b, hw_binding_size - 1));
 
  nir_tex_src *new_srcs = rzalloc_array(tex, nir_tex_src,
tex->num_srcs + 1);
@@ -167,7 +167,7 @@ lower_tex_deref(nir_tex_instr *tex, nir_deref_var *deref,
nir_src_for_ssa(index));
  tex->num_srcs++;
   } else {
- *const_index += MIN2(deref_array->base_offset, array_size - 1);
+ *const_index += MIN2(deref_array->base_offset, hw_binding_size - 1);
   }
}
 }
@@ -196,19 +196,18 @@ lower_tex(nir_tex_instr *tex, struct 
apply_pipeline_layout_state *state)
 
unsigned set = tex->texture->var->data.descriptor_set;
unsigned binding = tex->texture->var->data.binding;
-   unsigned array_size =
-  state->layout->set[set].layout->binding[binding].array_size;
+   unsigned hw_binding_size =
+  state->layout->set[set].layout->binding[binding].hw_binding_size;
tex->texture_index = 

[Mesa-dev] [PATCH v2 01/11] vulkan: util: add macros to extract extension/offset number from enums

[Lionel Landwerlin]

v2: Simplify offset enum computation (Jason)

Signed-off-by: Lionel Landwerlin 
---
 src/vulkan/util/vk_util.h | 6 ++
 1 file changed, 6 insertions(+)

diff --git a/src/vulkan/util/vk_util.h b/src/vulkan/util/vk_util.h
index 2ed601f881e..8c8cb64d513 100644
--- a/src/vulkan/util/vk_util.h
+++ b/src/vulkan/util/vk_util.h
@@ -199,4 +199,10 @@ __vk_find_struct(void *start, VkStructureType sType)
 
 uint32_t vk_get_driver_version(void);
 
+#define VK_EXT_OFFSET (10UL)
+#define vk_enum_extension(__enum) \
+   ((__enum) >= VK_EXT_OFFSET ? __enum) - VK_EXT_OFFSET) / 1000UL) + 1) : 
0)
+#define vk_enum_offset(__enum) \
+   ((__enum) >= VK_EXT_OFFSET ? ((__enum) % 1000) : (__enum))
+
 #endif /* VK_UTIL_H */
-- 
2.14.2

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[Mesa-dev] [PATCH v2 04/11] anv: prepare formats to handle disjoints sets

[Lionel Landwerlin]

Newer format enums start at offset 10, making it impossible to
have them all in one table. This change splits the formats into sets
that we then access through indirection.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/vulkan/anv_formats.c | 35 ++-
 1 file changed, 26 insertions(+), 9 deletions(-)

diff --git a/src/intel/vulkan/anv_formats.c b/src/intel/vulkan/anv_formats.c
index 049ffe17ac0..71824256b25 100644
--- a/src/intel/vulkan/anv_formats.c
+++ b/src/intel/vulkan/anv_formats.c
@@ -58,7 +58,7 @@
  * other.  The reason for this is that, for packed formats, the ISL (and
  * bspec) names are in LSB -> MSB order while VK formats are MSB -> LSB.
  */
-static const struct anv_format anv_formats[] = {
+static const struct anv_format main_formats[] = {
fmt(VK_FORMAT_UNDEFINED,   ISL_FORMAT_UNSUPPORTED),
fmt(VK_FORMAT_R4G4_UNORM_PACK8,ISL_FORMAT_UNSUPPORTED),
fmt(VK_FORMAT_R4G4B4A4_UNORM_PACK16,   ISL_FORMAT_A4B4G4R4_UNORM),
@@ -251,13 +251,30 @@ static const struct anv_format anv_formats[] = {
 
 #undef fmt
 
+static const struct {
+   const struct anv_format *formats;
+   uint32_t n_formats;
+} anv_formats[] = {
+   [0] = { .formats = main_formats, .n_formats = ARRAY_SIZE(main_formats), },
+};
+
+static struct anv_format
+format_extract(VkFormat vk_format)
+{
+   uint32_t enum_offset = vk_enum_offset(vk_format);
+   uint32_t ext_number = vk_enum_extension(vk_format);
+
+   if (ext_number >= ARRAY_SIZE(anv_formats) ||
+   enum_offset >= anv_formats[ext_number].n_formats)
+  return (struct anv_format) { .isl_format = ISL_FORMAT_UNSUPPORTED };
+
+   return anv_formats[ext_number].formats[enum_offset];
+}
+
 static bool
 format_supported(VkFormat vk_format)
 {
-   if (vk_format >= ARRAY_SIZE(anv_formats))
-  return false;
-
-   return anv_formats[vk_format].isl_format != ISL_FORMAT_UNSUPPORTED;
+   return format_extract(vk_format).isl_format != ISL_FORMAT_UNSUPPORTED;
 }
 
 /**
@@ -267,10 +284,10 @@ struct anv_format
 anv_get_format(const struct gen_device_info *devinfo, VkFormat vk_format,
VkImageAspectFlags aspect, VkImageTiling tiling)
 {
-   if (!format_supported(vk_format))
-  return anv_formats[VK_FORMAT_UNDEFINED];
+   struct anv_format format = format_extract(vk_format);
 
-   struct anv_format format = anv_formats[vk_format];
+   if (format.isl_format == ISL_FORMAT_UNSUPPORTED)
+  return format;
 
if (aspect == VK_IMAGE_ASPECT_STENCIL_BIT) {
   assert(vk_format_aspects(vk_format) & VK_IMAGE_ASPECT_STENCIL_BIT);
@@ -553,7 +570,7 @@ anv_get_image_format_properties(
 ** This field cannot be ASTC format if the Surface Type is SURFTYPE_1D.
 */
if (info->type == VK_IMAGE_TYPE_1D &&
-   isl_format_is_compressed(anv_formats[info->format].isl_format)) {
+   isl_format_is_compressed(format_extract(info->format).isl_format)) {
goto unsupported;
}
 
-- 
2.14.2

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[Mesa-dev] [PATCH v2 02/11] isl: make format layout channels accessible by index

[Lionel Landwerlin]

Signed-off-by: Lionel Landwerlin 
---
 src/intel/isl/isl.h | 21 -
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/src/intel/isl/isl.h b/src/intel/isl/isl.h
index df275f85c49..98de4c0f57f 100644
--- a/src/intel/isl/isl.h
+++ b/src/intel/isl/isl.h
@@ -994,15 +994,18 @@ struct isl_format_layout {
uint8_t bh; /**< Block height, in pixels */
uint8_t bd; /**< Block depth, in pixels */
 
-   struct {
-  struct isl_channel_layout r; /**< Red channel */
-  struct isl_channel_layout g; /**< Green channel */
-  struct isl_channel_layout b; /**< Blue channel */
-  struct isl_channel_layout a; /**< Alpha channel */
-  struct isl_channel_layout l; /**< Luminance channel */
-  struct isl_channel_layout i; /**< Intensity channel */
-  struct isl_channel_layout p; /**< Palette channel */
-   } channels;
+   union {
+  struct {
+ struct isl_channel_layout r; /**< Red channel */
+ struct isl_channel_layout g; /**< Green channel */
+ struct isl_channel_layout b; /**< Blue channel */
+ struct isl_channel_layout a; /**< Alpha channel */
+ struct isl_channel_layout l; /**< Luminance channel */
+ struct isl_channel_layout i; /**< Intensity channel */
+ struct isl_channel_layout p; /**< Palette channel */
+  } channels;
+  struct isl_channel_layout channels_array[7];
+   };
 
enum isl_colorspace colorspace;
enum isl_txc txc;
-- 
2.14.2

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[Mesa-dev] [PATCH v2 03/11] isl: fill out layout descriptions for yuv formats

[Lionel Landwerlin]

Some description was missing.

Signed-off-by: Lionel Landwerlin 
---
 src/intel/isl/isl_format_layout.csv | 8 
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/intel/isl/isl_format_layout.csv 
b/src/intel/isl/isl_format_layout.csv
index f340e30a1bf..ebb3d22bc18 100644
--- a/src/intel/isl/isl_format_layout.csv
+++ b/src/intel/isl/isl_format_layout.csv
@@ -222,8 +222,8 @@ I8_UINT ,   8,  1,  1,  1, , ,  
   , , ,  ui
 I8_SINT ,   8,  1,  1,  1, , , , , ,  
si8,, linear,
 DXT1_RGB_SRGB   ,  64,  4,  4,  1,  un4,  un4,  un4, , ,   
  ,,   srgb,  dxt1
 R1_UNORM,   1,  1,  1,  1,  un1, , , , ,   
  ,, linear,
-YCRCB_NORMAL,   0,  0,  0,  0, , , , , ,   
  ,,yuv,
-YCRCB_SWAPUVY   ,   0,  0,  0,  0, , , , , ,   
  ,,yuv,
+YCRCB_NORMAL,  16,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,,yuv,
+YCRCB_SWAPUVY   ,  16,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,,yuv,
 P2_UNORM_PALETTE0   ,   2,  1,  1,  1, , , , , ,   
  , un2, linear,
 P2_UNORM_PALETTE1   ,   2,  1,  1,  1, , , , , ,   
  , un2, linear,
 BC1_UNORM   ,  64,  4,  4,  1,  un4,  un4,  un4,  un4, ,   
  ,, linear,  dxt1
@@ -235,8 +235,8 @@ BC1_UNORM_SRGB  ,  64,  4,  4,  1,  un4,  un4,  
un4,  un4, ,
 BC2_UNORM_SRGB  , 128,  4,  4,  1,  un4,  un4,  un4,  un4, ,   
  ,,   srgb,  dxt3
 BC3_UNORM_SRGB  , 128,  4,  4,  1,  un4,  un4,  un4,  un4, ,   
  ,,   srgb,  dxt5
 MONO8   ,   1,  1,  1,  1, , , , , ,   
  ,,   ,
-YCRCB_SWAPUV,   0,  0,  0,  0, , , , , ,   
  ,,yuv,
-YCRCB_SWAPY ,   0,  0,  0,  0, , , , , ,   
  ,,yuv,
+YCRCB_SWAPUV,  16,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,,yuv,
+YCRCB_SWAPY ,  16,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,,yuv,
 DXT1_RGB,  64,  4,  4,  1,  un4,  un4,  un4, , ,   
  ,, linear,  dxt1
 FXT1, 128,  8,  4,  1,  un4,  un4,  un4, , ,   
  ,, linear,  fxt1
 R8G8B8_UNORM,  24,  1,  1,  1,  un8,  un8,  un8, , ,   
  ,, linear,
-- 
2.14.2

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[Mesa-dev] [PATCH v2 00/11] anv: implement KHR_sampler_ycbcr_conversion

[Lionel Landwerlin]

Hi all,

Here is a v2 of KHR_sampler_ycbcr_conversion. The major change is the
decoupling of descriptors from the binding table elements (patch 7).

This is available on the following branch :

   https://github.com/djdeath/mesa/tree/wip/djdeath/ycbcr_conversion

Cheers,

Lionel Landwerlin (11):
  vulkan: util: add macros to extract extension/offset number from enums
  isl: make format layout channels accessible by index
  isl: fill out layout descriptions for yuv formats
  anv: prepare formats to handle disjoints sets
  anv: modify the internal concept of format to express multiple planes
  anv: add new formats KHR_sampler_ycbcr_conversion
  anv: add descriptor support for multiplanar image/sampler
  anv: prepare sampler emission code for multiplanar images
  anv: add nir lowering pass for ycrcb textures
  anv: enable multiple planes per image/imageView
  anv: enable VK_KHR_sampler_ycbcr_conversion

 src/intel/Makefile.sources   |   1 +
 src/intel/isl/isl.h  |  21 +-
 src/intel/isl/isl_format_layout.csv  |   8 +-
 src/intel/vulkan/anv_blorp.c | 333 +++
 src/intel/vulkan/anv_descriptor_set.c|  24 +-
 src/intel/vulkan/anv_device.c|  69 ++-
 src/intel/vulkan/anv_dump.c  |  17 +-
 src/intel/vulkan/anv_extensions.py   |   1 +
 src/intel/vulkan/anv_formats.c   | 724 +++
 src/intel/vulkan/anv_image.c | 659 +
 src/intel/vulkan/anv_intel.c |   4 +-
 src/intel/vulkan/anv_nir.h   |   3 +
 src/intel/vulkan/anv_nir_apply_pipeline_layout.c | 128 +++-
 src/intel/vulkan/anv_nir_lower_ycbcr_textures.c  | 468 +++
 src/intel/vulkan/anv_pipeline.c  |   2 +
 src/intel/vulkan/anv_private.h   | 348 ---
 src/intel/vulkan/anv_wsi.c   |   8 +-
 src/intel/vulkan/gen8_cmd_buffer.c   |   2 +-
 src/intel/vulkan/genX_cmd_buffer.c   | 331 +++
 src/intel/vulkan/genX_pipeline.c |  14 +-
 src/intel/vulkan/genX_state.c| 122 ++--
 src/intel/vulkan/vk_format_info.h|  27 +
 src/vulkan/util/vk_util.h|   6 +
 23 files changed, 2406 insertions(+), 914 deletions(-)
 create mode 100644 src/intel/vulkan/anv_nir_lower_ycbcr_textures.c

--
2.14.2
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Re: [Mesa-dev] [PATCH v2 3/7] travis: Add clover build using llvm-3.7

[Jan Vesely]

On Tue, 2017-10-03 at 17:26 +0100, Eric Engestrom wrote:
> On Friday, 2017-09-29 16:32:36 +, Jan Vesely wrote:
> > On Mon, 2017-09-18 at 16:46 +0100, Eric Engestrom wrote:
> > > On Monday, 2017-09-18 11:10:37 -0400, Jan Vesely wrote:
> > > > On Mon, 2017-09-18 at 11:13 +0100, Eric Engestrom wrote:
> > > > > On Sunday, 2017-09-17 02:02:33 -0400, Jan Vesely wrote:
> > > > > > v2: Use direct llvm repo link instead of alias
> > > > > > Enable
> > > > > > 
> > > > > > Signed-off-by: Jan Vesely 
> > > > > > ---
> > > > > >  .travis.yml | 40 
> > > > > >  1 file changed, 40 insertions(+)
> > > > > > 
> > > > > > diff --git a/.travis.yml b/.travis.yml
> > > > > > index 0012d27dc7..638ec2a78a 100644
> > > > > > --- a/.travis.yml
> > > > > > +++ b/.travis.yml
> > > > > > @@ -152,6 +152,46 @@ matrix:
> > > > > >  - libelf-dev
> > > > > >  - libunwind8-dev
> > > > > >  - env:
> > > > > > +# Disable for now since travis does not allow 
> > > > > > llvm-toolchain-trusty-3.7
> > > > > 
> > > > > You can drop this line now :)
> > > > 
> > > > Fixed locally.
> > > > 
> > > > > 
> > > > > Don't 4.0 and 5.0 need the same binutils-2.26 as 3.9?
> > > 
> > > You didn't answer this; isn't it needed?
> > > 
> > > > > Speaking of, I think the OVERRIDE_PATH you added is the only way to 
> > > > > do this.
> > > > > 
> > > > > With the above fixed or justified, the series is:
> > > > > Reviewed-by: Eric Engestrom 
> > > > 
> > > > thanks.
> > > > 
> > > > > 
> > > > > One thing before anyone pushes this however: this will make the builds
> > > > > much longer; is the gain of testing every supported llvm version 
> > > > > worth it?
> > > > 
> > > > It does not really make builds that much worse after the ccache has
> > > > warmed up:
> > > > https://travis-ci.org/jvesely/mesa/builds/276686220
> > > > building SWR is the elephant and it leaves time to build these in
> > > > parallel.
> > > 
> > > Looking at the numbers, I'm convinced :)
> > > Do you have push access, or do you want me to push the series for you?
> > > 
> > > (Note: typo in the subject of patch 6/7)
> > 
> > sorry, I missed this part the first time.
> > I've fixed the typo in patch 6 and pushed patches 5/6/7 per discussion
> > with Emil.
> 
> Don't we want to drop the 3.6 build then?

I've left it for Emil to remove in the same patch(or series) that drops
clover llvm<3.9 support. seemed like a good idea to keep around until
then.

Jan

> 
> > 
> > regards,
> > Jan
> > 

-- 
Jan Vesely 

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Re: [Mesa-dev] Fwd: errors for mesa master Android build 862

[Marek Olšák]

On Mon, Oct 2, 2017 at 12:05 AM, Rob Herring  wrote:
> FYI, 2 Android build errors on i965 and r600 started in the last week.
> I've been traveling and haven't investigated.

r600 doesn't use gallium/drivers/radeon anymore.

Marek
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Re: [Mesa-dev] [PATCH v2 3/7] travis: Add clover build using llvm-3.7

[Eric Engestrom]

On Friday, 2017-09-29 16:32:36 +, Jan Vesely wrote:
> On Mon, 2017-09-18 at 16:46 +0100, Eric Engestrom wrote:
> > On Monday, 2017-09-18 11:10:37 -0400, Jan Vesely wrote:
> > > On Mon, 2017-09-18 at 11:13 +0100, Eric Engestrom wrote:
> > > > On Sunday, 2017-09-17 02:02:33 -0400, Jan Vesely wrote:
> > > > > v2: Use direct llvm repo link instead of alias
> > > > > Enable
> > > > > 
> > > > > Signed-off-by: Jan Vesely 
> > > > > ---
> > > > >  .travis.yml | 40 
> > > > >  1 file changed, 40 insertions(+)
> > > > > 
> > > > > diff --git a/.travis.yml b/.travis.yml
> > > > > index 0012d27dc7..638ec2a78a 100644
> > > > > --- a/.travis.yml
> > > > > +++ b/.travis.yml
> > > > > @@ -152,6 +152,46 @@ matrix:
> > > > >  - libelf-dev
> > > > >  - libunwind8-dev
> > > > >  - env:
> > > > > +# Disable for now since travis does not allow 
> > > > > llvm-toolchain-trusty-3.7
> > > > 
> > > > You can drop this line now :)
> > > 
> > > Fixed locally.
> > > 
> > > > 
> > > > Don't 4.0 and 5.0 need the same binutils-2.26 as 3.9?
> > 
> > You didn't answer this; isn't it needed?
> > 
> > > > Speaking of, I think the OVERRIDE_PATH you added is the only way to do 
> > > > this.
> > > > 
> > > > With the above fixed or justified, the series is:
> > > > Reviewed-by: Eric Engestrom 
> > > 
> > > thanks.
> > > 
> > > > 
> > > > One thing before anyone pushes this however: this will make the builds
> > > > much longer; is the gain of testing every supported llvm version worth 
> > > > it?
> > > 
> > > It does not really make builds that much worse after the ccache has
> > > warmed up:
> > > https://travis-ci.org/jvesely/mesa/builds/276686220
> > > building SWR is the elephant and it leaves time to build these in
> > > parallel.
> > 
> > Looking at the numbers, I'm convinced :)
> > Do you have push access, or do you want me to push the series for you?
> > 
> > (Note: typo in the subject of patch 6/7)
> 
> sorry, I missed this part the first time.
> I've fixed the typo in patch 6 and pushed patches 5/6/7 per discussion
> with Emil.

Don't we want to drop the 3.6 build then?

> 
> regards,
> Jan
> 
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