From: Michel Dänzer michel.daen...@amd.com
This is certainly not the last word on scheduling for this target, but
right now this allows a few apps to run / finish with radeonsi, most
notably UT2004 / Lightsmark. They fail to compile some shaders with the
default scheduler because it ends up
be equivalent on little endian and big endian hosts at the
same time. As it works for you, it's apparently equivalent on little
endian.
I suspect ReadPixels could be made even faster with similar treatment as
Marek has applied to TexSubImage etc.
--
Earthling Michel Dänzer
From: Michel Dänzer michel.daen...@amd.com
In cases where the vertex element size is smaller than the vertex buffer
stride, the previous calculation could end up 1 too low. This would result
in the GPU using index 0 instead of the maximum index for those elements,
which would be visible
.
Reviewed-by: Alex Deucher alexander.deuc...@amd.com
Likewise,
Reviewed-by: Michel Dänzer michel.daen...@amd.com
@@ -139,6 +140,11 @@ void si_pm4_inval_texture_cache(struct si_pm4_state
*state)
state-cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
}
+void
it is better to remove this check.
If the read buffer is in VRAM, reading from it with the CPU directly
will be very slow.
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-buffer_size);
Why not use cb-buffer_size?
The rest of the radeonsi patches in this series looks good to me.
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output.
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From: Michel Dänzer michel.daen...@amd.com
Not sure it actually works though, some buffer callbacks seem to have rotted
before.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/state_trackers/egl/drm/native_drm.c | 8 +++-
src/gallium/state_trackers/egl/wayland
On Die, 2013-03-19 at 11:07 +0100, Michel Dänzer wrote:
From: Michel Dänzer michel.daen...@amd.com
Not sure it actually works though, some buffer callbacks seem to have rotted
before.
Also, more than 20 piglit tests are now failing with radeonsi (via
egl_dri2) with:
libEGL fatal: DRI2: did
From: Michel Dänzer michel.daen...@amd.com
Fixes random failures with piglit glsl-max-varyings.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c | 5 +
1 file changed, 5 insertions(+)
diff
.
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On Don, 2013-03-21 at 17:12 +0100, Christian König wrote:
Am 21.03.2013 15:06, schrieb Michel Dänzer:
When I tried this earlier, something broke. Unfortunately, I can't seem
to remember or dig up if it was a piglit test or e.g. one of the sampler
demos in mesa/demos/src/glsl/. Did you test
From: Michel Dänzer michel.daen...@amd.com
Fixes wrong lighting in some corner cases with r600g and radeonsi, e.g.
manifested by failure of two piglit/glean tests and intermittent black
patches in many apps.
Tested on SI and RS880.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=62012
From: Michel Dänzer michel.daen...@amd.com
This helps minimize confusion / effort when moving between branches or
helping others.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/r600/r600_pipe.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/src
.
*/
- if (cb == NULL)
+ if (cb == NULL || (!cb-buffer !cb-user_buffer))
return;
pm4 = CALLOC_STRUCT(si_pm4_state);
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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Libre software
On Fre, 2013-03-22 at 11:04 +0100, Christian König wrote:
Am 21.03.2013 17:17, schrieb Michel Dänzer:
On Don, 2013-03-21 at 17:12 +0100, Christian König wrote:
Am 21.03.2013 15:06, schrieb Michel Dänzer:
When I tried this earlier, something broke. Unfortunately, I can't seem
to remember
= V_009910_ARRAY_1D_TILED_THIN1;
}
r = r600_init_surface(rscreen, surface, templ, array_mode,
What's this hunk doing in here? :)
The rest looks good to me on a quick look.
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On Die, 2013-03-26 at 11:56 +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
The include isn't needed and the file has moved with LLVM master.
Signed-off-by: Christian König christian.koe...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com
The rest
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Patches 1-3 are
Reviewed-by: Michel Dänzer michel.daen...@amd.com
Tested-by: Michel Dänzer michel.daen...@amd.com
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On Mit, 2013-03-27 at 12:02 +0100, Christian König wrote:
Am 26.03.2013 18:03, schrieb Michel Dänzer:
On Die, 2013-03-26 at 17:37 +0100, Christian König wrote:
Am 26.03.2013 15:56, schrieb Michel Dänzer:
On Die, 2013-03-26 at 14:51 +0100, Christian König wrote:
From: Christian König
From: Michel Dänzer michel.daen...@amd.com
Fixes mplayer -vo vdpau OSD.
Reported-by: Igor Vagulin igor.vagu...@gmail.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/r600_blit.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/gallium/drivers
changed to a shared object to work around
linker error in egl_static.so, but these appear to be fixed now.
https://bugs.freedesktop.org/show_bug.cgi?id=62226
---
Please test to make sure this works for your build configuration.
Tested-by: Michel Dänzer michel.daen...@amd.com
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On Mit, 2013-03-27 at 16:35 +0100, Christian König wrote:
From: Christian König christian.koe...@amd.com
v2: reduce key size, don't copy key around to much.
v3: remove key size reduction
Signed-off-by: Christian König christian.koe...@amd.com
Reviewed-by: Michel Dänzer michel.daen
On Die, 2013-04-02 at 10:20 +0200, Michel Dänzer wrote:
On Mon, 2013-04-01 at 14:11 -0700, Tom Stellard wrote:
From: Tom Stellard thomas.stell...@amd.com
Building libradeonllvm as a shared object has led to a number of bugs
and build system complications, and I don't think it's
building with
--enable-texture-float?
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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this would need to be reported to the X.org xserver project.
Do you really need to build Mesa with --enable-xorg though?
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for component 0/'x' and one for component 3/'w'
of a four component vector. Is this handled correctly?
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On Mit, 2013-04-03 at 15:38 +0200, Christian König wrote:
Am 03.04.2013 15:19, schrieb Michel Dänzer:
On Mit, 2013-03-27 at 17:57 +0100, Christian König wrote:
the attached patches dynamically adjust the writemask of MIMG
instructions depending on the used components. Additional
;
view-state[7] = 0;
-
return view-base;
}
Please drop the whitespace-only hunks.
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to change depending how the DRM minor bumps pan out
between UVD and SI 2D tiling support. Other than that,
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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On Mit, 2013-04-03 at 11:04 -0700, Matt Turner wrote:
On Wed, Apr 3, 2013 at 5:25 AM, Michel Dänzer mic...@daenzer.net wrote:
On Mit, 2013-04-03 at 14:40 +0400, Alexander Khryukin wrote:
Hi all!
i'm trying to build latest mesa release 9.1.1 on my arm board i.mx6
and i got
.c
;
makes clearer how many GPRs are allocated in the hardware.
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(depth - 1) | S_008F20_PITCH(pitch -
1));
Looks like this should be in patch 1 as well.
The actual compressed format related bits look good to me. :)
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Dänzer michel.daen...@amd.com
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From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/targets/opencl/Makefile.am | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/gallium/targets/opencl/Makefile.am
b/src/gallium/targets/opencl/Makefile.am
On Mit, 2013-04-10 at 10:26 +0200, Christian König wrote:
Am 03.04.2013 15:43, schrieb Michel Dänzer:
On Mit, 2013-04-03 at 15:38 +0200, Christian König wrote:
Am 03.04.2013 15:19, schrieb Michel Dänzer:
On Mit, 2013-03-27 at 17:57 +0100, Christian König wrote:
the attached patches
From: Michel Dänzer michel.daen...@amd.com
21 more little piglits with radeonsi.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
v2: Now with lit test.
lib/Target/R600/SIInstructions.td | 11 +--
test/CodeGen/R600/urecip.ll | 12
2 files changed, 21
On Mit, 2013-04-10 at 12:07 +0200, Christian König wrote:
Am 10.04.2013 11:46, schrieb Michel Dänzer:
From: Michel Dänzer michel.daen...@amd.com
21 more little piglits with radeonsi.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
You figured it out, great!
I figured out what
On Mit, 2013-04-10 at 12:59 +0200, Christian König wrote:
Am 10.04.2013 12:21, schrieb Michel Dänzer:
On Mit, 2013-04-10 at 12:07 +0200, Christian König wrote:
Am 10.04.2013 11:46, schrieb Michel Dänzer:
But why the heck is multiplying with 0x4f80 fixing the result?
I'm afraid I
From: Michel Dänzer michel.daen...@amd.com
21 more little piglits with radeonsi.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
v3: Use constant for and add comments about scaling multiplications
lib/Target/R600/AMDGPUInstructions.td | 1 +
lib/Target/R600/R600Instructions.td | 3
the register address and
the second dword contians the value to write.
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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Libre software enthusiast | Debian, X and DRI developer
-op_actions[TGSI_OPCODE_IF].emit = if_emit;
+ bld_base-op_actions[TGSI_OPCODE_IF].emit = uif_emit;
This looks like a typo, should be TGSI_OPCODE_UIF?
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to add a new
R600_RESOURCE_* flag instead of (ab)using R600_RESOURCE_FLAG_TRANSFER
for this.
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-by: Alex Deucher alexander.deuc...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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are
Tested-by: Michel Dänzer michel.daen...@amd.com
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array state validation if _DrawArrays
+ * is NULL. It also has no affect on performance, because attrib
'effect'
+ * bindings will be recalculated anyway.
+ */
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Libre software enthusiast
],
depth, PIPE_USAGE_STATIC, 0);
+ /* TODO: Setting the transfer flag is only a workaround till we get
tilling working */
Spelling: 'tiling'
With that fixed,
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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Libre
On Fre, 2013-04-26 at 11:51 +0200, Christian König wrote:
From: Christian König christian.koe...@amd.com
That is just not supported by the hardware.
Signed-off-by: Christian König christian.koe...@amd.com
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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in registers but in resource descriptors in a BO. In
theory, I think we could even support many more inputs than 32, but
let's just leave it at that for now.
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Kasanen c...@gmx.com
I pushed both your fixes, with the commit summaries amended to clarify
that the problem was only with non-standard libdrm installation
prefixes. Thanks!
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a integer SUB opcode, so the natural way for encoding that would
of course just be with a ADD with negate modifier on second arg, and I
bet your hw could do that one.
I agree it shouldn't matter that much how this is expressed in TGSI.
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AFAICT these new patterns and intrinsics should be sufficient for full
GLSL 1.30 support in radeonsi.
I suspect these will need some polishing, but I wanted to send them out
now for initial comments so they can hopefully make it into the LLVM 3.3
release.
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On Mon, 2013-05-06 at 16:07 -0700, Tom Stellard wrote:
On Mon, May 06, 2013 at 09:30:58AM -0700, Tom Stellard wrote:
On Mon, May 06, 2013 at 06:23:05PM +0200, Michel Dänzer wrote:
AFAICT these new patterns and intrinsics should be sufficient for full
GLSL 1.30 support in radeonsi
From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
test/CodeGen/R600/llvm.AMDGPU.imax.ll | 21 +
test/CodeGen/R600/llvm.AMDGPU.imin.ll | 21 +
test/CodeGen/R600/llvm.AMDGPU.trunc.ll | 22
On Mon, 2013-05-13 at 16:53 -0400, alexdeuc...@gmail.com wrote:
From: Alex Deucher alexander.deuc...@amd.com
Note: this is a candidate for the 9.1 branch
Signed-off-by: Alex Deucher alexander.deuc...@amd.com
For the series:
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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the new formats 'packed' or something along
those lines.
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On Don, 2013-05-16 at 10:59 -0400, Adam Jackson wrote:
On Thu, 2013-05-16 at 16:28 +0200, Michel Dänzer wrote:
On Don, 2013-05-16 at 09:06 -0400, Adam Jackson wrote:
This series introduces bytewise formats for framebuffers, and fixes the
vector representation on big-endian. No damage
From: Michel Dänzer michel.daen...@amd.com
4 more little piglits.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/si_state_draw.c | 7 +++
1 file changed, 3 insertions(+), 4 deletions(-)
diff --git a/src
From: Michel Dänzer michel.daen...@amd.com
17 more little piglits.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 1 -
src/gallium/drivers/radeonsi/radeonsi_shader.c | 62
From: Michel Dänzer michel.daen...@amd.com
Two more little piglits.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 1 -
src/gallium/drivers/radeonsi/radeonsi_shader.c | 4 +++-
src/gallium
From: Michel Dänzer michel.daen...@amd.com
Just enough to support an additional internal constant buffer for the user
clip planes.
NOTE: This is a candidate for the 9.1 branch.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/r600_buffer.c | 30
From: Marek Olšák mar...@gmail.com
and add assertions to prevent buffer overflow. This fixes corruption
of the si_shader struct.
NOTE: This is a candidate for the 9.1 branch.
[ Cherry-pick of r600g commit da33f9b919039442e9ab51f9b1d1c83a73607133 ]
Signed-off-by: Michel Dänzer michel.daen
On Mit, 2013-05-15 at 14:26 -0700, Tom Stellard wrote:
The attached patches add some new patterns and instructions for SI and
are a prerequisite for more invasive compute shader changes that I'm
working on.
Please Review.
The SI changes are
Reviewed-by: Michel Dänzer michel.daen
;
+ type.fixed = FALSE;
type.sign = TRUE;
+ type.norm = FALSE;
type.width = 32;
type.length = 1;
Might be safer to use memset? Either way:
NOTE: This is a candidate for the stable branches.
Reviewed-by: Michel Dänzer michel.daen...@amd.com
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non-packed formats (which only makes
sense if one presumes little endian byte order).
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as before, right? I suppose everything was busted before, so no net
change here
Exactly. :\
I think is_bitmask should be enough for that though, if that is
explicitly defined to imply host byte order, so no new field should be
necessary?
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From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 63 --
1 file changed, 50 insertions(+), 13 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src
From: Michel Dänzer michel.daen...@amd.com
Set up CB_SHADER_MASK register according to pixel shader exports, and enable
some minimal state for colour buffer 1 in case dual source blending is used.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi
From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 32 ++
1 file changed, 7 insertions(+), 25 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src
This series fixes a couple of problems in preparation, then adds the missing
functionality for GLSL 1.30 and finally enables it. This enables around 800
more piglit tests, keeping the overall passrate about the same as before.
[PATCH 1/7] radeonsi: Fix hardware state for dual source blending
From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pipe.h | 2 +-
src/gallium/drivers/radeonsi/si_state.c | 45
2 files changed, 27 insertions(+), 20 deletions(-)
diff --git
From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 34 --
1 file changed, 32 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src
From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 21 +
1 file changed, 17 insertions(+), 4 deletions(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_shader.c
b/src
From: Michel Dänzer michel.daen...@amd.com
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_pipe.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/gallium/drivers/radeonsi/radeonsi_pipe.c
b/src/gallium/drivers/radeonsi
offhand what would be the best way
to achieve that for the util_format stuff.
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;;
xnouveau)
AFAICT the r600g LLVM backend also needs this. Can you put it in a block
shared between r600g and radeonsi?
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On Die, 2013-06-04 at 01:15 -0700, Jose Fonseca wrote:
- Original Message -
Michel Dänzer mic...@daenzer.net writes:
On Fre, 2013-05-24 at 09:11 -0700, Jose Fonseca wrote:
I agree that with non-array formats, like B5G6R5 and R5G6B5, replacing
them with endian-variant BGR565
that.
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why I'd prefer making
the difference more explicit in the naming scheme. Sticking to LSB
first, BGRA might already look a little less scary? :)
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On Don, 2013-06-06 at 21:23 +1000, Jonathan Gray wrote:
On Thu, Jun 06, 2013 at 11:30:50AM +0200, Michel Dänzer wrote:
On Mit, 2013-06-05 at 15:00 +1000, Jonathan Gray wrote:
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but mesa
uses it with drmCommandWriteRead instead of drmCommandWrite
On Don, 2013-06-06 at 14:21 +0200, Michel Dänzer wrote:
On Don, 2013-06-06 at 21:23 +1000, Jonathan Gray wrote:
On Thu, Jun 06, 2013 at 11:30:50AM +0200, Michel Dänzer wrote:
On Mit, 2013-06-05 at 15:00 +1000, Jonathan Gray wrote:
RADEON_GEM_WAIT_IDLE is declared DRM_IOW but mesa
The most important difference to the previous version of these is that
whole quad mode is now enabled and M0 initialized appropriately for the
LDS instructions, which now allows all of the relevant piglit tests to
pass.
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I wonder how we should deal with LLVM 3.3 for these: Might we be able to
get the intrinsics into an LLVM 3.3.y release, or do we need to only enable
this stuff as of LLVM 3.4?
[PATCH 1/2] radeonsi: Handle TGSI_OPCODE_TXD
[PATCH 2/2] radeonsi: Handle TGSI_OPCODE_DDX/Y
From: Michel Dänzer michel.daen...@amd.com
One more little piglit.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
diff --git a/src/gallium/drivers/radeonsi
From: Michel Dänzer michel.daen...@amd.com
16 more little piglits.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_shader.c | 35 ++
src/gallium/drivers/radeonsi/radeonsi_shader.h | 1 +
src/gallium/drivers/radeonsi
On Sam, 2013-06-08 at 20:08 -0400, Tom Stellard wrote:
On Fri, Jun 07, 2013 at 05:48:05PM -0700, Tom Stellard wrote:
On Fri, Jun 07, 2013 at 05:24:42PM +0200, Michel Dänzer wrote:
@@ -1544,6 +1562,26 @@ def : Pat
sub3)
;
+class DDXY Intrinsic name
into implicitly thinking of the semantics of bitfields in
the C implementation they're using.
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Debian, X and DRI developer
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On Mon, 2013-06-17 at 01:11 +1000, Jonathan Gray wrote:
byteswap.h and bswap_32 aren't portable, replace them with calls to
gallium's util_bswap32 as suggested by Mark Kettenis. Lets these files
build on OpenBSD.
Signed-off-by: Jonathan Gray j...@jsg.id.au
Reviewed-by: Michel Dänzer
Michel Dänzer | http://www.amd.com
Libre software enthusiast | Debian, X and DRI developer
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that, the series looks good to me.
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Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Debian, X and DRI developer
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http
is not possible.
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Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Debian, X and DRI developer
From f4ca359c4536aa53122b654196f2e007d50976f8 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Michel=20D=C3=A4nzer?= michel.daen...@amd.com
Date
From: Michel Dänzer michel.daen...@amd.com
One more little piglit.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
v2: Only use the new functionality as of LLVM 3.4.
src/gallium/drivers/radeonsi/radeonsi_shader.c | 27 --
1 file changed, 25 insertions(+), 2
From: Michel Dänzer michel.daen...@amd.com
16 more little piglits.
Signed-off-by: Michel Dänzer michel.daen...@amd.com
---
src/gallium/drivers/radeonsi/radeonsi_compute.c | 2 +-
src/gallium/drivers/radeonsi/radeonsi_shader.c | 101 +++-
src/gallium/drivers/radeonsi
or PIPE_ENDIAN_SMALL.
Typo: PIPE_ENDIAN_LITTLE, not PIPE_ENDIAN_SMALL.
Other than that,
Reviewed-by: Michel Dänzer michel.daen...@amd.com
--
Earthling Michel Dänzer | http://www.amd.com
Libre software enthusiast | Debian, X and DRI developer
On Fre, 2013-06-28 at 14:37 -0700, Tom Stellard wrote:
On Wed, Jun 19, 2013 at 06:28:21PM +0200, Michel Dänzer wrote:
These patches implement enough of local memory support to allow radeonsi
to use that for computing derivatives, as suggested by Tom.
They also almost allow test
On Mit, 2013-07-10 at 08:15 -0700, Tom Stellard wrote:
On Wed, Jul 10, 2013 at 12:32:25PM +0200, Michel Dänzer wrote:
On Fre, 2013-06-28 at 14:37 -0700, Tom Stellard wrote:
On Wed, Jun 19, 2013 at 06:28:21PM +0200, Michel Dänzer wrote:
These patches implement enough of local memory
RADEON_MAX_CMDBUF_DWORDS (16 * 1024)
I guess this is okay for now, though in the long run we shouldn't leak
winsys/platform specific details into the Gallium pipe driver like this.
Don't you need to add $(LIBDRM_CFLAGS) to
src/gallium/drivers/r600/Makefile.am as well though?
--
Earthling Michel Dänzer
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