From: Nanley Chery nanley.g.ch...@intel.com
This patch series adds support for the KHR_texture_compression_astc_{ldr,hdr}
extensions. The last two commits enable support for Skylake systems.
Some rendering issues were encountered during testing, so there is some more
work to be done
From: Nanley Chery nanley.g.ch...@intel.com
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_defines.h | 36
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
.../glapi/gen/KHR_texture_compression_astc.xml | 40 ++
src/mapi/glapi/gen/Makefile.am | 1 +
src/mapi/glapi/gen/gl_API.xml | 2
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50 insertions(+)
diff --git a/src/mesa/main/texcompress.c
From: Nanley Chery nanley.g.ch...@intel.com
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 3 +
src/mesa/main/formats.c | 130
From: Nanley Chery nanley.g.ch...@intel.com
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 29 +
2 files changed, 7 insertions(+), 24 deletions(-)
diff --git a/src/mesa/main/format_info.py
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c | 3 +++
src/mesa/main/mtypes.h | 3 +++
2 files changed, 6 insertions(+)
diff --git a/src/mesa/main/extensions.c b/src/mesa/main/extensions.c
index c82416a
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 8ced579..d1dfb7a 100644
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src/mesa/drivers/dri/i965/intel_extensions.c
Hi Ilia,
Thanks for finding these errors. I'll have fixes in v2.
- Nanley
On Tue, May 19, 2015 at 7:07 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, May 19, 2015 at 8:48 PM, Nanley Chery nanleych...@gmail.com
wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off
Cheers,
-ilia
P.S. Congrats on your first public patch submission to mesa-dev :)
Thanks for the welcome!
- Nanley
On Tue, May 19, 2015 at 8:48 PM, Nanley Chery nanleych...@gmail.com
wrote:
From: Nanley Chery nanley.g.ch...@intel.com
This patch series adds support
On Tue, May 19, 2015 at 7:22 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, May 19, 2015 at 10:16 PM, Matt Turner matts...@gmail.com wrote:
On Tue, May 19, 2015 at 5:48 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley
From: Nanley Chery nanley.g.ch...@intel.com
Aligning with a non-power-of-two number is a general task that can be used in
various places. This commit is required for the next one.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_upload.c | 6 --
src
From: Nanley Chery nanley.g.ch...@intel.com
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN is changed to ALIGN_NPOT because alignment values are sometimes not
powers of two when working with ASTC.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c| 12 ++--
src/mesa/drivers
From: Nanley Chery nanley.g.ch...@intel.com
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
v2: remove extra newlines.
v3: follow existing coding style in translate_tex_format().
Signed-off-by: Nanley Chery
From: Nanley Chery nanley.g.ch...@intel.com
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Because the original
From: Nanley Chery nanley.g.ch...@intel.com
v2: alphabetize the extensions.
remove OES ASTC extension.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c | 2 ++
src/mesa/main/mtypes.h | 2 ++
2 files
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove extra newline.
v3: use bool instead of GLboolean.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
From: Nanley Chery nanley.g.ch...@intel.com
This patch series enables support for the KHR_texture_compression_astc_{ldr,hdr}
extensions on Skylake machines. This revision includes developer suggestions and
fixes rendering issues on previously untested systems. The sRGB issues were
fixed
From: Nanley Chery nanley.g.ch...@intel.com
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed
into the macro be a power of two in the comments. Using software assertions
verifies this to be the case.
v2: use static inline functions instead of gcc-specific statement expressions
From: Nanley Chery nanley.g.ch...@intel.com
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove OES ASTC extension reference.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
v2: add newlines to separate declarations, statments, and comments.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Reviewed-by: Neil
From: Nanley Chery nanley.g.ch...@intel.com
Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
v2: reintroduce brw.
don't include functional changes.
don't adjust function parameters or create a new function.
Signed-off
From: Nanley Chery nanley.g.ch...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa
From: Nanley Chery nanley.g.ch...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50
From: Nanley Chery nanley.g.ch...@intel.com
v2: correct the spelling of the sRGB variants.
remove spaces around = when setting the enum value.
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
.../glapi/gen
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with the coding style, functions that aren't directly visible
to the GL API should prefer the use of bool over GLboolean.
Suggested-by: Ian Romanick ian.d.roman...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src
From: Nanley Chery nanley.g.ch...@intel.com
Reviewed-by: Anuj Phogat anuj.pho...@gmail.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main
On Thu, Jun 25, 2015 at 12:37 AM, Pohjolainen, Topi
topi.pohjolai...@intel.com wrote:
On Wed, Jun 24, 2015 at 05:57:13PM -0700, Anuj Phogat wrote:
On Wed, Jun 24, 2015 at 3:51 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Although the horizontal
How about if I create a patch which puts the greater than 0 check into
is_power_of_two()?
(value 0) (value (value - 1)) == 0);
Thanks,
Nanley
On Wed, Jun 24, 2015 at 3:22 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Mon, Jun 22, 2015 at 4:02 PM, Nanley Chery nanleych...@gmail.com wrote
On Wed, Jun 24, 2015 at 3:43 PM, Anuj Phogat anuj.pho...@gmail.com wrote:
On Mon, Jun 22, 2015 at 4:02 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Aligning with a non-power-of-two number is a general task that can be used in
various places
From: Nanley Chery nanley.g.ch...@intel.com
Although the horizontal and vertical alignment fields are ignored here,
0 is a reserved value for them and may cause undefined behavior. Change
the default value to an abitrary valid one.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src
and
intel_horizontal_texture_alignment_unit are called from within the
top-level (and only within it), it would be assumed that the
references also apply to these functions.
On Tue, Jun 9, 2015 at 12:13 PM, Ian Romanick i...@freedesktop.org wrote:
On 06/01/2015 10:13 AM, Nanley Chery wrote:
From: Nanley
From: Nanley Chery nanley.g.ch...@intel.com
Aligning with a non-power-of-two number is a general task that can be used in
various places. This commit is required for the next one.
v2: add greater than 0 assertion (Anuj).
convert the macro to a static inline function.
Signed-off-by: Nanley
On Thu, Jun 11, 2015 at 8:56 AM, Neil Roberts n...@linux.intel.com wrote:
Hi Nanley,
Could you explain the reasoning behind this patch? I can't find any
mention of needing to align to the square of the block size in the docs.
Sure. I came to the conclusion that alignment must be squared due
I agree. This will be fixed in the next revision.
On Tue, Jun 9, 2015 at 12:03 PM, Ian Romanick i...@freedesktop.org wrote:
Should this patch be last? It looks like later patches fix bugs.
On 06/01/2015 10:13 AM, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove
aligned by the alignment term, right?
Thanks,
Nanley
On Mon, Jun 15, 2015 at 10:45 AM, Neil Roberts n...@linux.intel.com wrote:
Nanley Chery nanleych...@gmail.com writes:
Although most of the patch is incorrect, the following change is still
necessary isn't it?
if (mt-compressed) {
mip1_width
On Thu, Jun 11, 2015 at 9:04 AM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Jun 10, 2015 at 05:01:44PM -0700, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
On Gen9+, vertical and horizontal alignment values for compressed textures
are
equal to the pre-Gen9 value squared
My test results haven't been consistent and some of the failures don't seem
to match what's going on in this patch. I'll have to look into improving my
testing methods on SKL, but that's a separate issue. This patch makes sense.
Reviewed-by: Nanley Chery nanley.g.ch...@intel.com
src/mesa/drivers/dri/i965/brw_tex_layout.c | 20
1 file changed, 8 insertions(+), 12 deletions(-)
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c
b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 312a887..dffc699 100644
---
From: Nanley Chery nanley.g.ch...@intel.com
On Gen9+, vertical and horizontal alignment values for compressed textures are
equal to the pre-Gen9 value squared. Each miplevel must be aligned to this
value.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
This fixes an FXT1 Piglit test
Although most of the patch is incorrect, the following change is still
necessary isn't it?
if (mt-compressed) {
mip1_width = ALIGN(minify(mt-physical_width0, 1), mt-align_w) +
- ALIGN(minify(mt-physical_width0, 2), bw);
+ ALIGN(minify(mt-physical_width0,
Hey Neil,
While this patch does fix FXT1, it also regresses 21 other Piglit tests on SKL.
- Nanley
On Thu, Jun 11, 2015 at 8:59 AM, Neil Roberts n...@linux.intel.com wrote:
This function was trying to align the width and height to a multiple
of the block size for compressed textures. It was
. Once I do that then there are no regressions and only the
two FXT1 tests appear in the fixes.
It might be interesting to see if you can run some of the regressing
tests by hand after a reboot to see if they fail consistently.
Regards,
- Neil
Nanley Chery nanleych...@gmail.com writes:
Hey
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with commit 4ab8d59a23, vertical alignment values are equal to
four times the block height on Gen9+.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/brw_tex_layout.c | 7 +--
1 file changed, 5
From: Nanley Chery nanley.g.ch...@intel.com
Includes definition of the formats, updates to functions likely to be used, as
well as changes necessary for compilation.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 3 +
src/mesa/main/formats.c | 130
From: Nanley Chery nanley.g.ch...@intel.com
An ASTC block takes up 16 bytes for all block width and height configurations.
This size is not integrally divisible by all ASTC block widths. Therefore cpp
is changed to mean bytes per block if the texture is compressed.
Along with changing the cpp
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove extra newline.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 2 ++
src/mesa/main/formats.c | 28
2 files changed, 6 insertions(+), 24 deletions(-)
diff --git
From: Nanley Chery nanley.g.ch...@intel.com
ALIGN and ROUND_DOWN_TO both require that the alignment value passed into the
macro be a power of two in the comments. Using software assertions verifies
this to be the case.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main
From: Nanley Chery nanley.g.ch...@intel.com
Intel surface formats default to LDR unless there is hardware
support for HDR and the texture is able to be processed in HDR mode.
v2: remove extra newlines.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 114
1 file changed, 114 insertions(+)
diff --git a/src/mesa/main/texcompress.c b/src/mesa/main/texcompress.c
index
From: Nanley Chery nanley.g.ch...@intel.com
v2: correct the spelling of the sRGB variants.
remove spaces around = when setting the enum value.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
.../glapi/gen/KHR_texture_compression_astc.xml | 40 ++
src/mapi
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/glformats.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/src/mesa/main/glformats.c b/src/mesa/main/glformats.c
index 6a77c91..10e2a87 100644
From: Nanley Chery nanley.g.ch...@intel.com
v2: alphabetize the extensions.
remove OES ASTC extension.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/extensions.c | 2 ++
src/mesa/main/mtypes.h | 2 ++
2 files changed, 4 insertions(+)
diff --git a/src/mesa/main
From: Nanley Chery nanley.g.ch...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texcompress.c | 22 ++
src/mesa/main/teximage.c| 28
2 files changed, 50 insertions(+)
diff --git a/src/mesa/main/texcompress.c
From: Nanley Chery nanley.g.ch...@intel.com
This is necesary to initialize the gl_texture_image struct.
From the KHR_texture_compression_astc_ldr spec:
Added to Section 3.8.6, Compressed Texture Images
Add the tokens specified above to Table 3.16, Compressed Internal Formats.
In all
From: Nanley Chery nanley.g.ch...@intel.com
In this revision, comments have been taken into account and most rendering
issues have been fixed. Unfortunately, when rendering the reference sRGB
textures, the HW-loaded compressed versions are still rendered darker than
the pre-decoded SW ones
From: Nanley Chery nanley.g.ch...@intel.com
- Remove redundant checks and comments by grouping our calculations for
align_w and align_h wherever possible.
- Don't pass more parameters than necessary.
- Minor code simplifications.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src
From: Nanley Chery nanley.g.ch...@intel.com
This patch creates a new macro, FETCH_COMPRESSED - similar in nature
to the other FETCH_* macros. This reduces repetition in the code that
deals with compressed textures.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/swrast
From: Nanley Chery nanley.g.ch...@intel.com
v2: remove OES ASTC extension reference.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/drivers/dri/i965/intel_extensions.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/src/mesa/drivers/dri/i965/intel_extensions.c
b/src
Nice find. What do you think about putting this in a function to
reduce the code duplication?
- Nanley
On Wed, Jul 1, 2015 at 6:14 PM, Ben Widawsky b...@bwidawsk.net wrote:
On Wed, Jul 01, 2015 at 04:03:53PM -0700, Ben Widawsky wrote:
Certain compressed formats require this setting. The docs
From: Nanley Chery nanley.g.ch...@intel.com
All compressed formats return GL_FALSE. Remove all switch cases for
compressed formats. Compressed formats should be at the bottom of
the switch statement, so ordering is still preserved.
Cc: Jason Ekstrand jason.ekstr...@intel.com
Signed-off
From: Nanley Chery nanley.g.ch...@intel.com
Add the classes of compressed formats as layouts. This will make determining if
a texture is an ASTC format simpler.
Cc: Jason Ekstrand jason.ekstr...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/format_info.py | 4
From: Nanley Chery nanley.g.ch...@intel.com
Combine the adjacent cases which have the same GL type in the switch statemnt.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/formats.c | 152 ++--
1 file changed, 17 insertions
From: Nanley Chery nanley.g.ch...@intel.com
Only uncompressed formats have a non-void type and actual components per pixel.
Rename _mesa_format_to_type_and_comps to
_mesa_uncompressed_format_to_type_and_comps and require callers to check if
the format is not compressed.
Cc: Jason Ekstrand
, 2015 at 4:53 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Add the classes of compressed formats as layouts. This will make
determining if
a texture is an ASTC format simpler.
v2. simplify layout name construction (Ilia).
Cc: Jason Ekstrand
From: Nanley Chery nanley.g.ch...@intel.com
This function's cases for non-generic compressed formats duplicate
the GL to MESA translation in _mesa_glenum_to_compressed_format().
This patch replaces the switch cases with a call to the translation
function. There are no behavioral changes except
On Fri, Aug 14, 2015 at 4:00 PM, Chad Versace chad.vers...@intel.com
wrote:
On Tue 11 Aug 2015, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Only uncompressed formats have a non-void type and actual components per
pixel.
Rename _mesa_format_to_type_and_comps
Cc'ing Brian.
I'm planning to make a patch to implement the first (3-step) solution.
On Mon, Aug 17, 2015 at 3:45 PM, Nanley Chery nanleych...@gmail.com wrote:
On Fri, Aug 14, 2015 at 4:00 PM, Chad Versace chad.vers...@intel.com
wrote:
On Tue 11 Aug 2015, Nanley Chery wrote:
From: Nanley
The last line of the commit message should say:
GL_RGBA4_S3TC (0x83A3) - COMPRESSED_RGBA_S3TC_DXT5_EXT (0x83F3)
On Wed, Aug 12, 2015 at 4:19 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
This function's cases for non-generic compressed formats
From: Nanley Chery nanley.g.ch...@intel.com
All compressed formats return GL_FALSE and there isn't any evidence to
support that this behaviour would change. Remove all switch cases for
compressed formats.
v2. Since the exhaustive switch is removed, add a gtest to ensure
all formats
On Fri, Aug 14, 2015 at 4:09 PM, Chad Versace chad.vers...@intel.com
wrote:
On Tue 11 Aug 2015, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Combine the adjacent cases which have the same GL type in the switch
statemnt.
Signed-off-by: Nanley Chery nanley.g.ch
From: Nanley Chery nanley.g.ch...@intel.com
Only uncompressed formats have a non-void type and actual components per pixel.
Rename _mesa_format_to_type_and_comps to
_mesa_uncompressed_format_to_type_and_comps and require callers to check if
the format is not compressed.
v2. include compressed
From: Nanley Chery nanley.g.ch...@intel.com
We currently check that our format info table is sane during context
initialization in debug builds. Perform this check during
`make check` instead. This enables format testing in release builds
and removes the requirement of an exhuastive switch
From: Nanley Chery nanley.g.ch...@intel.com
All compressed formats return GL_FALSE and there isn't any evidence to
support that this behaviour would change. Remove all switch cases for
compressed formats.
v2. Since the exhaustive switch is removed, add a gtest to ensure
all formats
On Mon, Aug 17, 2015 at 11:54 AM, Chad Versace chad.vers...@intel.com
wrote:
On Tue 28 Jul 2015, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
According to the spec, Tex*Storage* commands are supported if the GL
implementation has support for immutable textures
Agreed. I've updated the patch. Thanks.
On Mon, Aug 17, 2015 at 11:39 AM, Chad Versace chad.vers...@intel.com
wrote:
On Tue 11 Aug 2015, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with the ASTC spec, this makes calls to TexImage*D
unsuccessful.
Implied
On Thu, Aug 20, 2015 at 11:34 AM, Emil Velikov emil.l.veli...@gmail.com
wrote:
2015-08-12 0:07 GMT+01:00 Nanley Chery nanleych...@gmail.com:
From: Nanley Chery nanley.g.ch...@intel.com
Combine the adjacent cases which have the same GL type in the switch
statemnt.
Signed-off-by: Nanley
From: Nanley Chery nanley.g.ch...@intel.com
Define two-thirds of the 2D Intel ASTC surface formats (LDR-only). This allows
a 1-to-1 mapping from the mesa format to the Intel format.
ASTC textures will default to being processed in LDR mode. If there is
hardware support for HDR/Full mode
From: Nanley Chery nanley.g.ch...@intel.com
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column 3D
From: Nanley Chery nanley.g.ch...@intel.com
According to the spec, Tex*Storage* commands are supported if the GL
implementation has support for immutable textures.
Signed-off-by: Nanley Chery nanley.g.ch...@intel.com
---
src/mesa/main/texformat.c | 56
From: Nanley Chery nanley.g.ch...@intel.com
The following patches add missing functionality to my prior ASTC patch series
needed to advertise support for the extension. The missing first patch was an
oversight, while the second patch is due to the release of a newer spec
revision.
The series
From: Nanley Chery nanley.g.ch...@intel.com
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column 3D
From: Nanley Chery nanley.g.ch...@intel.com
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column 3D
On Tue, Aug 11, 2015 at 4:16 PM, Ilia Mirkin imir...@alum.mit.edu wrote:
On Tue, Aug 11, 2015 at 7:07 PM, Nanley Chery nanleych...@gmail.com
wrote:
From: Nanley Chery nanley.g.ch...@intel.com
Add the classes of compressed formats as layouts. This will make
determining if
a texture
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful.
Implied by the spec, Generate[Texture]Mipmap and [Copy]TexSubImage*D calls
must be unsuccessful as well.
v2. actually force attempts to compress online to fail.
v3
This patch is a followup on this:
http://lists.freedesktop.org/archives/mesa-dev/2015-June/087055.html
On Tue, Aug 11, 2015 at 4:54 PM, Nanley Chery nanleych...@gmail.com wrote:
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with the ASTC spec, this makes calls to TexImage*D
From: Nanley Chery nanley.g.ch...@intel.com
This function would always report that a dimension or size error occurred
in glTexImage even when it was called from glCompressedTexImage. Replace
the static string with the dynamically determined caller name.
Signed-off-by: Nanley Chery nanley.g.ch
From: Nanley Chery nanley.g.ch...@intel.com
Add the classes of compressed formats as layouts. This will make determining if
a texture is an ASTC format simpler.
v2. simplify layout name construction (Ilia).
Cc: Jason Ekstrand jason.ekstr...@intel.com
Signed-off-by: Nanley Chery nanley.g.ch
From: Nanley Chery nanley.g.ch...@intel.com
In agreement with the ASTC spec, this makes calls to TexImage*D unsuccessful.
Implied by the spec, Generate[Texture]Mipmap and [Copy]TexSubImage*D calls
must be unsuccessful as well.
v2. actually force attempts to compress online to fail.
Signed-off
From: Nanley Chery nanley.g.ch...@intel.com
The ASTC spec was revised as follows:
Revision 2, April 28, 2015 - added CompressedTex{Sub,}Image3D to
commands accepting ASTC format tokens in the New Tokens section [...].
Support only exists in the HDR submode:
Add a second new column 3D
On Fri, Aug 21, 2015 at 2:12 PM, Chad Versace chad.vers...@intel.com
wrote:
On Wed 19 Aug 2015, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
We currently check that our format info table is sane during context
initialization in debug builds. Perform this check during
Thanks for pointing out these errors. I'll fix them in the next version.
On Fri, Aug 21, 2015 at 2:34 PM, Chad Versace chad.vers...@intel.com
wrote:
On Wed 19 Aug 2015, Nanley Chery wrote:
From: Nanley Chery nanley.g.ch...@intel.com
All compressed formats return GL_FALSE and there isn't
From: Nanley Chery nanley.g.ch...@intel.com
All compressed formats return GL_FALSE and there isn't any evidence to
support that this behaviour would change. Remove all switch cases for
compressed formats.
v2. Since the exhaustive switch is removed, add a gtest to ensure
all formats
From: Nanley Chery nanley.g.ch...@intel.com
We currently check that our format info table is sane during context
initialization in debug builds. Perform this check during
`make check` instead. This enables format testing in release builds
and removes the requirement of an exhuastive switch
1 - 100 of 1405 matches
Mail list logo
