Re: [Mesa-dev] r600g merged

: It assumed that there was always a depthbuffer available, resulting in a segfault if there wasn't. Here is my new depthbuffer patch: http://www.basnieuwenhuizen.nl/r600g-added-code-for-depthtesting-v3.patch - Bas Nieuwenhuizen ___ mesa-dev mailing list

[Mesa-dev] [PATCH 0/3] r600g: fix occlusion querying in the new design

These patches fix piglit test occlusion-query-discard in the new design of r600g. The evergreen code is only compile tested as I don't have one. Bas Nieuwenhuizen (3): r600g: set ENABLE_KILL in the shader state in the new design r600g: introduce query state in new design r600g: set

[Mesa-dev] [PATCH 3/3] r600g: set ENABLE_KILL on evergreen too

--- src/gallium/drivers/r600/evergreen_state.c |9 - 1 files changed, 8 insertions(+), 1 deletions(-) diff --git a/src/gallium/drivers/r600/evergreen_state.c b/src/gallium/drivers/r600/evergreen_state.c index 5026f21..d77129b 100644 --- a/src/gallium/drivers/r600/evergreen_state.c

[Mesa-dev] [PATCH] r600g: use dirty array to speed up emitting blocks

Emitting the dirty blocks sometimes accounted for about 30% percent of the time spent in r600_dri.so, so I made a seperate array with only the dirty blocks. --- src/gallium/drivers/r600/r600.h|2 ++ src/gallium/winsys/r600/drm/evergreen_hw_context.c | 18

[Mesa-dev] [PATCH] r600g: use dirty list to track dirty blocks

Got a speed up by tracking the dirty blocks in a seperate list instead of looping through all blocks. This version should work with block that get their dirty state disabled again and I added a dirty check during the flush as some blocks were already dirty. --- src/gallium/drivers/r600/r600.h

[Mesa-dev] [PATCH] r600g: track whether we need to update the shaders

The shaders only depend on the shader itself and the vertex_elements state and we don't need to emit the registers again if these are not changed. Tracking is also faster than the memcmp in r600_shader_update, so in some cases that expensive check doesn't have to be performed. I also optimized

[Mesa-dev] [PATCH] r600g: track whether we need to update the shaders (v2)

The shaders only depend on the shader itself, the vertex_elements state and flatshade and we don't need to emit the registers again if these are not changed. Tracking is also faster than the memcmp in r600_shader_update, so in some cases that expensive check doesn't have to be performed. I also

[Mesa-dev] [PATCH 1/3] r600g: don't flush caches if we already did so, even for a subset of the flags

Merging the flushes that are left doesn't seem to give a significant performance improvement --- src/gallium/winsys/r600/drm/r600_hw_context.c |4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/gallium/winsys/r600/drm/r600_hw_context.c

[Mesa-dev] [PATCH 2/3] r600g: also flush read caches if currently in use

If a resource isn't set again during a draw and the previous draw had it as colorbuffer, then the read caches wouldn't get invalidated. This hasn't surfaced as a bug yet because all resources are set again due to dirty marking with many false positives. It currently flushes all read caches,

[Mesa-dev] [PATCH 3/3] r600g: only emit blocks when they are changed

previously, we always emitted blocks that were set before a draw, after this patch the block only gets emitted when it is really changed. Also added a force parameter to r600_context_pipe_state_set, because the shader constant buffers need 2 registers in different blocks updated, even if only

Re: [Mesa-dev] [PATCH 3/3] r600g: only emit blocks when they are changed

On 04/18/11 12:14, Dave Airlie wrote: On Thu, Apr 14, 2011 at 4:36 AM, Bas Nieuwenhuizen b...@basnieuwenhuizen.nl wrote: previously, we always emitted blocks that were set before a draw, after this patch the block only gets emitted when it is really changed. Also added a force parameter

Re: [Mesa-dev] [PATCH v3 5/7] radeonsi: Implement DCC fast clear.

On Thu, Oct 22, 2015 at 12:12 PM, Marek Olšák wrote: >> diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c >> b/src/gallium/drivers/radeonsi/si_descriptors.c >> index 5548cba3..a277fa5 100644 >> --- a/src/gallium/drivers/radeonsi/si_descriptors.c >> +++

Re: [Mesa-dev] [PATCH v3 5/7] radeonsi: Implement DCC fast clear.

On Fri, Oct 23, 2015 at 12:50 PM, Marek Olšák <mar...@gmail.com> wrote: > On Fri, Oct 23, 2015 at 12:17 PM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> On Thu, Oct 22, 2015 at 12:12 PM, Marek Olšák <mar...@gmail.com> wrote: >>>>

Re: [Mesa-dev] [PATCH v3 5/7] radeonsi: Implement DCC fast clear.

On Fri, Oct 23, 2015 at 1:52 PM, Marek Olšák <mar...@gmail.com> wrote: > On Fri, Oct 23, 2015 at 1:30 PM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> On Fri, Oct 23, 2015 at 12:50 PM, Marek Olšák <mar...@gmail.com> wrote: >>> On Fri, Oct 23, 201

Re: [Mesa-dev] [PATCH v3 5/7] radeonsi: Implement DCC fast clear.

On Fri, Oct 23, 2015 at 4:57 PM, Marek Olšák <mar...@gmail.com> wrote: > On Fri, Oct 23, 2015 at 1:57 PM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> On Fri, Oct 23, 2015 at 1:52 PM, Marek Olšák <mar...@gmail.com> wrote: >>> On Fri, Oct 23, 20

[Mesa-dev] [PATCH v4] radeonsi: Implement DCC fast clear.

Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR still works. Furthermore, with DCC compression we can directly clear to a limited set of colors such that we do not need a postprocessing step. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/g

Re: [Mesa-dev] [PATCH v3 5/7] radeonsi: Implement DCC fast clear.

On Thu, Oct 22, 2015 at 12:12 PM, Marek Olšák <mar...@gmail.com> wrote: > On Wed, Oct 21, 2015 at 12:10 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl> wrote: >> Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR >> still works. Furthermor

[Mesa-dev] [PATCH v3 6/7] radeonsi: Add DCC decompression.

This is currently not needed but will be necessary when we have features that do not work with DCC enabled, such as image stores and sharing non-scanout surfaces. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_blit.c

[Mesa-dev] [PATCH v3 4/7] radeonsi: Enable DCC.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 2 ++ src/gallium/drivers/radeon/r600d_common.h | 1 + src/gallium/drivers/radeonsi/si_descriptors.c | 5 +++ src/g

[Mesa-dev] [PATCH v3 3/7] radeonsi: Add FLUSH_AND_INV_CB_DATA_TS for DCC.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_state_draw.c | 11 +++ 1 file changed, 11 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state_draw.c b/src/gallium/drivers/radeonsi/si_state_draw.c index ce6c98c..29c40d2

[Mesa-dev] [PATCH v3 5/7] radeonsi: Implement DCC fast clear.

Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR still works. Furthermore, with DCC compression we can directly clear to a limited set of colors such that we do not need a postprocessing step. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/g

[Mesa-dev] [PATCH v3 7/7] radeonsi: Add DCC compression tracking machinery.

Add a mask to track if a texture level is still in its decompressed state or that we would need to decompress again. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 1

[Mesa-dev] [PATCH v3 2/7] radeonsi: Disable operations that do not work with DCC.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_texture.c | 5 + src/gallium/drivers/radeonsi/cik_sdma.c | 3 ++- src/gallium/drivers/radeonsi/si_blit.c| 3 ++- src/gallium/drivers/radeonsi/si_dma.c | 3 ++- 4 files chang

[Mesa-dev] [PATCH v3 1/7] radeonsi: Allocate buffers for DCC.

As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. DCC is disabled for textures that can be shared as sharing the DCC buffers has not been implemented yet. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/d

[Mesa-dev] [PATCH v3 0/7] Add DCC support

SAA resolve if the destination is DCC compressed. - Only set ALPHA_IS_ON_MSB when needed. - Rework compression tracking and decompress to be optional. Bas Nieuwenhuizen (7): radeonsi: Allocate buffers for DCC. radeonsi: Disable operations that do not work with DCC. radeonsi:

Re: [Mesa-dev] [PATCH v3 1/7] radeonsi: Allocate buffers for DCC.

On Wed, Oct 21, 2015 at 9:56 AM, Axel Davy <axel.d...@ens.fr> wrote: > On 21/10/2015 00:10, Bas Nieuwenhuizen wrote: >> >> >> DCC is disabled for textures that can be shared as sharing the >> DCC buffers has not been implemented yet. >> >>

Re: [Mesa-dev] [PATCH 4/4] pipe: Add new bind flag for shared resources with flush_resource call

On Wed, Oct 21, 2015 at 12:28 PM, Axel Davy wrote: > +/* This flag indicates that in addition to being shared, the resource won't > be > + * read by any external process before we call flush_resource. This allows > + * things like compressing the buffer when drawing, while

Re: [Mesa-dev] [PATCH 4/4] pipe: Add new bind flag for shared resources with flush_resource call

My apologies, wrong term. I meant the front buffer of the X server in the non-compositing case. - Bas On Wed, Oct 21, 2015 at 1:26 PM, Axel Davy <axel.d...@ens.fr> wrote: > On 21/10/2015 13:16, Bas Nieuwenhuizen wrote: >> >> On Wed, Oct 21, 2015 at 12:28 PM, Axel Davy <

Re: [Mesa-dev] [PATCH 3/8] radeonsi: Enable DCC.

appended to the resource of a MSAA buffer. This has the secondary benefit of not needing to reference as many resources for command submission. Yours sincerely, Bas Nieuwenhuizen ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.or

[Mesa-dev] [PATCH v2 6/7] radeonsi: Add DCC decompress.

This is currently not needed but will be necessary when we have features that do not work with DCC enabled, such as image stores and sharing non-scanout surfaces. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_blit.c

[Mesa-dev] [PATCH v2 2/7] radeonsi: Disable operations that do not work with DCC.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_texture.c | 5 + src/gallium/drivers/radeonsi/cik_sdma.c | 3 ++- src/gallium/drivers/radeonsi/si_blit.c| 3 ++- src/gallium/drivers/radeonsi/si_dma.c | 3 ++- 4 files chang

[Mesa-dev] [PATCH v2 1/7] radeonsi: Allocate buffers for DCC.

As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_buffer_common.c | 21 +++ src/gallium/drivers/radeon/r600_pipe_common.h | 6 +++

[Mesa-dev] [PATCH v2 5/7] radeonsi: Implement DCC fast clear.

Uses the DCC buffer instead of the CMASK buffer. The ELIMINATE_FAST_CLEAR still works. Furthermore, with DCC compression we can directly clear to a limited set of colors such that we do not need a postprocessing step. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/g

[Mesa-dev] [PATCH v2 4/7] radeonsi: Enable DCC.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 2 ++ src/gallium/drivers/radeon/r600d_common.h | 1 + src/gallium/drivers/radeonsi/si_descriptors.c | 5 src/g

[Mesa-dev] [PATCH v2 3/7] radeonsi: Add a CACHE_FLUSH event

Needed for various DCC related operations. As invalidating the L2 cache seems unnecesary, this introduces a new flag to flush the cache without invalidating the L2 cache. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_pipe.h | 1

[Mesa-dev] [PATCH v2 7/7] radeonsi: Add DCC compression tracking machinery.

Add a mask to track if a texture level is still in its decompressed state or that we would need to decompress again. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 1

[Mesa-dev] [PATCH v2 0/7] Add DCC Support.

is DCC compressed. - Only set ALPHA_IS_ON_MSB when needed. - Rework compression tracking and decompress to be optional. Bas Nieuwenhuizen (7): radeonsi: Allocate buffers for DCC. radeonsi: Disable operations that do not work with DCC. radeonsi: Add a CACHE_FLUSH event radeonsi: Enable DCC

Re: [Mesa-dev] [PATCH v2 6/7] radeonsi: Add DCC decompress.

anymore for rendering. Do we still want patch 6 and 7 or should I drop them until we have an actual user? Yours sincerely, Bas Nieuwenhuizen ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org http://lists.freedesktop.org/mailman/listinfo/mesa-dev

Re: [Mesa-dev] [PATCH v2 6/7] radeonsi: Add DCC decompress.

, Xonotic regresses for me if I enable DCC for scanout surfaces. Yours sincerely, Bas Nieuwenhuizen On Mon, Oct 12, 2015 at 10:27 PM, Axel Davy <axel.d...@ens.fr> wrote: > On 12/10/2015 17:05, Bas Nieuwenhuizen wrote: >> >> Hi Marek, >> >> Thanks for the quick review.

[Mesa-dev] [PATCH 7/8] radeonsi: Do not decompress DCC textures for sampling.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_blit.c| 18 -- src/gallium/drivers/radeonsi/si_descriptors.c | 2 +- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_bli

[Mesa-dev] [PATCH 1/8] radeonsi: Allocate buffers for DCC.

As the alignment requirements can be 32 KiB or more, also adding an aligned buffer creation function. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_buffer_common.c | 20 +++ src/gallium/drivers/radeon/r600_pipe_common.h | 6 +++

[Mesa-dev] [PATCH 5/8] radeonsi: Invalidate the L2 cache on framebuffer change.

This is needed by DCC when using compressed textures. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_state.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_s

[Mesa-dev] [PATCH 8/8] radeonsi: Add DCC for multisampled textures.

The DCC fast clear for multisampled textures is still disabled as that does not work correctly yet. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_texture.c | 3 ++- src/gallium/drivers/radeonsi/si_blit.c | 2 +- src/gallium/

[Mesa-dev] [PATCH 4/8] radeonsi: Add DCC fast clear.

We cannot use the clear words from the cmask fast clear, so the fast clears are somewhat limited. The clear patterns have been taken from Catalyst traces. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_texture.

[Mesa-dev] [PATCH 3/8] radeonsi: Enable DCC.

The flags to be enabled in the control registers have been taken from Catalyst traces. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 1 + src/gallium/drivers/radeon/r600_texture.c | 2 ++ src/gallium/drivers/

[Mesa-dev] [PATCH 0/8] Add DCC support.

testing, I run this systemwide for a few days now and a piglit test minus a few tests that locked up on the baseline or seemingly gave random results, did not result in regressions. Bas Nieuwenhuizen (8): radeonsi: Allocate buffers for DCC. radeonsi: Add DCC compression tracking machinery. ra

[Mesa-dev] [PATCH 6/8] radeonsi: Add sampling of DCC compressed textures.

The values for resource word 6 have been taken from Catalyst traces. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 5 + src/gallium/drivers/radeonsi/si_pipe.h| 1 + src/gallium/drivers/radeonsi/si_state.c

[Mesa-dev] [PATCH 2/8] radeonsi: Add DCC compression tracking machinery.

As textures can be sampled without decompression and the fastclear bits can be erased without decompressing, so add a new set of flags. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 2 ++ src/gallium/drivers/radeonsi/cik_

Re: [Mesa-dev] [PATCH 0/8] Add DCC support.

On Friday, September 04, 2015 05:00:47 PM Alex Deucher wrote: > On Fri, Sep 4, 2015 at 3:47 PM, Bas Nieuwenhuizen > > <b...@basnieuwenhuizen.nl> wrote: > > This patch series enables delta color compression (DCC) for Vulcanic > > Islands GPU's. This should reduce m

Re: [Mesa-dev] [PATCH 3/8] radeonsi: Enable DCC.

renames that impact this series. On Thursday, September 24, 2015 01:36:31 AM Marek Olšák wrote: > On Fri, Sep 4, 2015 at 9:47 PM, Bas Nieuwenhuizen > > <b...@basnieuwenhuizen.nl> wrote: > > The flags to be enabled in the control registers have been taken from > > Catal

Re: [Mesa-dev] [PATCH 5/8] radeonsi: Invalidate the L2 cache on framebuffer change.

On Thursday, September 24, 2015 02:22:23 AM Marek Olšák wrote: > On Fri, Sep 4, 2015 at 9:47 PM, Bas Nieuwenhuizen > > <b...@basnieuwenhuizen.nl> wrote: > > This is needed by DCC when using compressed textures. > > > > Signed-off-by: Bas Nieuwe

Re: [Mesa-dev] [PATCH 3/8] radeonsi: Enable DCC.

On Thursday, September 24, 2015 07:24:50 PM Marek Olšák wrote: > On Thu, Sep 24, 2015 at 2:15 PM, Bas Nieuwenhuizen > > <b...@basnieuwenhuizen.nl> wrote: > > Hi Marek, > > > > Thanks for the review and my apologies, it seems I underestimated the > > p

Re: [Mesa-dev] [PATCH] radeonsi: fix images with level > 0

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Fri, Jun 3, 2016 at 7:20 PM, Marek Olšák <mar...@gmail.com> wrote: > From: Marek Olšák <marek.ol...@amd.com> > > This should fix spec@arb_shader_image_load_store@level.

Re: [Mesa-dev] [PATCH 04/12] radeonsi: add per-level dcc_enabled flags

; } > > return 0; > @@ -344,7 +347,8 @@ static int amdgpu_surface_init(struct radeon_winsys *rws, > AddrSurfInfoIn.flags.dccCompatible = !(surf->flags & > RADEON_SURF_Z_OR_SBUFFER) && > !(surf->flags & RADEON

Re: [Mesa-dev] [PATCH 2/4] gallium/radeon: don't discard DCC if an external user can write to it

On Mon, Jun 6, 2016 at 4:21 PM, Nicolai Hähnle wrote: > On 06.06.2016 16:16, Nicolai Hähnle wrote: >> >> Patches 1 & 2: >> >> Reviewed-by: Nicolai Hähnle > > > Hold off on patch #2 - how does this work together with shader image writes? > Then we're

Re: [Mesa-dev] [PATCH] radeonsi: Save and restore entire CE RAM.

On Mon, Jun 6, 2016 at 5:14 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > On 06.06.2016 00:28, Bas Nieuwenhuizen wrote: >> >> This fixes a problem with the CE preamble and restoring only stuff in the >> preamble when needed. >> >> To illustrate suppose w

[Mesa-dev] [PATCH] radeonsi: Reinitialize all descriptors in CE preamble.

all descriptor set buffers instead of load and store the entire CE RAM. - Leave the ce_ram_dirty tracking in place for the non-preamble case. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Cc: "12.0" <mesa-sta...@lists.freedesktop.org> --- Replaces "

Re: [Mesa-dev] [PATCH v3] radeonsi: Reinitialize all descriptors in CE preamble.

On Fri, Jun 10, 2016 at 11:35 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > On 09.06.2016 19:50, Bas Nieuwenhuizen wrote: >> >> This fixes a problem with the CE preamble and restoring only stuff in the >> preamble when needed. >> >> To illustrate suppose w

[Mesa-dev] [PATCH v3] radeonsi: Reinitialize all descriptors in CE preamble.

all descriptor set buffers instead of load and store the entire CE RAM. - Leave the ce_ram_dirty tracking in place for the non-preamble case. v3: - Fixed parameter alignment. - Rebased to master (Nicolai's descriptor series). Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen

Re: [Mesa-dev] [PATCH] radeonsi: don't generate "ret void undef"

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Mon, Jun 13, 2016 at 6:17 PM, Marek Olšák <mar...@gmail.com> wrote: > From: Marek Olšák <marek.ol...@amd.com> > > Use LLVMBuildRetVoid in epilogs and the GS copy shader and > si_llvm_build_ret otherwise

[Mesa-dev] [PATCH] radeonsi: Save and restore entire CE RAM.

1, but not between IB 1 and IB 2. The old code put the CE RAM loads in the preamble of IB 2. As the preamble of IB 1 does not have the loads and the preamble of IB 2 does not get executed, the old values are not load into CE RAM. Fix this by always restoring the entire CE RAM. Signed-off-by: Bas

Re: [Mesa-dev] [PATCH 0/9] radeonsi: speed up no-op descriptor uploads

o-benchmark I've seen more than a 30% > speedup. The difference in real-world applications should of course be > *much* smaller (1-2% if you're really lucky, if that). Please review! This series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Did you also try/benchm

[Mesa-dev] [PATCH] radeonsi: Don't offset OFFCHIP_BUFFERING on pre-VI cards.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=96239 --- src/gallium/drivers/radeonsi/si_state_shaders.c | 8 ++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/radeonsi/si_state_sha

Re: [Mesa-dev] [PATCH 03/10] radeonsi: set some image descriptor fields at bind time

h = base_level_info->nblk_x * block_width; > + > + state[1] &= C_008F14_BASE_ADDRESS_HI; > + state[3] &= C_008F1C_TILING_INDEX; > + state[4] &= C_008F20_PITCH; > + state[6] &= C_008F28_COMPRESSION_EN; Aren't these fields cleared already? Either way, the se

[Mesa-dev] [PATCH] gallium/ddebug: Add passthrough for query_memory_info.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/ddebug/dd_screen.c | 9 + 1 file changed, 9 insertions(+) diff --git a/src/gallium/drivers/ddebug/dd_screen.c b/src/gallium/drivers/ddebug/dd_screen.c index ebe090b..5a883bd 100644 --- a/src/g

Re: [Mesa-dev] [PATCH] radeonsi: Always reserve space for tessellation factors.

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Fri, May 27, 2016 at 12:40 PM, Marek Olšák <mar...@gmail.com> wrote: > And how about the attached patch? > > Marek > > On Fri, May 27, 2016 at 10:08 AM, Bas Nieuwenhuizen > <b...@basnieuwenhuizen.nl

[Mesa-dev] [PATCH v3 01/14] radeonsi: Add buffer for offchip storage between TCS and TES.

The buffer is quite large, but should only be allocated if the application uses tessellation. Most non-games don't. v2: - Use the correct register for SI. - Add define for block size. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol..

[Mesa-dev] [PATCH v3 14/14] radeonsi: Allow TES distribution between shader engines.

The R_028B50_VGT_TESS_DISTRIBUTION value is copied from amdgpu-pro. Smaller values in the ACCUM fields seem to decrease the performance advantage from this patch, higher values don't seem to matter. v2: Add distribution mode field enums. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen

[Mesa-dev] [PATCH v3 11/14] radeonsi: Enable dynamic HS.

This allows running the TES on different CU's than the TCS which results in performance improvements. v2: Only write the control word from one invocation. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/driv

[Mesa-dev] [PATCH v3 03/14] radeonsi: Define build_tbuffer_store_dwords earlier to support new users.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c | 138 +++ 1 file changed, 69 insertion

[Mesa-dev] [PATCH v3 08/14] radeonsi: Store inputs to memory when not using a TCS.

, or complexity to avoid that. The main body of the fixed function TCS is not that interesting to precompile anyway, since we do it on demand and it is very small. v2: Use u_bit_scan64. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> ---

[Mesa-dev] [PATCH v3 02/14] radeonsi: Add offchip tessellation parameters.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c| 28 - src/gallium/drivers/radeonsi/si_sh

[Mesa-dev] [PATCH v3 05/14] radeonsi: Use correct parameter index for LS_OUT_LAYOUT.

This happens to be in the right position, but that changes when TCS/TES get new parameters. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/galliu

[Mesa-dev] [PATCH v3 07/14] radeonsi: Add offchip buffer address calculation.

s possible. - Use tgsi_full_src_register_from_dst. - Remove some bad comments. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c | 124 +++ 1 file c

[Mesa-dev] [PATCH v3 06/14] radeonsi: Add user SGPR for the layout of the offchip buffer.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c | 3 +++ src/gallium/drivers/radeonsi/si_shader.h | 12 +++

[Mesa-dev] [PATCH v3 04/14] radeonsi: Add buffer load functions.

v2: - Use llvm.admgcn.buffer.load instrinsics for new LLVM. - Code style fixes. v3: - Code style fix. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_sh

[Mesa-dev] [PATCH v3 09/14] radeonsi: Use buffer loads and stores for passing data from TCS to TES.

and the LDS space, so we can load the outputs later, either due to the shader, of for wrting the tess factors. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/galliu

[Mesa-dev] [PATCH v3 12/14] radeonsi: Add barrier before writing the tess factors.

The factors may be stored to LDs by another invocation than the invocation for vertex 0. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_shader.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_shade

[Mesa-dev] [PATCH v3 00/14] radeonsi: offchip tessellation

that the optimal value for it differs between applications, and I don't have that many applications to check against. Any thoughts on the issue? - Bas Bas Nieuwenhuizen (14): radeonsi: Add buffer for offchip storage between TCS and TES. radeonsi: Add offchip tessellation parameters. radeonsi

[Mesa-dev] [PATCH v3 10/14] radeonsi: Remove LDS layout user SGPR's from TES.

They are unused. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> Reviewed-by: Nicolai Hähnle <nicolai.haeh...@amd.com> Reviewed-by: Marek Olšák <marek.ol...@amd.com> --- src/gallium/drivers/radeonsi/si_shader.c | 4 +--- src/gallium/drivers/radeonsi/si

[Mesa-dev] [PATCH v3 13/14] radeonsi: Process multiple patches per threadgroup.

for not splitting patches between waves. - Set max num_patches to 40 as in the proprietary driver. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_state_draw.c | 50 +++- 1 file changed, 35 insertions(+), 15 del

Re: [Mesa-dev] [PATCH] radeonsi: avoid divide by 0 in new TCS code.

I don't think this is the right approach as we shouldn't be getting 0 in the first place. At least for LDS the output size shoudl be at least 2 as we load the inner & outer tess factors while writing them to the tessellation factor ring. We could just do num_tcs_patch_outputs =

[Mesa-dev] [PATCH] radeonsi: Always reserve space for tessellation factors.

Those are always read for writing to the TF ring. Should fix CTS test GL45-CTS.shader_image_load_store.multiple-uniforms after a regression due to the new tessellation code. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- I have no CTS, so it actually is not tested w

[Mesa-dev] [PATCH 1/2] radeonsi: Add counter to check if a texture is bound to a framebuffer.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_pipe_common.h | 5 + src/gallium/drivers/radeonsi/si_pipe.c| 2 ++ src/gallium/drivers/radeonsi/si_state.c | 18 ++ src/gallium/drivers/radeonsi/si_s

[Mesa-dev] [PATCH 2/2] radeonsi: Decompress DCC textures in a render feedback loop.

By using a counter to quickly reject textures that are not bound to a framebuffer, the performance impact when binding sampler_views/images is not too large. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_blit.c

[Mesa-dev] [PATCH 1/2] gallium/os: Add CPU time functions

Adds functions to query the elapsed CPU time of the current process or thread. Implements Linux support only. To be used by the gallium HUD. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/auxiliary/os/os_time.c | 48 +

[Mesa-dev] [PATCH 2/2] gallium/hud: Add a frame time query

applications that do not do that. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/auxiliary/Makefile.sources | 1 + src/gallium/auxiliary/hud/hud_context.c| 18 + src/gallium/auxiliary/hud/hud_frame_time.c | 114 + src/gallium/aux

[Mesa-dev] [PATCH v2] radeonsi: Lazily re-set sampler views after disabling DCC

Clear DCC flags if necessary when binding a new sampler view. v2: Do not reset DCC flags of bound sampler views. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_texture.c | 2 -- src/gallium/drivers/radeonsi/si_descriptors.

[Mesa-dev] [PATCH] radeonsi: Lazily re-set sampler views after disabling DCC

Clear DCC flags if necessary when binding a new sampler_view. Also rebind all sampler views so that the sampler views that were already bound are also up to date. Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeon/r600_texture.c | 2 -- src/g

Re: [Mesa-dev] [PATCH 1/4] gallium/radeon: notify all contexts when cmasks are enabled/disabled

FWIW The series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> - Bas On Thu, Mar 10, 2016 at 12:07 AM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > From: Nicolai Hähnle <nicolai.haeh...@amd.com> > > There is an annoying corner case that I st

Re: [Mesa-dev] [PATCH 0/7] gallium, radeonsi: raise number of samplers to 32

Hi Nicolai, Patches 1-2 and 5-6 are Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> However, for increasing the limits there are several cases which still use signed shifts (i.e. 1 << ...) which is undefined behavior shifting into bit 31. mesa/st contains several of tho

Re: [Mesa-dev] [PATCH] radeonsi: don't use the real barrier instruction in tess ctrl shaders

This patch is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Thu, Apr 7, 2016 at 2:07 AM, Marek Olšák <mar...@gmail.com> wrote: > From: Marek Olšák <marek.ol...@amd.com> > > --- > src/gallium/drivers/radeonsi/si_shader.c | 8 > 1 file

Re: [Mesa-dev] [PATCH] radeonsi: fix bounds check in si_create_vertex_elements

Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> On Tue, Apr 12, 2016 at 7:25 PM, Nicolai Hähnle <nhaeh...@gmail.com> wrote: > From: Nicolai Hähnle <nicolai.haeh...@amd.com> > > This was triggered by > dEQP-GLES3.functional.vertex_array_objects.all_attrib

Re: [Mesa-dev] [PATCH v2 2/3] gallium: Add capability for ARB_robust_buffer_access_behavior

On Tue, Apr 12, 2016 at 6:09 PM, Roland Scheidegger <srol...@vmware.com> wrote: > Am 12.04.2016 um 16:23 schrieb Bas Nieuwenhuizen: >> On Tue, Apr 12, 2016 at 3:56 PM, Roland Scheidegger <srol...@vmware.com> >> wrote: >>> Am 12.04.2016 um 15:12 schrieb Bas Ni

Re: [Mesa-dev] [PATCH 1/2] radeonsi: fix NUM_SGPRS calculation once more

;info.num_input_sgprs + 2; /* VCC */ >> + >> + if (shader->config.scratch_bytes_per_wave) >> + min_sgprs += 2; /* scratch wave offset */ > > Sorry, this should be += 1. > > Marek With that changed, the series is Reviewed-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> - Bas ___ mesa-dev mailing list mesa-dev@lists.freedesktop.org https://lists.freedesktop.org/mailman/listinfo/mesa-dev

[Mesa-dev] [PATCH] radeonsi: Synchronize a streamout write after read hazard.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/drivers/radeonsi/si_descriptors.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/src/gallium/drivers/radeonsi/si_descriptors.c b/src/gallium/drivers/radeonsi/si_descriptors.c index cf898fd..a2c096f

[Mesa-dev] [PATCH v2 1/3] radeonsi: Expose the ARB_robust_buffer_access_behavior extension.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/mesa/main/extensions_table.h | 1 + src/mesa/main/mtypes.h | 1 + src/mesa/main/version.c | 2 +- 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mesa/main/extensions_table.h b/src/mes

[Mesa-dev] [PATCH v2 3/3] radeonsi: Mark ARB_robust_buffer_access_behavior as supported.

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- docs/GL3.txt | 2 +- docs/relnotes/11.3.0.html | 1 + src/gallium/drivers/radeonsi/si_pipe.c | 2 +- 3 files changed, 3 insertions(+), 2 deletions(-) diff --git a/docs/GL3.txt b/docs/G

[Mesa-dev] [PATCH v2 2/3] gallium: Add capability for ARB_robust_buffer_access_behavior

Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> --- src/gallium/docs/source/screen.rst | 5 + src/gallium/drivers/freedreno/freedreno_screen.c | 1 + src/gallium/drivers/i915/i915_screen.c | 1 + src/gallium/drivers/ilo/ilo_screen.c | 1

Re: [Mesa-dev] [PATCH v2 2/3] gallium: Add capability for ARB_robust_buffer_access_behavior

On Tue, Apr 12, 2016 at 3:56 PM, Roland Scheidegger <srol...@vmware.com> wrote: > Am 12.04.2016 um 15:12 schrieb Bas Nieuwenhuizen: >> Signed-off-by: Bas Nieuwenhuizen <b...@basnieuwenhuizen.nl> >> --- >> src/gallium/docs/source/screen.rst | 5 +

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