Re: [Mesa-dev] [PATCH 5/5] radv/gfx9: fix tile swizzle handling for gfx9

[Emil Velikov]

Hi Dave, Bas,

On 21 August 2017 at 13:59, Emil Velikov  wrote:
> Hi Dave,
>
> On 15 August 2017 at 06:26, Dave Airlie  wrote:
>> From: David Airlie 
>>
>> This sets the tile swizzle up properly for gfx9.
>>
>> Signed-off-by: Dave Airlie 
>> ---
> Can you please provide a backport of this patch for 17.2.
>
> There are a couple of conflict and with the "disable radv on Vega"
> landed, I did not want to leave things in a broken state.
>
Friendly reminder that this patch needs a backport for the 17.2 branch.
ATM everything's fine, since Vega support is disabled :-)

Just a note if you're planning to flip it on.

-Emil
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Re: [Mesa-dev] [PATCH 5/5] radv/gfx9: fix tile swizzle handling for gfx9

[Emil Velikov]

Hi Dave,

On 15 August 2017 at 06:26, Dave Airlie  wrote:
> From: David Airlie 
>
> This sets the tile swizzle up properly for gfx9.
>
> Signed-off-by: Dave Airlie 
> ---
Can you please provide a backport of this patch for 17.2.

There are a couple of conflict and with the "disable radv on Vega"
landed, I did not want to leave things in a broken state.

Thanks
Emil
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Re: [Mesa-dev] [PATCH 5/5] radv/gfx9: fix tile swizzle handling for gfx9

[Bas Nieuwenhuizen]

Reviewed-by: Bas Nieuwenhuizen 

for the series.

On Tue, Aug 15, 2017, at 07:26, Dave Airlie wrote:
> From: David Airlie 
> 
> This sets the tile swizzle up properly for gfx9.
> 
> Signed-off-by: Dave Airlie 
> ---
>  src/amd/vulkan/radv_device.c |  7 +++
>  src/amd/vulkan/radv_image.c  | 12 +---
>  2 files changed, 8 insertions(+), 11 deletions(-)
> 
> diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
> index 85ba165b4c..9bdad6ad6f 100644
> --- a/src/amd/vulkan/radv_device.c
> +++ b/src/amd/vulkan/radv_device.c
> @@ -2983,6 +2983,7 @@ radv_initialise_color_surface(struct radv_device
> *device,
>   S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
>  
>   cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset 
> >> 8;
> +   cb->cb_color_base |= iview->image->surface.tile_swizzle;
>   } else {
>   const struct legacy_surf_level *level_info = 
> >u.legacy.level[iview->base_mip];
>   unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
> @@ -3024,8 +3025,7 @@ radv_initialise_color_surface(struct radv_device
> *device,
>   va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
>   va += iview->image->dcc_offset;
>   cb->cb_dcc_base = va >> 8;
> -   if (device->physical_device->rad_info.chip_class < GFX9)
> -   cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
> +   cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
>  
>   uint32_t max_slice = radv_surface_layer_count(iview);
>   cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
> @@ -3041,8 +3041,7 @@ radv_initialise_color_surface(struct radv_device
> *device,
>   if (iview->image->fmask.size) {
>   va = device->ws->buffer_get_va(iview->bo) + 
> iview->image->offset + iview->image->fmask.offset;
>   cb->cb_color_fmask = va >> 8;
> -   if (device->physical_device->rad_info.chip_class < GFX9)
> -   cb->cb_color_fmask |=
> iview->image->fmask.tile_swizzle;
> +   cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
>   } else {
>   cb->cb_color_fmask = cb->cb_color_base;
>   }
> diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
> index 7a4b2d57a5..314964d64e 100644
> --- a/src/amd/vulkan/radv_image.c
> +++ b/src/amd/vulkan/radv_image.c
> @@ -215,9 +215,9 @@ si_set_mutable_tex_desc_fields(struct radv_device
> *device,
>   va += base_level_info->offset;
>  
>   state[0] = va >> 8;
> -   if (chip_class < GFX9)
> -   if (base_level_info->mode == RADEON_SURF_MODE_2D)
> -   state[0] |= image->surface.tile_swizzle;
> +   if (chip_class >= GFX9 ||
> +   base_level_info->mode == RADEON_SURF_MODE_2D)
> +   state[0] |= image->surface.tile_swizzle;
>   state[1] &= C_008F14_BASE_ADDRESS_HI;
>   state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
>  
> @@ -230,8 +230,7 @@ si_set_mutable_tex_desc_fields(struct radv_device
> *device,
>   meta_va += base_level_info->dcc_offset;
>   state[6] |= S_008F28_COMPRESSION_EN(1);
>   state[7] = meta_va >> 8;
> -   if (chip_class < GFX9)
> -   state[7] |= image->surface.tile_swizzle;
> +   state[7] |= image->surface.tile_swizzle;
>   }
>   }
>  
> @@ -479,8 +478,7 @@ si_make_texture_descriptor(struct radv_device
> *device,
>   }
>  
>   fmask_state[0] = va >> 8;
> -   if (device->physical_device->rad_info.chip_class < GFX9)
> -   fmask_state[0] |= image->fmask.tile_swizzle;
> +   fmask_state[0] |= image->fmask.tile_swizzle;
>   fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
>   S_008F14_DATA_FORMAT_GFX6(fmask_format) |
>   S_008F14_NUM_FORMAT_GFX6(num_format);
> -- 
> 2.13.5
> 
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[Mesa-dev] [PATCH 5/5] radv/gfx9: fix tile swizzle handling for gfx9

[Dave Airlie]

From: David Airlie 

This sets the tile swizzle up properly for gfx9.

Signed-off-by: Dave Airlie 
---
 src/amd/vulkan/radv_device.c |  7 +++
 src/amd/vulkan/radv_image.c  | 12 +---
 2 files changed, 8 insertions(+), 11 deletions(-)

diff --git a/src/amd/vulkan/radv_device.c b/src/amd/vulkan/radv_device.c
index 85ba165b4c..9bdad6ad6f 100644
--- a/src/amd/vulkan/radv_device.c
+++ b/src/amd/vulkan/radv_device.c
@@ -2983,6 +2983,7 @@ radv_initialise_color_surface(struct radv_device *device,
S_028C74_PIPE_ALIGNED(meta.pipe_aligned);
 
cb->cb_color_base += iview->image->surface.u.gfx9.surf_offset 
>> 8;
+   cb->cb_color_base |= iview->image->surface.tile_swizzle;
} else {
const struct legacy_surf_level *level_info = 
>u.legacy.level[iview->base_mip];
unsigned pitch_tile_max, slice_tile_max, tile_mode_index;
@@ -3024,8 +3025,7 @@ radv_initialise_color_surface(struct radv_device *device,
va = device->ws->buffer_get_va(iview->bo) + iview->image->offset;
va += iview->image->dcc_offset;
cb->cb_dcc_base = va >> 8;
-   if (device->physical_device->rad_info.chip_class < GFX9)
-   cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
+   cb->cb_dcc_base |= iview->image->surface.tile_swizzle;
 
uint32_t max_slice = radv_surface_layer_count(iview);
cb->cb_color_view = S_028C6C_SLICE_START(iview->base_layer) |
@@ -3041,8 +3041,7 @@ radv_initialise_color_surface(struct radv_device *device,
if (iview->image->fmask.size) {
va = device->ws->buffer_get_va(iview->bo) + 
iview->image->offset + iview->image->fmask.offset;
cb->cb_color_fmask = va >> 8;
-   if (device->physical_device->rad_info.chip_class < GFX9)
-   cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
+   cb->cb_color_fmask |= iview->image->fmask.tile_swizzle;
} else {
cb->cb_color_fmask = cb->cb_color_base;
}
diff --git a/src/amd/vulkan/radv_image.c b/src/amd/vulkan/radv_image.c
index 7a4b2d57a5..314964d64e 100644
--- a/src/amd/vulkan/radv_image.c
+++ b/src/amd/vulkan/radv_image.c
@@ -215,9 +215,9 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
va += base_level_info->offset;
 
state[0] = va >> 8;
-   if (chip_class < GFX9)
-   if (base_level_info->mode == RADEON_SURF_MODE_2D)
-   state[0] |= image->surface.tile_swizzle;
+   if (chip_class >= GFX9 ||
+   base_level_info->mode == RADEON_SURF_MODE_2D)
+   state[0] |= image->surface.tile_swizzle;
state[1] &= C_008F14_BASE_ADDRESS_HI;
state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
 
@@ -230,8 +230,7 @@ si_set_mutable_tex_desc_fields(struct radv_device *device,
meta_va += base_level_info->dcc_offset;
state[6] |= S_008F28_COMPRESSION_EN(1);
state[7] = meta_va >> 8;
-   if (chip_class < GFX9)
-   state[7] |= image->surface.tile_swizzle;
+   state[7] |= image->surface.tile_swizzle;
}
}
 
@@ -479,8 +478,7 @@ si_make_texture_descriptor(struct radv_device *device,
}
 
fmask_state[0] = va >> 8;
-   if (device->physical_device->rad_info.chip_class < GFX9)
-   fmask_state[0] |= image->fmask.tile_swizzle;
+   fmask_state[0] |= image->fmask.tile_swizzle;
fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
S_008F14_DATA_FORMAT_GFX6(fmask_format) |
S_008F14_NUM_FORMAT_GFX6(num_format);
-- 
2.13.5

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