protocol.
What do we do to make the L2 cache in the FPGA fabric coherent with
the caches in the ARM cores? Is it just particular messages? Or is
it a different kind of bus? Do we have to maintain a directory?
Thanks.
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Assistant Professor of Computer Science, Binghamton
I do not have current plans to do that. :) Currently, I'm using it
to probe various interesting research questions.
On Tue, Jan 26, 2016 at 2:47 PM, "Ing. Daniel Rozsnyó"
<dan...@rozsnyo.com> wrote:
> Will it be ever manufactured in silicon?
>
>
> On 01/26/2016 08:1
We project 600MHz on 45nm. Does that help make a projection for 350nm?
On Thu, Jan 21, 2016 at 12:48 PM, Troy Benjegerdes <ho...@hozed.org> wrote:
> On Wed, Jan 20, 2016 at 06:50:34PM -0500, Timothy Normand Miller wrote:
>> http://hardware.slashdot.org/story/16/01/20/171226/open-
http://hardware.slashdot.org/story/16/01/20/171226/open-source-gpu-used-for-research
People should write some useful comments maybe.
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to judge this.
On Thu, Apr 2, 2015 at 4:28 AM, Chris Matrakidis cmatr...@gmail.com wrote:
Reddit would probably be good, and maybe osnews.com.
What about Hacker News (news.ycombinator.com)?
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http
or so ago, and bookmarked
it. Nice to see this momentum building.
On Wed, Apr 1, 2015 at 7:44 PM, Timothy Normand Miller theo...@gmail.com
wrote:
Here's another draft of the announcement:
It seems like open source hardware has really begun to take off lately,
but this is because quite a few
the
reduction table is pre-computed (based on exhaustive search), we can extend
it to include arbitrary gates, including XOR (already there) and gates with
more than 2 inputs and therefore do reductions of arbitrary complexity, as
long as they can be done two levels of logic at a time.
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Open
,r30,1
end
# return from sub
macro .ret
jmp r31
end
@start = 10
@n = 3
ori r2,r0,@start
ori r1,r0,@n
@loop:
#addi r2,r2,1
.call @mysub
subi r1,r1,1
bne @loop
nop
halt
@mysub:
addi r2,r2,1
.ret
nop
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Assistant
with @.
Terrible burden, right?
On Wed, Jul 23, 2014 at 10:51 AM, Timothy Normand Miller theo...@gmail.com
wrote:
It's not all in yet, but release early/often/etc.
https://sourceforge.net/p/educpu/code/ci/master/tree/implementation/
Right now, I'm trying to get working pieces together. Gradually, I'll do
Sweet. I added the new license. There's also a small test case in there
now. That limited test works.
On Wed, Jul 23, 2014 at 3:53 PM, Peter Stuge pe...@stuge.se wrote:
Timothy Normand Miller wrote:
What sort of boilerplate should I add for a BSD or MIT license?
http://opensource.org
_reset) begin
if (_reset == 0) begin
result = 0;
flags = 0;
operation_out = 0;
end else begin
operation_out = operation_in;
flags = {ovl, zero, neg, carry};
result = value[31:0];
end
end
endmodule
--
Timothy Normand Miller, PhD
Assistant
operation_out = operation_in;
flags = {ovl, zero, neg, carry};
result = value[31:0];
end
end
endmodule
On Mon, Jul 21, 2014 at 10:41 AM, Timothy Normand Miller theo...@gmail.com
wrote:
Hi, All.
In case anyone would like to offer opinions on it, I'm designing a
super
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Oh, no. Not partial writes. Rather, ANDI does ({16'h, I} A), for
instance, while the others zero extend.
On Sun, Apr 21, 2013 at 3:34 PM, why...@f-cpu.org wrote:
Le 2013-04-21 19:47, Timothy Normand Miller a écrit :
Also, Im going to stipulate that the immediate logicals leave
BTW, I've changed some of the opcodes:
http://www.cs.binghamton.edu/~millerti/ins-formats4.pdf
On Fri, Apr 19, 2013 at 2:51 PM, Timothy Normand Miller
theo...@gmail.comwrote:
I've committed code changes that update the CPU version of OpenShader to
the latest ISA. To be honest, I haven't done
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with functional testing of the ALU. Also, i-cache and d-cache are
really just flat memories right now. And the ISA this implements is the
OLD one, so it doesn't correspond to Chris's latest assembler. I'll fix
that soon, I hope.
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indicating the tool they're related to,
like:
- OpenShader-LLVM (the LLVM compiler component that produces native ISA
code from LLVM code)
- OpenShader-ASM
Comments?
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.
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we need to focus, at least for the moment. Having a
functionally verified design is excellent motivation to take us seriously.
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. On the other hand, if we toss LI, then
we can salvage that one bit and use it for something else. But what?
MM
On 24 March 2013 01:38, Timothy Normand Miller theo...@gmail.com wrote:
Here's another version.
http://www.cs.binghamton.edu/~millerti/ins-formats3.pdf
* This time, I've gotten
2013/3/24 Timothy Normand Miller theo...@gmail.com
Here's another version.
http://www.cs.binghamton.edu/~millerti/ins-formats3.pdf
* This time, I've gotten rid of the WR bit and made R0 the bitbucket.
* The top bit of the instruction is 1 for an LL instruction that loads a
31-bit immediate
, Chris Matrakidis cmatr...@gmail.comwrote:
http://www.cs.binghamton.edu/~millerti/ins-formats2.pdf
What about adding instructions to convert between float and half float
(IEEE binary16)?
Best Regards,
Chris Matrakidis
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On Sat, Mar 23, 2013 at 12:13 AM, why...@f-cpu.org wrote:
Le 2013-03-23 00:13, Timothy Normand Miller a écrit :
http://www.cs.binghamton.edu/~**millerti/ins-formats2.pdfhttp://www.cs.binghamton.edu/~millerti/ins-formats2.pdf
I would advise adding a ANDN instruction : AND with one inverted
On Sat, Mar 23, 2013 at 10:17 AM, why...@f-cpu.org wrote:
Hi !
Le 2013-03-23 14:34, Timothy Normand Miller a écrit :
On Sat, Mar 23, 2013 at 12:13 AM, why...@f-cpu.org [3] wrote:
I would advise adding a ANDN instruction : AND with one inverted
operand. it speeds up boolean MUX sequences
) ; Two instruction pattern to load fp constant to
general purpose register
R2=FADD(R2,R3)
which after optimisation becomes
R1=LI(3f80)
R2=FADD(R1,R3)
My understanding is that it is very simple to implement this.
Best Regards,
Chris Matrakidis
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to avoid confusion with the
register R1.
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simpler. (Except for a barrel processor that doesn't have this
problem.)
Again, that's about it. There is a strong argument for being able to
cancel writeback, but very little call for a zero register input for _this_
ISA.
Let's see some more debate. :)
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No. What if you select a different register? At _best_ (assume we can
hack the internals of an SRAM block), it has the same circuit delay as
accessing any other register.
On Fri, Mar 22, 2013 at 6:24 PM, Peter Stuge pe...@stuge.se wrote:
Timothy Normand Miller wrote:
a register file lookup
way combine the
predicate value with the sign bit.
Best Regards,
Chris Matrakidis
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Is there a setting for gmail that is mailing-list aware? I'm going to see
if there's a way to make reply all the default.
On Mon, Mar 18, 2013 at 4:34 PM, why...@f-cpu.org wrote:
Le 2013-03-18 15:38, Nicolas Boulay a écrit :
2013/3/18 Timothy Normand Miller theo...@gmail.com
For CPUs
relatively
narrow milestones that we can meet so that we get working products sooner,
even if they're more limited. In the long run, we won't get your super HPC
evolved-from-GPU chip any sooner regardless of which path we take.
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. And discipline and focus and OCD
and limited sanity, etc. :)
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some infrastructure for testing.
Nicolas
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not want to create a dependency through this bottleneck.)
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On Sun, Mar 17, 2013 at 4:31 PM, why...@f-cpu.org wrote:
Le 2013-03-17 21:20, Timothy Normand Miller a écrit :
snip
I'm looking here at the bit compactness, because
less bits means less toggles and less power draw.
Using a bit for each instruction to throw the register away : 1
bit
On Sun, Mar 17, 2013 at 5:51 PM, Troy Benjegerdes ho...@hozed.org wrote:
On Sun, Mar 17, 2013 at 05:04:27PM -0400, Timothy Normand Miller wrote:
On Sun, Mar 17, 2013 at 4:31 PM, why...@f-cpu.org wrote:
Le 2013-03-17 21:20, Timothy Normand Miller a ?crit :
snip
I'm looking here
until the dependencies are resolved, which could take a LONG
TIME.
But for an in-order processor, CMOV is usually better because it avoids
branch overhead. For a GPU, it's even MORE useful because we can avoid
warp divergence.
Nicolas
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I'm using the OpenShader code in my class this semester, and I've also got
a student interested in contributing for independent study credit. I'll
check it into git sooner or later, but I still need to work out the
specifics on the IP with the university.
--
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, but it strikes me as just math, so
I don't feel right trying to restrict its use, especially since the next
person doing the same thing will do it in much the same way.
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Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu
:M] = outer[4*M+1:M] + middle_ext;
end
// Output
assign C = total;
endmodule
On Wed, Jan 23, 2013 at 11:43 AM, Eitan Adler li...@eitanadler.com wrote:
On 23 January 2013 11:35, Timothy Normand Miller theo...@gmail.com
wrote:
I think one of the reasons to use a permissive license
by Duskglow Consulting, LLC (www.duskglow.com)
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game
* 5 minutes of compiling linux/android/libreoffice/firefox (say 1ghz cpu)
On Tue, Jan 22, 2013 at 03:45:06AM -0500, Timothy Normand Miller wrote:
Consider the use cases and the prevalence of multiplies.
On Tue, Jan 22, 2013 at 1:49 AM, Troy Benjegerdes ho...@hozed.org
wrote:
well
might be helpful for
asic vs fpga design flexibility.
On Mon, Jan 14, 2013 at 07:38:26PM -0500, Timothy Normand Miller wrote:
If it's not something like 2x or 1/2x or other power of two, it's
basically
impossible to do in the middle of a pipeline. Also, keep in mind that we
reuse
them. Instead they tricked millions(?) of hipsters into *buying*
them, because they come with a colorful fruity logo.
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Open Graphics Project
:
The multiplier block in FPGA are rather fast, so running them at twice or
4 time the clock speed could be possible. In an asic they would actually
slow down the design because of the logic depth.
On 2013-01-13 18:52, Timothy Normand Miller wrote:
The multipliers are probably going
that know if this particular multiply is in the
critical path for some other computation, or if it's just a bulk-parallel
multiply where total energy matters more than time-to-answer?
On Mon, Jan 14, 2013 at 10:46:03AM -0500, Timothy Normand Miller wrote:
Where I have used these, the worst part
on B's sign after the 1's complement, is
that mathematically the same? I think the one place where this could go
wrong is if we subtract zero and don't consider that the sign doesn't
change, but I can special-case that.
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Clarification: This is INTEGER subtract.
On Sun, Jan 13, 2013 at 1:31 PM, Timothy Normand Miller
theo...@gmail.comwrote:
For addition, overflow is easy: Keep track of the sign bits of the inputs
and output and do a little logic. (Overflow if the A and B have the same
sign, while C has
I'm including my own updates, although several unfixed denormal bugs have
been found, and we have some clever hacks to make multiply handle denormal
as well. More code in next two emails
/*
Copyright 2013, Timothy Normand Miller, all rights reserved.
*/
`include defines.v
// Compare
V_out = (sign6==0 C6[32]) || (sign6==3 !C6[32]);
assign Z_out = C6[32:27] == 0 Z6;
endmodule
--
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Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/
Open Graphics Project
;
end
operation_out = operation_s9;
end
endmodule
--
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translate_on
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multiply?
Daniel
On 01/13/2013 09:46 PM, Timothy Normand Miller wrote:
// TODO: Actually use clock enables
module four_stage_signed_35x35_**multiply(
input clock,
input [34:0] A,
input [34:0] B,
output reg [69:0] P);
// Pipeline state 0: Perform all multiplies
assign out = C6[32:1];
assign carry_out = C6[33];
endmodule
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where we control it 100%, I was already going to
strongly recommend that a big chunk be invested in research at BU.
Assuming that others agreed to this, this makes it a wash financially.
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http
at proofs. Let's find a way to equate this here graph theory
problem with 3SAT so we can prove the solution is at least as hard as the
hardest problem where a correct answer can be verified in polynomial time.
PAIN!
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I think I solved this myself.
It's only cases where overflow is possible are when the result is greater
than 0xFF00. Since the maximum result is 0xFE01, rounding
cannot overflow.
On Tue, Jan 8, 2013 at 2:21 PM, Timothy Normand Miller theo...@gmail.comwrote:
Thank you
, mantC_s9};
assign flags = {prod_underflow_s9, overflow_s9, 6'b0};
assign operation_out = operation_s9;
endmodule
--
Timothy Normand Miller, PhD
Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/http://www.cse.ohio-state.edu/~millerti
Open
? In that case
sub_exponent is wrong - it should extend the exponents to 9 bits before
doing the subtraction. For example:
A = 0x88
B = 0x03
A - B = 0x85
(A - B)[7] is 1, so your routine would report this as A B.
Best regards,
Mark M.
On 6 January 2013 21:30, Timothy Normand Miller theo
On Mon, Jan 7, 2013 at 8:36 AM, John Culp john.c...@me.gatech.edu wrote:
Timothy Normand Miller wrote:
So basically, the GPU is a moving target anyway. We should focus on
meeting current scientific needs, publish lots of results, and then use
our
clout from this to get more funding
/subtract/multiply I'd like to
write a regression test that runs a couple of floating point validation
tools.
Sweet. BTW, regression tests, like most of this stuff, should be pure GPL.
Or you could do a more permissive license.
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suite as well. And do we want the simulator to be
under the AGPL to ensure that a modified version doesn't get networked
somewhere?
On Mon, Jan 7, 2013 at 10:23 PM, Troy Benjegerdes ho...@hozed.org wrote:
On Mon, Jan 07, 2013 at 04:34:04PM -0500, Timothy Normand Miller wrote:
On Mon, Jan 7
has no revenue potential, so
it's out of scope.
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On Sat, Jan 5, 2013 at 1:18 AM, John Culp john.c...@me.gatech.edu wrote:
Timothy Normand Miller wrote:
SHOULD I let NYS own this?
Short answer: yes
I think you should do what is best for your career. Neglecting what has
already been created, what you create going forward (apparently
sure that both can happen, ultimately requiring two right-shifts
(by zero or one, so they're cheap). But am I right about that?
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the most mistakes. :)
/*
Copyright 2013, Timothy Normand Miller, all rights reserved.
For now.
*/
// Fields for normalized numbers
`define MANTISSA_SIZE 23
`define EXPONENT_SIZE 8
`define MANTISSA 22:0
`define EXPONENT 30:23
`define SIGN 31
`define FP_SIZE 32
// Fields for denormalized
/
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Assistant
-only
version anyhow.
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to this work or in violation of licensing terms.
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, but urban enough that we
don't feel like we're completely isolated from civilization. But not
everyone feels that way. It's nice that NYC is a 4-hour bus ride away, but
I'd never want to live there.)
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Well, I see no harm in applying the AGPL to the simulator and other stuff.
The value to applying it to the hardware is, as has been said, possibly
more of a source of irony. :)
On Fri, Jan 4, 2013 at 3:20 PM, why...@f-cpu.org wrote:
Hello list,
Le 2013-01-04 20:59, Timothy Normand Miller
discussion and paranoia begin. :)
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wiki maintainer.
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, partly because it's connected with the OpenShader
subproject, partly because there's no maintainer for OGP's wiki.
On Mon, Dec 24, 2012 at 11:36 AM, Russell Miller rmil...@duskglow.comwrote:
On Dec 24, 2012, at 2:06 AM, Timothy Normand Miller theo...@gmail.com
wrote:
Maintaining the wiki
list
Open-graphics@duskglow.com
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,
and a simple single shader in VHDL that I can put on an XESS Xula2, or
Actel FPGA, or DE0-Nano board?
Or maybe drive a 32x16 LED matrix? There's lots of interesting applications
with high potential margins that don't look like a PCI-E video card.
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are likely to fund the work.
Thanks.
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GCC. We could learn a lot from these existing
simulators, if only we could run them.
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in before you have a set of goals might actually slow things down?
When Can I Buy One ;)
Gary
On Sun, Dec 9, 2012 at 11:19 AM, Timothy Normand Miller theo...@gmail.com
wrote:
Steam is a business that wants to sell games, and they have found that
Linux is a good platform. They have gotten
Thanks to Troy, I now have two subprojects defined:
https://sourceforge.net/p/openshader/wiki/subprojects/
I'm eager for some more ideas! Thanks!
On Sat, Dec 8, 2012 at 8:39 AM, Timothy Normand Miller theo...@gmail.comwrote:
I'm glad to see OGML having some traffic. Now, I'd like some
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Timothy Normand Miller, PhD
Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/http://www.cse.ohio-state.edu/~millerti
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...@stuge.se wrote:
Timothy Normand Miller wrote:
Besides OGD1, another example I like to point out is the lack of Free
logic synthesis software, competing with the likes of Mentor Graphics,
Cadence, and Synopsys. The main reason it doesn't exist
There exists an embryo, actually. It supports
-graphics
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Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
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Timothy Normand Miller, PhD
Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/http://www.cse.ohio-state.edu/~millerti
Open Graphics Project
(www.duskglow.com)
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Timothy Normand Miller, PhD
Assistant Professor of Computer Science, Binghamton University
http://www.cs.binghamton.edu/~millerti/http://www.cse.ohio-state.edu/~millerti
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there are many requestors, we need a way to
identify where the read data has to go back to.
On Sun, Nov 11, 2012 at 8:17 PM, Troy Benjegerdes ho...@hozed.org wrote:
On Thu, Nov 08, 2012 at 04:25:11PM -0500, Timothy Normand Miller wrote:
On Thu, Nov 8, 2012 at 3:43 PM, Troy Benjegerdes ho
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Timothy Normand Miller, PhD
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with others' designs, etc.).
If nothing else, it's probably worth paying what it'd cost me for tuition
at one of the world's best private engineering schools, and potentially
a hell of a lot more lucrative if say rev number 5 actually works and we
ship a million units.
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Timothy Normand
lots of people really excited.
On Fri, Nov 02, 2012 at 01:04:09PM -0400, Timothy Normand Miller wrote:
Well, we have enough knowledge and defined architecture that we could
probably code up a reasonable GPU in Verilog already. It's a matter of
allocating time and people
a chip before you have a
full functional simulator.
On Sat, Nov 3, 2012 at 6:55 PM, Troy Benjegerdes ho...@hozed.org wrote:
On Sat, Nov 03, 2012 at 01:44:18PM -0400, Timothy Normand Miller wrote:
Let's not make this so overwhelmingly large that no one sees the end.
That's one of the problems
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